2 * Copyright (C) 2012,2013 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/kernel.h>
19 #include <linux/clk.h>
22 #include <linux/of_address.h>
23 #include <linux/tegra-powergate.h>
31 #define TEGRA_POWER_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */
32 #define TEGRA_POWER_SYSCLK_OE (1 << 11) /* system clock enable */
33 #define TEGRA_POWER_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */
34 #define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */
35 #define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
38 #define PMC_CTRL_INTR_LOW (1 << 17)
39 #define PMC_PWRGATE_TOGGLE 0x30
40 #define PMC_PWRGATE_TOGGLE_START (1 << 8)
41 #define PMC_REMOVE_CLAMPING 0x34
42 #define PMC_PWRGATE_STATUS 0x38
44 #define PMC_CPUPWRGOOD_TIMER 0xc8
45 #define PMC_CPUPWROFF_TIMER 0xcc
47 static u8 tegra_cpu_domains[] = {
48 0xFF, /* not available for CPU0 */
53 static DEFINE_SPINLOCK(tegra_powergate_lock);
55 static void __iomem *tegra_pmc_base;
56 static bool tegra_pmc_invert_interrupt;
57 static struct clk *tegra_pclk;
60 u32 cpu_good_time; /* CPU power good time in uS */
61 u32 cpu_off_time; /* CPU power off time in uS */
62 u32 core_osc_time; /* Core power good osc time in uS */
63 u32 core_pmu_time; /* Core power good pmu time in uS */
64 u32 core_off_time; /* Core power off time in uS */
65 bool corereq_high; /* Core power request active-high */
66 bool sysclkreq_high; /* System clock request active-high */
67 bool combined_req; /* Combined pwr req for CPU & Core */
68 bool cpu_pwr_good_en; /* CPU power good signal is enabled */
69 u32 lp0_vec_phy_addr; /* The phy addr of LP0 warm boot code */
70 u32 lp0_vec_size; /* The size of LP0 warm boot code */
71 enum tegra_suspend_mode suspend_mode;
73 static struct pmc_pm_data pmc_pm_data;
75 static inline u32 tegra_pmc_readl(u32 reg)
77 return readl(tegra_pmc_base + reg);
80 static inline void tegra_pmc_writel(u32 val, u32 reg)
82 writel(val, tegra_pmc_base + reg);
85 static int tegra_pmc_get_cpu_powerdomain_id(int cpuid)
87 if (cpuid <= 0 || cpuid >= num_possible_cpus())
89 return tegra_cpu_domains[cpuid];
92 static bool tegra_pmc_powergate_is_powered(int id)
94 return (tegra_pmc_readl(PMC_PWRGATE_STATUS) >> id) & 1;
97 static int tegra_pmc_powergate_set(int id, bool new_state)
102 spin_lock_irqsave(&tegra_powergate_lock, flags);
104 old_state = tegra_pmc_powergate_is_powered(id);
105 WARN_ON(old_state == new_state);
107 tegra_pmc_writel(PMC_PWRGATE_TOGGLE_START | id, PMC_PWRGATE_TOGGLE);
109 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
114 static int tegra_pmc_powergate_remove_clamping(int id)
119 * Tegra has a bug where PCIE and VDE clamping masks are
120 * swapped relatively to the partition ids.
122 if (id == TEGRA_POWERGATE_VDEC)
123 mask = (1 << TEGRA_POWERGATE_PCIE);
124 else if (id == TEGRA_POWERGATE_PCIE)
125 mask = (1 << TEGRA_POWERGATE_VDEC);
129 tegra_pmc_writel(mask, PMC_REMOVE_CLAMPING);
134 bool tegra_pmc_cpu_is_powered(int cpuid)
138 id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
141 return tegra_pmc_powergate_is_powered(id);
144 int tegra_pmc_cpu_power_on(int cpuid)
148 id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
151 return tegra_pmc_powergate_set(id, true);
154 int tegra_pmc_cpu_remove_clamping(int cpuid)
158 id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
161 return tegra_pmc_powergate_remove_clamping(id);
164 void tegra_pmc_restart(enum reboot_mode mode, const char *cmd)
168 val = tegra_pmc_readl(0);
170 tegra_pmc_writel(val, 0);
173 #ifdef CONFIG_PM_SLEEP
174 static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
176 unsigned long long ticks;
177 unsigned long long pclk;
178 static unsigned long tegra_last_pclk;
180 if (WARN_ON_ONCE(rate <= 0))
185 if ((rate != tegra_last_pclk)) {
186 ticks = (us_on * pclk) + 999999ull;
187 do_div(ticks, 1000000);
188 tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER);
190 ticks = (us_off * pclk) + 999999ull;
191 do_div(ticks, 1000000);
192 tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER);
195 tegra_last_pclk = pclk;
198 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
200 return pmc_pm_data.suspend_mode;
203 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
205 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
208 pmc_pm_data.suspend_mode = mode;
211 void tegra_pmc_suspend(void)
213 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
216 void tegra_pmc_resume(void)
218 tegra_pmc_writel(0x0, PMC_SCRATCH41);
221 void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
224 unsigned long rate = 0;
226 reg = tegra_pmc_readl(PMC_CTRL);
227 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
228 reg &= ~TEGRA_POWER_EFFECT_LP0;
230 switch (tegra_chip_id) {
236 csr_reg = flowctrl_read_cpu_csr(0);
237 csr_reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
238 csr_reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
239 flowctrl_write_cpu_csr(0, csr_reg);
244 case TEGRA_SUSPEND_LP1:
247 case TEGRA_SUSPEND_LP2:
248 rate = clk_get_rate(tegra_pclk);
254 set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time,
257 tegra_pmc_writel(reg, PMC_CTRL);
260 void tegra_pmc_suspend_init(void)
264 /* Always enable CPU power request */
265 reg = tegra_pmc_readl(PMC_CTRL);
266 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
267 tegra_pmc_writel(reg, PMC_CTRL);
269 reg = tegra_pmc_readl(PMC_CTRL);
271 if (!pmc_pm_data.sysclkreq_high)
272 reg |= TEGRA_POWER_SYSCLK_POLARITY;
274 reg &= ~TEGRA_POWER_SYSCLK_POLARITY;
276 /* configure the output polarity while the request is tristated */
277 tegra_pmc_writel(reg, PMC_CTRL);
279 /* now enable the request */
280 reg |= TEGRA_POWER_SYSCLK_OE;
281 tegra_pmc_writel(reg, PMC_CTRL);
285 static const struct of_device_id matches[] __initconst = {
286 { .compatible = "nvidia,tegra124-pmc" },
287 { .compatible = "nvidia,tegra114-pmc" },
288 { .compatible = "nvidia,tegra30-pmc" },
289 { .compatible = "nvidia,tegra20-pmc" },
293 void __init tegra_pmc_init_irq(void)
295 struct device_node *np;
298 np = of_find_matching_node(NULL, matches);
301 tegra_pmc_base = of_iomap(np, 0);
303 tegra_pmc_invert_interrupt = of_property_read_bool(np,
304 "nvidia,invert-interrupt");
306 val = tegra_pmc_readl(PMC_CTRL);
307 if (tegra_pmc_invert_interrupt)
308 val |= PMC_CTRL_INTR_LOW;
310 val &= ~PMC_CTRL_INTR_LOW;
311 tegra_pmc_writel(val, PMC_CTRL);
314 void __init tegra_pmc_init(void)
316 struct device_node *np;
318 enum tegra_suspend_mode suspend_mode;
319 u32 core_good_time[2] = {0, 0};
320 u32 lp0_vec[2] = {0, 0};
322 np = of_find_matching_node(NULL, matches);
325 tegra_pclk = of_clk_get_by_name(np, "pclk");
326 WARN_ON(IS_ERR(tegra_pclk));
328 /* Grabbing the power management configurations */
329 if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) {
330 suspend_mode = TEGRA_SUSPEND_NONE;
334 suspend_mode = TEGRA_SUSPEND_LP0;
337 suspend_mode = TEGRA_SUSPEND_LP1;
340 suspend_mode = TEGRA_SUSPEND_LP2;
343 suspend_mode = TEGRA_SUSPEND_NONE;
347 suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode);
349 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop))
350 suspend_mode = TEGRA_SUSPEND_NONE;
351 pmc_pm_data.cpu_good_time = prop;
353 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop))
354 suspend_mode = TEGRA_SUSPEND_NONE;
355 pmc_pm_data.cpu_off_time = prop;
357 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
358 core_good_time, ARRAY_SIZE(core_good_time)))
359 suspend_mode = TEGRA_SUSPEND_NONE;
360 pmc_pm_data.core_osc_time = core_good_time[0];
361 pmc_pm_data.core_pmu_time = core_good_time[1];
363 if (of_property_read_u32(np, "nvidia,core-pwr-off-time",
365 suspend_mode = TEGRA_SUSPEND_NONE;
366 pmc_pm_data.core_off_time = prop;
368 pmc_pm_data.corereq_high = of_property_read_bool(np,
369 "nvidia,core-power-req-active-high");
371 pmc_pm_data.sysclkreq_high = of_property_read_bool(np,
372 "nvidia,sys-clock-req-active-high");
374 pmc_pm_data.combined_req = of_property_read_bool(np,
375 "nvidia,combined-power-req");
377 pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np,
378 "nvidia,cpu-pwr-good-en");
380 if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec,
381 ARRAY_SIZE(lp0_vec)))
382 if (suspend_mode == TEGRA_SUSPEND_LP0)
383 suspend_mode = TEGRA_SUSPEND_LP1;
385 pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0];
386 pmc_pm_data.lp0_vec_size = lp0_vec[1];
388 pmc_pm_data.suspend_mode = suspend_mode;