2 * drivers/powergate/tegra-powergate.c
4 * Copyright (c) 2010 Google, Inc
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/clk.h>
22 #include <linux/debugfs.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
27 #include <linux/seq_file.h>
28 #include <linux/spinlock.h>
31 #include <mach/iomap.h>
32 #include <mach/powergate.h>
36 #define PWRGATE_TOGGLE 0x30
37 #define PWRGATE_TOGGLE_START (1 << 8)
39 #define REMOVE_CLAMPING 0x34
41 #define PWRGATE_STATUS 0x38
43 static int tegra_num_powerdomains;
44 static int tegra_num_cpu_domains;
45 static u8 *tegra_cpu_domains;
46 static u8 tegra30_cpu_domains[] = {
53 static DEFINE_SPINLOCK(tegra_powergate_lock);
55 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
57 static u32 pmc_read(unsigned long reg)
59 return readl(pmc + reg);
62 static void pmc_write(u32 val, unsigned long reg)
64 writel(val, pmc + reg);
67 static int tegra_powergate_set(int id, bool new_state)
72 spin_lock_irqsave(&tegra_powergate_lock, flags);
74 status = pmc_read(PWRGATE_STATUS) & (1 << id);
76 if (status == new_state) {
77 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
81 pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
83 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
88 int tegra_powergate_power_on(int id)
90 if (id < 0 || id >= tegra_num_powerdomains)
93 return tegra_powergate_set(id, true);
96 int tegra_powergate_power_off(int id)
98 if (id < 0 || id >= tegra_num_powerdomains)
101 return tegra_powergate_set(id, false);
104 int tegra_powergate_is_powered(int id)
108 if (id < 0 || id >= tegra_num_powerdomains)
111 status = pmc_read(PWRGATE_STATUS) & (1 << id);
115 int tegra_powergate_remove_clamping(int id)
119 if (id < 0 || id >= tegra_num_powerdomains)
123 * Tegra 2 has a bug where PCIE and VDE clamping masks are
124 * swapped relatively to the partition ids
126 if (id == TEGRA_POWERGATE_VDEC)
127 mask = (1 << TEGRA_POWERGATE_PCIE);
128 else if (id == TEGRA_POWERGATE_PCIE)
129 mask = (1 << TEGRA_POWERGATE_VDEC);
133 pmc_write(mask, REMOVE_CLAMPING);
138 /* Must be called with clk disabled, and returns with clk enabled */
139 int tegra_powergate_sequence_power_up(int id, struct clk *clk)
143 tegra_periph_reset_assert(clk);
145 ret = tegra_powergate_power_on(id);
149 ret = clk_prepare_enable(clk);
155 ret = tegra_powergate_remove_clamping(id);
160 tegra_periph_reset_deassert(clk);
165 clk_disable_unprepare(clk);
167 tegra_powergate_power_off(id);
172 int tegra_cpu_powergate_id(int cpuid)
174 if (cpuid > 0 && cpuid < tegra_num_cpu_domains)
175 return tegra_cpu_domains[cpuid];
180 int __init tegra_powergate_init(void)
182 switch (tegra_chip_id) {
184 tegra_num_powerdomains = 7;
187 tegra_num_powerdomains = 14;
188 tegra_num_cpu_domains = 4;
189 tegra_cpu_domains = tegra30_cpu_domains;
192 /* Unknown Tegra variant. Disable powergating */
193 tegra_num_powerdomains = 0;
200 #ifdef CONFIG_DEBUG_FS
202 static const char * const *powergate_name;
204 static const char * const powergate_name_t20[] = {
205 [TEGRA_POWERGATE_CPU] = "cpu",
206 [TEGRA_POWERGATE_3D] = "3d",
207 [TEGRA_POWERGATE_VENC] = "venc",
208 [TEGRA_POWERGATE_VDEC] = "vdec",
209 [TEGRA_POWERGATE_PCIE] = "pcie",
210 [TEGRA_POWERGATE_L2] = "l2",
211 [TEGRA_POWERGATE_MPE] = "mpe",
214 static const char * const powergate_name_t30[] = {
215 [TEGRA_POWERGATE_CPU] = "cpu0",
216 [TEGRA_POWERGATE_3D] = "3d0",
217 [TEGRA_POWERGATE_VENC] = "venc",
218 [TEGRA_POWERGATE_VDEC] = "vdec",
219 [TEGRA_POWERGATE_PCIE] = "pcie",
220 [TEGRA_POWERGATE_L2] = "l2",
221 [TEGRA_POWERGATE_MPE] = "mpe",
222 [TEGRA_POWERGATE_HEG] = "heg",
223 [TEGRA_POWERGATE_SATA] = "sata",
224 [TEGRA_POWERGATE_CPU1] = "cpu1",
225 [TEGRA_POWERGATE_CPU2] = "cpu2",
226 [TEGRA_POWERGATE_CPU3] = "cpu3",
227 [TEGRA_POWERGATE_CELP] = "celp",
228 [TEGRA_POWERGATE_3D1] = "3d1",
231 static int powergate_show(struct seq_file *s, void *data)
235 seq_printf(s, " powergate powered\n");
236 seq_printf(s, "------------------\n");
238 for (i = 0; i < tegra_num_powerdomains; i++)
239 seq_printf(s, " %9s %7s\n", powergate_name[i],
240 tegra_powergate_is_powered(i) ? "yes" : "no");
244 static int powergate_open(struct inode *inode, struct file *file)
246 return single_open(file, powergate_show, inode->i_private);
249 static const struct file_operations powergate_fops = {
250 .open = powergate_open,
253 .release = single_release,
256 int __init tegra_powergate_debugfs_init(void)
260 switch (tegra_chip_id) {
262 powergate_name = powergate_name_t20;
265 powergate_name = powergate_name_t30;
269 if (powergate_name) {
270 d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,