2 * arch/arm/mach-tegra/sleep.S
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 * Copyright (c) 2011, Google, Inc.
7 * Author: Colin Cross <ccross@android.com>
8 * Gary King <gking@nvidia.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
25 #include <linux/linkage.h>
27 #include <asm/assembler.h>
28 #include <asm/cache.h>
30 #include <asm/hardware/cache-l2x0.h>
37 #define CLK_RESET_CCLK_BURST 0x20
38 #define CLK_RESET_CCLK_DIVIDER 0x24
40 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
42 * tegra_disable_clean_inv_dcache
44 * disable, clean & invalidate the D-cache
46 * Corrupted registers: r1-r3, r6, r8, r9-r11
48 ENTRY(tegra_disable_clean_inv_dcache)
49 stmfd sp!, {r0, r4-r5, r7, r9-r11, lr}
52 /* Disable the D-cache */
53 mrc p15, 0, r2, c1, c0, 0
55 mcr p15, 0, r2, c1, c0, 0
58 /* Flush the D-cache */
59 cmp r0, #TEGRA_FLUSH_CACHE_ALL
60 blne v7_flush_dcache_louis
61 bleq v7_flush_dcache_all
63 /* Trun off coherency */
66 ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc}
67 ENDPROC(tegra_disable_clean_inv_dcache)
70 #ifdef CONFIG_PM_SLEEP
72 * tegra_sleep_cpu_finish(unsigned long v2p)
74 * enters suspend in LP2 by turning off the mmu and jumping to
75 * tegra?_tear_down_cpu
77 ENTRY(tegra_sleep_cpu_finish)
79 /* Flush and disable the L1 data cache */
80 mov r0, #TEGRA_FLUSH_CACHE_ALL
81 bl tegra_disable_clean_inv_dcache
84 mov32 r6, tegra_tear_down_cpu
88 mov32 r3, tegra_shut_off_mmu
93 ENDPROC(tegra_sleep_cpu_finish)
98 * r0 = physical address to jump to with mmu off
100 * called with VA=PA mapping
101 * turns off MMU, icache, dcache and branch prediction
103 .align L1_CACHE_SHIFT
104 .pushsection .idmap.text, "ax"
105 ENTRY(tegra_shut_off_mmu)
106 mrc p15, 0, r3, c1, c0, 0
107 movw r2, #CR_I | CR_Z | CR_C | CR_M
110 mcr p15, 0, r3, c1, c0, 0
112 #ifdef CONFIG_CACHE_L2X0
113 /* Disable L2 cache */
114 check_cpu_part_num 0xc09, r9, r10
115 movweq r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
116 movteq r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
118 streq r5, [r4, #L2X0_CTRL]
121 ENDPROC(tegra_shut_off_mmu)
125 * tegra_switch_cpu_to_pllp
127 * In LP2 the normal cpu clock pllx will be turned off. Switch the CPU to pllp
129 ENTRY(tegra_switch_cpu_to_pllp)
130 /* in LP2 idle (SDRAM active), set the CPU burst policy to PLLP */
131 mov32 r5, TEGRA_CLK_RESET_BASE
132 mov r0, #(2 << 28) @ burst policy = run mode
133 orr r0, r0, #(4 << 4) @ use PLLP in run mode burst
134 str r0, [r5, #CLK_RESET_CCLK_BURST]
136 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
138 ENDPROC(tegra_switch_cpu_to_pllp)