2 * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #ifndef __MACH_TEGRA_SLEEP_H
18 #define __MACH_TEGRA_SLEEP_H
22 #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
24 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
26 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
28 #define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
30 #define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
32 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
33 #define PMC_SCRATCH37 0x130
34 #define PMC_SCRATCH38 0x134
35 #define PMC_SCRATCH39 0x138
36 #define PMC_SCRATCH41 0x140
38 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
39 #define CPU_RESETTABLE 2
40 #define CPU_RESETTABLE_SOON 1
41 #define CPU_NOT_RESETTABLE 0
44 /* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */
45 #define TEGRA_FLUSH_CACHE_LOUIS 0
46 #define TEGRA_FLUSH_CACHE_ALL 1
49 /* returns the offset of the flow controller halt register for a cpu */
50 .macro cpu_to_halt_reg rd, rcpu
53 movne \rd, \rd, lsl #3
58 /* returns the offset of the flow controller csr register for a cpu */
59 .macro cpu_to_csr_reg rd, rcpu
62 movne \rd, \rd, lsl #3
67 /* returns the ID of the current processor */
69 mrc p15, 0, \rd, c0, c0, 5
73 /* loads a 32-bit value into a register without a data access */
74 .macro mov32, reg, val
75 movw \reg, #:lower16:\val
76 movt \reg, #:upper16:\val
79 /* Marco to check CPU part num */
80 .macro check_cpu_part_num part_num, tmp1, tmp2
81 mrc p15, 0, \tmp1, c0, c0, 0
82 ubfx \tmp1, \tmp1, #4, #12
83 mov32 \tmp2, \part_num
87 /* Macro to exit SMP coherency. */
88 .macro exit_smp, tmp1, tmp2
89 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
90 bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW
91 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
93 #ifdef CONFIG_HAVE_ARM_SCU
94 check_cpu_part_num 0xc09, \tmp1, \tmp2
95 mrceq p15, 0, \tmp1, c0, c0, 5
96 andeq \tmp1, \tmp1, #0xF
97 moveq \tmp1, \tmp1, lsl #2
99 moveq \tmp2, \tmp2, lsl \tmp1
100 ldreq \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
101 streq \tmp2, [\tmp1] @ invalidate SCU tags for CPU
106 /* Macro to check Tegra revision */
107 #define APB_MISC_GP_HIDREV 0x804
108 .macro tegra_get_soc_id base, tmp1
110 ldr \tmp1, [\tmp1, #APB_MISC_GP_HIDREV]
111 and \tmp1, \tmp1, #0xff00
112 mov \tmp1, \tmp1, lsr #8
115 /* Macro to resume & re-enable L2 cache */
117 #define L2X0_CTRL_EN 1
120 #ifdef CONFIG_CACHE_L2X0
121 .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
122 W(adr) \tmp1, \phys_l2x0_saved_regs
124 ldr \tmp2, [\tmp1, #L2X0_R_PHY_BASE]
125 ldr \tmp3, [\tmp2, #L2X0_CTRL]
126 tst \tmp3, #L2X0_CTRL_EN
128 ldr \tmp3, [\tmp1, #L2X0_R_TAG_LATENCY]
129 str \tmp3, [\tmp2, #L2X0_TAG_LATENCY_CTRL]
130 ldr \tmp3, [\tmp1, #L2X0_R_DATA_LATENCY]
131 str \tmp3, [\tmp2, #L2X0_DATA_LATENCY_CTRL]
132 ldr \tmp3, [\tmp1, #L2X0_R_PREFETCH_CTRL]
133 str \tmp3, [\tmp2, #L2X0_PREFETCH_CTRL]
134 ldr \tmp3, [\tmp1, #L2X0_R_PWR_CTRL]
135 str \tmp3, [\tmp2, #L2X0_POWER_CTRL]
136 ldr \tmp3, [\tmp1, #L2X0_R_AUX_CTRL]
137 str \tmp3, [\tmp2, #L2X0_AUX_CTRL]
138 mov \tmp3, #L2X0_CTRL_EN
139 str \tmp3, [\tmp2, #L2X0_CTRL]
142 #else /* CONFIG_CACHE_L2X0 */
143 .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
145 #endif /* CONFIG_CACHE_L2X0 */
147 void tegra_pen_lock(void);
148 void tegra_pen_unlock(void);
149 void tegra_resume(void);
150 int tegra_sleep_cpu_finish(unsigned long);
151 void tegra_disable_clean_inv_dcache(u32 flag);
153 #ifdef CONFIG_HOTPLUG_CPU
154 void tegra20_hotplug_shutdown(void);
155 void tegra30_hotplug_shutdown(void);
156 void tegra_hotplug_init(void);
158 static inline void tegra_hotplug_init(void) {}
161 void tegra20_cpu_shutdown(int cpu);
162 int tegra20_cpu_is_resettable_soon(void);
163 void tegra20_cpu_clear_resettable(void);
164 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
165 void tegra20_cpu_set_resettable_soon(void);
167 static inline void tegra20_cpu_set_resettable_soon(void) {}
170 int tegra20_sleep_cpu_secondary_finish(unsigned long);
171 void tegra20_tear_down_cpu(void);
172 int tegra30_sleep_cpu_secondary_finish(unsigned long);
173 void tegra30_tear_down_cpu(void);