2 * arch/arm/mach-tegra/tegra20_clocks.c
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
8 * Colin Cross <ccross@google.com>
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/list.h>
24 #include <linux/spinlock.h>
25 #include <linux/delay.h>
27 #include <linux/clkdev.h>
28 #include <linux/clk.h>
30 #include <mach/iomap.h>
34 #include "tegra2_emc.h"
35 #include "tegra_cpu_car.h"
37 #define RST_DEVICES 0x004
38 #define RST_DEVICES_SET 0x300
39 #define RST_DEVICES_CLR 0x304
40 #define RST_DEVICES_NUM 3
42 #define CLK_OUT_ENB 0x010
43 #define CLK_OUT_ENB_SET 0x320
44 #define CLK_OUT_ENB_CLR 0x324
45 #define CLK_OUT_ENB_NUM 3
47 #define CLK_MASK_ARM 0x44
48 #define MISC_CLK_ENB 0x48
51 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
52 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
53 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
54 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
55 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
56 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
58 #define OSC_FREQ_DET 0x58
59 #define OSC_FREQ_DET_TRIG (1<<31)
61 #define OSC_FREQ_DET_STATUS 0x5C
62 #define OSC_FREQ_DET_BUSY (1<<31)
63 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
65 #define PERIPH_CLK_SOURCE_I2S1 0x100
66 #define PERIPH_CLK_SOURCE_EMC 0x19c
67 #define PERIPH_CLK_SOURCE_OSC 0x1fc
68 #define PERIPH_CLK_SOURCE_NUM \
69 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
71 #define PERIPH_CLK_SOURCE_MASK (3<<30)
72 #define PERIPH_CLK_SOURCE_SHIFT 30
73 #define PERIPH_CLK_SOURCE_PWM_MASK (7<<28)
74 #define PERIPH_CLK_SOURCE_PWM_SHIFT 28
75 #define PERIPH_CLK_SOURCE_ENABLE (1<<28)
76 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
77 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
78 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
80 #define SDMMC_CLK_INT_FB_SEL (1 << 23)
81 #define SDMMC_CLK_INT_FB_DLY_SHIFT 16
82 #define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
85 #define PLL_BASE_BYPASS (1<<31)
86 #define PLL_BASE_ENABLE (1<<30)
87 #define PLL_BASE_REF_ENABLE (1<<29)
88 #define PLL_BASE_OVERRIDE (1<<28)
89 #define PLL_BASE_DIVP_MASK (0x7<<20)
90 #define PLL_BASE_DIVP_SHIFT 20
91 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
92 #define PLL_BASE_DIVN_SHIFT 8
93 #define PLL_BASE_DIVM_MASK (0x1F)
94 #define PLL_BASE_DIVM_SHIFT 0
96 #define PLL_OUT_RATIO_MASK (0xFF<<8)
97 #define PLL_OUT_RATIO_SHIFT 8
98 #define PLL_OUT_OVERRIDE (1<<2)
99 #define PLL_OUT_CLKEN (1<<1)
100 #define PLL_OUT_RESET_DISABLE (1<<0)
102 #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
104 #define PLL_MISC_DCCON_SHIFT 20
105 #define PLL_MISC_CPCON_SHIFT 8
106 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
107 #define PLL_MISC_LFCON_SHIFT 4
108 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
109 #define PLL_MISC_VCOCON_SHIFT 0
110 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
112 #define PLLU_BASE_POST_DIV (1<<20)
114 #define PLLD_MISC_CLKENABLE (1<<30)
115 #define PLLD_MISC_DIV_RST (1<<23)
116 #define PLLD_MISC_DCCON_SHIFT 12
118 #define PLLE_MISC_READY (1 << 15)
120 #define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
121 #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
122 #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
124 #define SUPER_CLK_MUX 0x00
125 #define SUPER_STATE_SHIFT 28
126 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
127 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
128 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
129 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
130 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
131 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
132 #define SUPER_SOURCE_MASK 0xF
133 #define SUPER_FIQ_SOURCE_SHIFT 12
134 #define SUPER_IRQ_SOURCE_SHIFT 8
135 #define SUPER_RUN_SOURCE_SHIFT 4
136 #define SUPER_IDLE_SOURCE_SHIFT 0
138 #define SUPER_CLK_DIVIDER 0x04
140 #define BUS_CLK_DISABLE (1<<3)
141 #define BUS_CLK_DIV_MASK 0x3
144 #define PMC_CTRL_BLINK_ENB (1 << 7)
146 #define PMC_DPD_PADS_ORIDE 0x1c
147 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
149 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
150 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
151 #define PMC_BLINK_TIMER_ENB (1 << 15)
152 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
153 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
155 /* Tegra CPU clock and reset control regs */
156 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
157 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
158 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
160 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
161 #define CPU_RESET(cpu) (0x1111ul << (cpu))
163 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
164 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
167 * Some clocks share a register with other clocks. Any clock op that
168 * non-atomically modifies a register used by another clock must lock
169 * clock_register_lock first.
171 static DEFINE_SPINLOCK(clock_register_lock);
174 * Some peripheral clocks share an enable bit, so refcount the enable bits
175 * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
177 static int tegra_periph_clk_enable_refcount[3 * 32];
179 #define clk_writel(value, reg) \
180 __raw_writel(value, reg_clk_base + (reg))
181 #define clk_readl(reg) \
182 __raw_readl(reg_clk_base + (reg))
183 #define pmc_writel(value, reg) \
184 __raw_writel(value, reg_pmc_base + (reg))
185 #define pmc_readl(reg) \
186 __raw_readl(reg_pmc_base + (reg))
188 static unsigned long clk_measure_input_freq(void)
190 u32 clock_autodetect;
191 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
192 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
193 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
194 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
196 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
198 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
200 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
203 pr_err("%s: Unexpected clock autodetect value %d",
204 __func__, clock_autodetect);
210 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
212 s64 divider_u71 = parent_rate * 2;
213 divider_u71 += rate - 1;
214 do_div(divider_u71, rate);
216 if (divider_u71 - 2 < 0)
219 if (divider_u71 - 2 > 255)
222 return divider_u71 - 2;
225 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
229 divider_u16 = parent_rate;
230 divider_u16 += rate - 1;
231 do_div(divider_u16, rate);
233 if (divider_u16 - 1 < 0)
236 if (divider_u16 - 1 > 0xFFFF)
239 return divider_u16 - 1;
242 static unsigned long tegra_clk_fixed_recalc_rate(struct clk_hw *hw,
243 unsigned long parent_rate)
245 return to_clk_tegra(hw)->fixed_rate;
248 struct clk_ops tegra_clk_32k_ops = {
249 .recalc_rate = tegra_clk_fixed_recalc_rate,
252 /* clk_m functions */
253 static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw,
256 if (!to_clk_tegra(hw)->fixed_rate)
257 to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
258 return to_clk_tegra(hw)->fixed_rate;
261 static void tegra20_clk_m_init(struct clk_hw *hw)
263 struct clk_tegra *c = to_clk_tegra(hw);
264 u32 osc_ctrl = clk_readl(OSC_CTRL);
265 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
267 switch (c->fixed_rate) {
269 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
272 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
275 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
278 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
283 clk_writel(auto_clock_control, OSC_CTRL);
286 struct clk_ops tegra_clk_m_ops = {
287 .init = tegra20_clk_m_init,
288 .recalc_rate = tegra20_clk_m_recalc_rate,
291 /* super clock functions */
292 /* "super clocks" on tegra have two-stage muxes and a clock skipping
293 * super divider. We will ignore the clock skipping divider, since we
294 * can't lower the voltage when using the clock skip, but we can if we
295 * lower the PLL frequency.
297 static int tegra20_super_clk_is_enabled(struct clk_hw *hw)
299 struct clk_tegra *c = to_clk_tegra(hw);
302 val = clk_readl(c->reg + SUPER_CLK_MUX);
303 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
304 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
309 static int tegra20_super_clk_enable(struct clk_hw *hw)
311 struct clk_tegra *c = to_clk_tegra(hw);
312 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
316 static void tegra20_super_clk_disable(struct clk_hw *hw)
318 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
320 /* oops - don't disable the CPU clock! */
324 static u8 tegra20_super_clk_get_parent(struct clk_hw *hw)
326 struct clk_tegra *c = to_clk_tegra(hw);
327 int val = clk_readl(c->reg + SUPER_CLK_MUX);
331 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
332 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
333 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
334 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
335 source = (val >> shift) & SUPER_SOURCE_MASK;
339 static int tegra20_super_clk_set_parent(struct clk_hw *hw, u8 index)
341 struct clk_tegra *c = to_clk_tegra(hw);
342 u32 val = clk_readl(c->reg + SUPER_CLK_MUX);
345 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
346 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
347 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
348 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
349 val &= ~(SUPER_SOURCE_MASK << shift);
350 val |= index << shift;
352 clk_writel(val, c->reg);
357 /* FIX ME: Need to switch parents to change the source PLL rate */
358 static unsigned long tegra20_super_clk_recalc_rate(struct clk_hw *hw,
364 static long tegra20_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
365 unsigned long *prate)
370 static int tegra20_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
371 unsigned long parent_rate)
376 struct clk_ops tegra_super_ops = {
377 .is_enabled = tegra20_super_clk_is_enabled,
378 .enable = tegra20_super_clk_enable,
379 .disable = tegra20_super_clk_disable,
380 .set_parent = tegra20_super_clk_set_parent,
381 .get_parent = tegra20_super_clk_get_parent,
382 .set_rate = tegra20_super_clk_set_rate,
383 .round_rate = tegra20_super_clk_round_rate,
384 .recalc_rate = tegra20_super_clk_recalc_rate,
387 static unsigned long tegra20_twd_clk_recalc_rate(struct clk_hw *hw,
388 unsigned long parent_rate)
390 struct clk_tegra *c = to_clk_tegra(hw);
391 u64 rate = parent_rate;
393 if (c->mul != 0 && c->div != 0) {
395 rate += c->div - 1; /* round up */
396 do_div(rate, c->div);
402 struct clk_ops tegra_twd_ops = {
403 .recalc_rate = tegra20_twd_clk_recalc_rate,
406 static u8 tegra20_cop_clk_get_parent(struct clk_hw *hw)
411 struct clk_ops tegra_cop_ops = {
412 .get_parent = tegra20_cop_clk_get_parent,
415 /* virtual cop clock functions. Used to acquire the fake 'cop' clock to
416 * reset the COP block (i.e. AVP) */
417 void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert)
419 unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
421 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
422 clk_writel(1 << 1, reg);
425 /* bus clock functions */
426 static int tegra20_bus_clk_is_enabled(struct clk_hw *hw)
428 struct clk_tegra *c = to_clk_tegra(hw);
429 u32 val = clk_readl(c->reg);
431 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
435 static int tegra20_bus_clk_enable(struct clk_hw *hw)
437 struct clk_tegra *c = to_clk_tegra(hw);
441 spin_lock_irqsave(&clock_register_lock, flags);
443 val = clk_readl(c->reg);
444 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
445 clk_writel(val, c->reg);
447 spin_unlock_irqrestore(&clock_register_lock, flags);
452 static void tegra20_bus_clk_disable(struct clk_hw *hw)
454 struct clk_tegra *c = to_clk_tegra(hw);
458 spin_lock_irqsave(&clock_register_lock, flags);
460 val = clk_readl(c->reg);
461 val |= BUS_CLK_DISABLE << c->reg_shift;
462 clk_writel(val, c->reg);
464 spin_unlock_irqrestore(&clock_register_lock, flags);
467 static unsigned long tegra20_bus_clk_recalc_rate(struct clk_hw *hw,
470 struct clk_tegra *c = to_clk_tegra(hw);
471 u32 val = clk_readl(c->reg);
474 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
477 if (c->mul != 0 && c->div != 0) {
479 rate += c->div - 1; /* round up */
480 do_div(rate, c->div);
485 static int tegra20_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
486 unsigned long parent_rate)
488 struct clk_tegra *c = to_clk_tegra(hw);
494 spin_lock_irqsave(&clock_register_lock, flags);
496 val = clk_readl(c->reg);
497 for (i = 1; i <= 4; i++) {
498 if (rate == parent_rate / i) {
499 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
500 val |= (i - 1) << c->reg_shift;
501 clk_writel(val, c->reg);
509 spin_unlock_irqrestore(&clock_register_lock, flags);
514 static long tegra20_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
515 unsigned long *prate)
517 unsigned long parent_rate = *prate;
520 if (rate >= parent_rate)
523 divider = parent_rate;
525 do_div(divider, rate);
532 do_div(parent_rate, divider);
537 struct clk_ops tegra_bus_ops = {
538 .is_enabled = tegra20_bus_clk_is_enabled,
539 .enable = tegra20_bus_clk_enable,
540 .disable = tegra20_bus_clk_disable,
541 .set_rate = tegra20_bus_clk_set_rate,
542 .round_rate = tegra20_bus_clk_round_rate,
543 .recalc_rate = tegra20_bus_clk_recalc_rate,
546 /* Blink output functions */
547 static int tegra20_blink_clk_is_enabled(struct clk_hw *hw)
549 struct clk_tegra *c = to_clk_tegra(hw);
552 val = pmc_readl(PMC_CTRL);
553 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
557 static unsigned long tegra20_blink_clk_recalc_rate(struct clk_hw *hw,
560 struct clk_tegra *c = to_clk_tegra(hw);
565 val = pmc_readl(c->reg);
567 if (val & PMC_BLINK_TIMER_ENB) {
570 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
571 PMC_BLINK_TIMER_DATA_ON_MASK;
572 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
573 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
575 /* each tick in the blink timer is 4 32KHz clocks */
581 if (c->mul != 0 && c->div != 0) {
583 rate += c->div - 1; /* round up */
584 do_div(rate, c->div);
589 static int tegra20_blink_clk_enable(struct clk_hw *hw)
593 val = pmc_readl(PMC_DPD_PADS_ORIDE);
594 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
596 val = pmc_readl(PMC_CTRL);
597 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
602 static void tegra20_blink_clk_disable(struct clk_hw *hw)
606 val = pmc_readl(PMC_CTRL);
607 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
609 val = pmc_readl(PMC_DPD_PADS_ORIDE);
610 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
613 static int tegra20_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
614 unsigned long parent_rate)
616 struct clk_tegra *c = to_clk_tegra(hw);
618 if (rate >= parent_rate) {
620 pmc_writel(0, c->reg);
625 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
628 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
629 PMC_BLINK_TIMER_DATA_ON_SHIFT;
630 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
631 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
633 val |= PMC_BLINK_TIMER_ENB;
634 pmc_writel(val, c->reg);
640 static long tegra20_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
641 unsigned long *prate)
645 long round_rate = *prate;
649 if (rate >= *prate) {
652 div = DIV_ROUND_UP(*prate / 8, rate);
657 round_rate += div - 1;
658 do_div(round_rate, div);
663 struct clk_ops tegra_blink_clk_ops = {
664 .is_enabled = tegra20_blink_clk_is_enabled,
665 .enable = tegra20_blink_clk_enable,
666 .disable = tegra20_blink_clk_disable,
667 .set_rate = tegra20_blink_clk_set_rate,
668 .round_rate = tegra20_blink_clk_round_rate,
669 .recalc_rate = tegra20_blink_clk_recalc_rate,
673 static int tegra20_pll_clk_wait_for_lock(struct clk_tegra *c)
675 udelay(c->u.pll.lock_delay);
679 static int tegra20_pll_clk_is_enabled(struct clk_hw *hw)
681 struct clk_tegra *c = to_clk_tegra(hw);
682 u32 val = clk_readl(c->reg + PLL_BASE);
684 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
688 static unsigned long tegra20_pll_clk_recalc_rate(struct clk_hw *hw,
691 struct clk_tegra *c = to_clk_tegra(hw);
692 u32 val = clk_readl(c->reg + PLL_BASE);
695 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
696 const struct clk_pll_freq_table *sel;
697 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
698 if (sel->input_rate == prate &&
699 sel->output_rate == c->u.pll.fixed_rate) {
701 c->div = sel->m * sel->p;
705 pr_err("Clock %s has unknown fixed frequency\n",
706 __clk_get_name(hw->clk));
708 } else if (val & PLL_BASE_BYPASS) {
712 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
713 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
715 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
717 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
720 if (c->mul != 0 && c->div != 0) {
722 rate += c->div - 1; /* round up */
723 do_div(rate, c->div);
728 static int tegra20_pll_clk_enable(struct clk_hw *hw)
730 struct clk_tegra *c = to_clk_tegra(hw);
732 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
734 val = clk_readl(c->reg + PLL_BASE);
735 val &= ~PLL_BASE_BYPASS;
736 val |= PLL_BASE_ENABLE;
737 clk_writel(val, c->reg + PLL_BASE);
739 tegra20_pll_clk_wait_for_lock(c);
744 static void tegra20_pll_clk_disable(struct clk_hw *hw)
746 struct clk_tegra *c = to_clk_tegra(hw);
748 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
750 val = clk_readl(c->reg);
751 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
752 clk_writel(val, c->reg);
755 static int tegra20_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
756 unsigned long parent_rate)
758 struct clk_tegra *c = to_clk_tegra(hw);
759 unsigned long input_rate = parent_rate;
760 const struct clk_pll_freq_table *sel;
763 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
765 if (c->flags & PLL_FIXED) {
767 if (rate != c->u.pll.fixed_rate) {
768 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
769 __func__, __clk_get_name(hw->clk),
770 c->u.pll.fixed_rate, rate);
776 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
777 if (sel->input_rate == input_rate && sel->output_rate == rate) {
779 c->div = sel->m * sel->p;
781 val = clk_readl(c->reg + PLL_BASE);
782 if (c->flags & PLL_FIXED)
783 val |= PLL_BASE_OVERRIDE;
784 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
786 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
787 (sel->n << PLL_BASE_DIVN_SHIFT);
788 BUG_ON(sel->p < 1 || sel->p > 2);
789 if (c->flags & PLLU) {
791 val |= PLLU_BASE_POST_DIV;
794 val |= 1 << PLL_BASE_DIVP_SHIFT;
796 clk_writel(val, c->reg + PLL_BASE);
798 if (c->flags & PLL_HAS_CPCON) {
799 val = clk_readl(c->reg + PLL_MISC(c));
800 val &= ~PLL_MISC_CPCON_MASK;
801 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
802 clk_writel(val, c->reg + PLL_MISC(c));
806 tegra20_pll_clk_enable(hw);
813 static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
814 unsigned long *prate)
816 struct clk_tegra *c = to_clk_tegra(hw);
817 const struct clk_pll_freq_table *sel;
818 unsigned long input_rate = *prate;
819 u64 output_rate = *prate;
823 if (c->flags & PLL_FIXED)
824 return c->u.pll.fixed_rate;
826 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++)
827 if (sel->input_rate == input_rate && sel->output_rate == rate) {
829 div = sel->m * sel->p;
833 if (sel->input_rate == 0)
837 output_rate += div - 1; /* round up */
838 do_div(output_rate, div);
843 struct clk_ops tegra_pll_ops = {
844 .is_enabled = tegra20_pll_clk_is_enabled,
845 .enable = tegra20_pll_clk_enable,
846 .disable = tegra20_pll_clk_disable,
847 .set_rate = tegra20_pll_clk_set_rate,
848 .recalc_rate = tegra20_pll_clk_recalc_rate,
849 .round_rate = tegra20_pll_clk_round_rate,
852 static void tegra20_pllx_clk_init(struct clk_hw *hw)
854 struct clk_tegra *c = to_clk_tegra(hw);
856 if (tegra_sku_id == 7)
857 c->max_rate = 750000000;
860 struct clk_ops tegra_pllx_ops = {
861 .init = tegra20_pllx_clk_init,
862 .is_enabled = tegra20_pll_clk_is_enabled,
863 .enable = tegra20_pll_clk_enable,
864 .disable = tegra20_pll_clk_disable,
865 .set_rate = tegra20_pll_clk_set_rate,
866 .recalc_rate = tegra20_pll_clk_recalc_rate,
867 .round_rate = tegra20_pll_clk_round_rate,
870 static int tegra20_plle_clk_enable(struct clk_hw *hw)
872 struct clk_tegra *c = to_clk_tegra(hw);
875 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
879 val = clk_readl(c->reg + PLL_BASE);
880 if (!(val & PLLE_MISC_READY))
883 val = clk_readl(c->reg + PLL_BASE);
884 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
885 clk_writel(val, c->reg + PLL_BASE);
890 struct clk_ops tegra_plle_ops = {
891 .is_enabled = tegra20_pll_clk_is_enabled,
892 .enable = tegra20_plle_clk_enable,
893 .set_rate = tegra20_pll_clk_set_rate,
894 .recalc_rate = tegra20_pll_clk_recalc_rate,
895 .round_rate = tegra20_pll_clk_round_rate,
898 /* Clock divider ops */
899 static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw)
901 struct clk_tegra *c = to_clk_tegra(hw);
902 u32 val = clk_readl(c->reg);
904 val >>= c->reg_shift;
905 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
906 if (!(val & PLL_OUT_RESET_DISABLE))
911 static unsigned long tegra20_pll_div_clk_recalc_rate(struct clk_hw *hw,
914 struct clk_tegra *c = to_clk_tegra(hw);
916 u32 val = clk_readl(c->reg);
919 val >>= c->reg_shift;
921 if (c->flags & DIV_U71) {
922 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
923 c->div = (divu71 + 2);
925 } else if (c->flags & DIV_2) {
934 rate += c->div - 1; /* round up */
935 do_div(rate, c->div);
940 static int tegra20_pll_div_clk_enable(struct clk_hw *hw)
942 struct clk_tegra *c = to_clk_tegra(hw);
947 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
949 if (c->flags & DIV_U71) {
950 spin_lock_irqsave(&clock_register_lock, flags);
951 val = clk_readl(c->reg);
952 new_val = val >> c->reg_shift;
955 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
957 val &= ~(0xFFFF << c->reg_shift);
958 val |= new_val << c->reg_shift;
959 clk_writel(val, c->reg);
960 spin_unlock_irqrestore(&clock_register_lock, flags);
962 } else if (c->flags & DIV_2) {
963 BUG_ON(!(c->flags & PLLD));
964 spin_lock_irqsave(&clock_register_lock, flags);
965 val = clk_readl(c->reg);
966 val &= ~PLLD_MISC_DIV_RST;
967 clk_writel(val, c->reg);
968 spin_unlock_irqrestore(&clock_register_lock, flags);
974 static void tegra20_pll_div_clk_disable(struct clk_hw *hw)
976 struct clk_tegra *c = to_clk_tegra(hw);
981 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
983 if (c->flags & DIV_U71) {
984 spin_lock_irqsave(&clock_register_lock, flags);
985 val = clk_readl(c->reg);
986 new_val = val >> c->reg_shift;
989 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
991 val &= ~(0xFFFF << c->reg_shift);
992 val |= new_val << c->reg_shift;
993 clk_writel(val, c->reg);
994 spin_unlock_irqrestore(&clock_register_lock, flags);
995 } else if (c->flags & DIV_2) {
996 BUG_ON(!(c->flags & PLLD));
997 spin_lock_irqsave(&clock_register_lock, flags);
998 val = clk_readl(c->reg);
999 val |= PLLD_MISC_DIV_RST;
1000 clk_writel(val, c->reg);
1001 spin_unlock_irqrestore(&clock_register_lock, flags);
1005 static int tegra20_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1006 unsigned long parent_rate)
1008 struct clk_tegra *c = to_clk_tegra(hw);
1009 unsigned long flags;
1014 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
1016 if (c->flags & DIV_U71) {
1017 divider_u71 = clk_div71_get_divider(parent_rate, rate);
1018 if (divider_u71 >= 0) {
1019 spin_lock_irqsave(&clock_register_lock, flags);
1020 val = clk_readl(c->reg);
1021 new_val = val >> c->reg_shift;
1023 if (c->flags & DIV_U71_FIXED)
1024 new_val |= PLL_OUT_OVERRIDE;
1025 new_val &= ~PLL_OUT_RATIO_MASK;
1026 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
1028 val &= ~(0xFFFF << c->reg_shift);
1029 val |= new_val << c->reg_shift;
1030 clk_writel(val, c->reg);
1031 c->div = divider_u71 + 2;
1033 spin_unlock_irqrestore(&clock_register_lock, flags);
1036 } else if (c->flags & DIV_2) {
1037 if (parent_rate == rate * 2)
1043 static long tegra20_pll_div_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1044 unsigned long *prate)
1046 struct clk_tegra *c = to_clk_tegra(hw);
1047 unsigned long parent_rate = *prate;
1050 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
1052 if (c->flags & DIV_U71) {
1053 divider = clk_div71_get_divider(parent_rate, rate);
1056 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1057 } else if (c->flags & DIV_2) {
1058 return DIV_ROUND_UP(parent_rate, 2);
1063 struct clk_ops tegra_pll_div_ops = {
1064 .is_enabled = tegra20_pll_div_clk_is_enabled,
1065 .enable = tegra20_pll_div_clk_enable,
1066 .disable = tegra20_pll_div_clk_disable,
1067 .set_rate = tegra20_pll_div_clk_set_rate,
1068 .round_rate = tegra20_pll_div_clk_round_rate,
1069 .recalc_rate = tegra20_pll_div_clk_recalc_rate,
1072 /* Periph clk ops */
1074 static int tegra20_periph_clk_is_enabled(struct clk_hw *hw)
1076 struct clk_tegra *c = to_clk_tegra(hw);
1080 if (!c->u.periph.clk_num)
1083 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1084 PERIPH_CLK_TO_ENB_BIT(c)))
1087 if (!(c->flags & PERIPH_NO_RESET))
1088 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
1089 PERIPH_CLK_TO_ENB_BIT(c))
1096 static int tegra20_periph_clk_enable(struct clk_hw *hw)
1098 struct clk_tegra *c = to_clk_tegra(hw);
1099 unsigned long flags;
1102 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1104 if (!c->u.periph.clk_num)
1107 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
1108 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
1111 spin_lock_irqsave(&clock_register_lock, flags);
1113 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1114 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1115 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
1116 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1117 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1118 if (c->flags & PERIPH_EMC_ENB) {
1119 /* The EMC peripheral clock has 2 extra enable bits */
1120 /* FIXME: Do they need to be disabled? */
1121 val = clk_readl(c->reg);
1123 clk_writel(val, c->reg);
1126 spin_unlock_irqrestore(&clock_register_lock, flags);
1131 static void tegra20_periph_clk_disable(struct clk_hw *hw)
1133 struct clk_tegra *c = to_clk_tegra(hw);
1134 unsigned long flags;
1136 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1138 if (!c->u.periph.clk_num)
1141 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1143 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
1146 spin_lock_irqsave(&clock_register_lock, flags);
1148 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1149 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1151 spin_unlock_irqrestore(&clock_register_lock, flags);
1154 void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert)
1156 struct clk_tegra *c = to_clk_tegra(hw);
1157 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
1159 pr_debug("%s %s on clock %s\n", __func__,
1160 assert ? "assert" : "deassert", __clk_get_name(hw->clk));
1162 BUG_ON(!c->u.periph.clk_num);
1164 if (!(c->flags & PERIPH_NO_RESET))
1165 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1166 base + PERIPH_CLK_TO_ENB_SET_REG(c));
1169 static int tegra20_periph_clk_set_parent(struct clk_hw *hw, u8 index)
1171 struct clk_tegra *c = to_clk_tegra(hw);
1176 pr_debug("%s: %s %d\n", __func__, __clk_get_name(hw->clk), index);
1178 if (c->flags & MUX_PWM) {
1179 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
1180 mask = PERIPH_CLK_SOURCE_PWM_MASK;
1182 shift = PERIPH_CLK_SOURCE_SHIFT;
1183 mask = PERIPH_CLK_SOURCE_MASK;
1186 val = clk_readl(c->reg);
1188 val |= (index) << shift;
1190 clk_writel(val, c->reg);
1195 static u8 tegra20_periph_clk_get_parent(struct clk_hw *hw)
1197 struct clk_tegra *c = to_clk_tegra(hw);
1198 u32 val = clk_readl(c->reg);
1202 if (c->flags & MUX_PWM) {
1203 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
1204 mask = PERIPH_CLK_SOURCE_PWM_MASK;
1206 shift = PERIPH_CLK_SOURCE_SHIFT;
1207 mask = PERIPH_CLK_SOURCE_MASK;
1211 return (val & mask) >> shift;
1216 static unsigned long tegra20_periph_clk_recalc_rate(struct clk_hw *hw,
1217 unsigned long prate)
1219 struct clk_tegra *c = to_clk_tegra(hw);
1220 unsigned long rate = prate;
1221 u32 val = clk_readl(c->reg);
1223 if (c->flags & DIV_U71) {
1224 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1225 c->div = divu71 + 2;
1227 } else if (c->flags & DIV_U16) {
1228 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1229 c->div = divu16 + 1;
1237 if (c->mul != 0 && c->div != 0) {
1239 rate += c->div - 1; /* round up */
1240 do_div(rate, c->div);
1246 static int tegra20_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1247 unsigned long parent_rate)
1249 struct clk_tegra *c = to_clk_tegra(hw);
1253 val = clk_readl(c->reg);
1255 if (c->flags & DIV_U71) {
1256 divider = clk_div71_get_divider(parent_rate, rate);
1259 val = clk_readl(c->reg);
1260 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1262 clk_writel(val, c->reg);
1263 c->div = divider + 2;
1267 } else if (c->flags & DIV_U16) {
1268 divider = clk_div16_get_divider(parent_rate, rate);
1270 val = clk_readl(c->reg);
1271 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1273 clk_writel(val, c->reg);
1274 c->div = divider + 1;
1278 } else if (parent_rate <= rate) {
1287 static long tegra20_periph_clk_round_rate(struct clk_hw *hw,
1288 unsigned long rate, unsigned long *prate)
1290 struct clk_tegra *c = to_clk_tegra(hw);
1291 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1294 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
1297 parent_rate = *prate;
1299 if (c->flags & DIV_U71) {
1300 divider = clk_div71_get_divider(parent_rate, rate);
1304 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1305 } else if (c->flags & DIV_U16) {
1306 divider = clk_div16_get_divider(parent_rate, rate);
1309 return DIV_ROUND_UP(parent_rate, divider + 1);
1314 struct clk_ops tegra_periph_clk_ops = {
1315 .is_enabled = tegra20_periph_clk_is_enabled,
1316 .enable = tegra20_periph_clk_enable,
1317 .disable = tegra20_periph_clk_disable,
1318 .set_parent = tegra20_periph_clk_set_parent,
1319 .get_parent = tegra20_periph_clk_get_parent,
1320 .set_rate = tegra20_periph_clk_set_rate,
1321 .round_rate = tegra20_periph_clk_round_rate,
1322 .recalc_rate = tegra20_periph_clk_recalc_rate,
1325 /* External memory controller clock ops */
1326 static void tegra20_emc_clk_init(struct clk_hw *hw)
1328 struct clk_tegra *c = to_clk_tegra(hw);
1329 c->max_rate = __clk_get_rate(hw->clk);
1332 static long tegra20_emc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1333 unsigned long *prate)
1335 struct clk_tegra *c = to_clk_tegra(hw);
1340 * The slowest entry in the EMC clock table that is at least as
1343 emc_rate = tegra_emc_round_rate(rate);
1348 * The fastest rate the PLL will generate that is at most the
1351 clk_rate = tegra20_periph_clk_round_rate(hw, emc_rate, NULL);
1354 * If this fails, and emc_rate > clk_rate, it's because the maximum
1355 * rate in the EMC tables is larger than the maximum rate of the EMC
1356 * clock. The EMC clock's max rate is the rate it was running when the
1357 * kernel booted. Such a mismatch is probably due to using the wrong
1358 * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
1360 WARN_ONCE(emc_rate != clk_rate,
1361 "emc_rate %ld != clk_rate %ld",
1362 emc_rate, clk_rate);
1367 static int tegra20_emc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1368 unsigned long parent_rate)
1373 * The Tegra2 memory controller has an interlock with the clock
1374 * block that allows memory shadowed registers to be updated,
1375 * and then transfer them to the main registers at the same
1376 * time as the clock update without glitches.
1378 ret = tegra_emc_set_rate(rate);
1382 ret = tegra20_periph_clk_set_rate(hw, rate, parent_rate);
1388 struct clk_ops tegra_emc_clk_ops = {
1389 .init = tegra20_emc_clk_init,
1390 .is_enabled = tegra20_periph_clk_is_enabled,
1391 .enable = tegra20_periph_clk_enable,
1392 .disable = tegra20_periph_clk_disable,
1393 .set_parent = tegra20_periph_clk_set_parent,
1394 .get_parent = tegra20_periph_clk_get_parent,
1395 .set_rate = tegra20_emc_clk_set_rate,
1396 .round_rate = tegra20_emc_clk_round_rate,
1397 .recalc_rate = tegra20_periph_clk_recalc_rate,
1400 /* Clock doubler ops */
1401 static int tegra20_clk_double_is_enabled(struct clk_hw *hw)
1403 struct clk_tegra *c = to_clk_tegra(hw);
1407 if (!c->u.periph.clk_num)
1410 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1411 PERIPH_CLK_TO_ENB_BIT(c)))
1418 static unsigned long tegra20_clk_double_recalc_rate(struct clk_hw *hw,
1419 unsigned long prate)
1421 struct clk_tegra *c = to_clk_tegra(hw);
1428 rate += c->div - 1; /* round up */
1429 do_div(rate, c->div);
1434 static long tegra20_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
1435 unsigned long *prate)
1437 unsigned long output_rate = *prate;
1439 do_div(output_rate, 2);
1443 static int tegra20_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
1444 unsigned long parent_rate)
1446 if (rate != 2 * parent_rate)
1451 struct clk_ops tegra_clk_double_ops = {
1452 .is_enabled = tegra20_clk_double_is_enabled,
1453 .enable = tegra20_periph_clk_enable,
1454 .disable = tegra20_periph_clk_disable,
1455 .set_rate = tegra20_clk_double_set_rate,
1456 .recalc_rate = tegra20_clk_double_recalc_rate,
1457 .round_rate = tegra20_clk_double_round_rate,
1460 /* Audio sync clock ops */
1461 static int tegra20_audio_sync_clk_is_enabled(struct clk_hw *hw)
1463 struct clk_tegra *c = to_clk_tegra(hw);
1464 u32 val = clk_readl(c->reg);
1466 c->state = (val & (1<<4)) ? OFF : ON;
1470 static int tegra20_audio_sync_clk_enable(struct clk_hw *hw)
1472 struct clk_tegra *c = to_clk_tegra(hw);
1474 clk_writel(0, c->reg);
1478 static void tegra20_audio_sync_clk_disable(struct clk_hw *hw)
1480 struct clk_tegra *c = to_clk_tegra(hw);
1481 clk_writel(1, c->reg);
1484 static u8 tegra20_audio_sync_clk_get_parent(struct clk_hw *hw)
1486 struct clk_tegra *c = to_clk_tegra(hw);
1487 u32 val = clk_readl(c->reg);
1494 static int tegra20_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
1496 struct clk_tegra *c = to_clk_tegra(hw);
1499 val = clk_readl(c->reg);
1503 clk_writel(val, c->reg);
1508 struct clk_ops tegra_audio_sync_clk_ops = {
1509 .is_enabled = tegra20_audio_sync_clk_is_enabled,
1510 .enable = tegra20_audio_sync_clk_enable,
1511 .disable = tegra20_audio_sync_clk_disable,
1512 .set_parent = tegra20_audio_sync_clk_set_parent,
1513 .get_parent = tegra20_audio_sync_clk_get_parent,
1516 /* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1518 static int tegra20_cdev_clk_is_enabled(struct clk_hw *hw)
1520 struct clk_tegra *c = to_clk_tegra(hw);
1521 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1522 * currently done in the pinmux code. */
1525 BUG_ON(!c->u.periph.clk_num);
1527 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1528 PERIPH_CLK_TO_ENB_BIT(c)))
1533 static int tegra20_cdev_clk_enable(struct clk_hw *hw)
1535 struct clk_tegra *c = to_clk_tegra(hw);
1536 BUG_ON(!c->u.periph.clk_num);
1538 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1539 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1543 static void tegra20_cdev_clk_disable(struct clk_hw *hw)
1545 struct clk_tegra *c = to_clk_tegra(hw);
1546 BUG_ON(!c->u.periph.clk_num);
1548 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1549 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1552 static unsigned long tegra20_cdev_recalc_rate(struct clk_hw *hw,
1553 unsigned long prate)
1555 return to_clk_tegra(hw)->fixed_rate;
1558 struct clk_ops tegra_cdev_clk_ops = {
1559 .is_enabled = tegra20_cdev_clk_is_enabled,
1560 .enable = tegra20_cdev_clk_enable,
1561 .disable = tegra20_cdev_clk_disable,
1562 .recalc_rate = tegra20_cdev_recalc_rate,
1565 /* Tegra20 CPU clock and reset control functions */
1566 static void tegra20_wait_cpu_in_reset(u32 cpu)
1571 reg = readl(reg_clk_base +
1572 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1574 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1579 static void tegra20_put_cpu_in_reset(u32 cpu)
1581 writel(CPU_RESET(cpu),
1582 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1586 static void tegra20_cpu_out_of_reset(u32 cpu)
1588 writel(CPU_RESET(cpu),
1589 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1593 static void tegra20_enable_cpu_clock(u32 cpu)
1597 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1598 writel(reg & ~CPU_CLOCK(cpu),
1599 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1601 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1604 static void tegra20_disable_cpu_clock(u32 cpu)
1608 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1609 writel(reg | CPU_CLOCK(cpu),
1610 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1613 static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1614 .wait_for_reset = tegra20_wait_cpu_in_reset,
1615 .put_in_reset = tegra20_put_cpu_in_reset,
1616 .out_of_reset = tegra20_cpu_out_of_reset,
1617 .enable_clock = tegra20_enable_cpu_clock,
1618 .disable_clock = tegra20_disable_cpu_clock,
1621 void __init tegra20_cpu_car_ops_init(void)
1623 tegra_cpu_car_ops = &tegra20_cpu_car_ops;