2 * arch/arm/mach-tegra/tegra2_clocks.c
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
8 * Colin Cross <ccross@google.com>
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 #include <linux/clk-private.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/list.h>
25 #include <linux/spinlock.h>
26 #include <linux/delay.h>
28 #include <linux/clk.h>
30 #include <mach/iomap.h>
34 #include "tegra2_emc.h"
35 #include "tegra20_clocks.h"
37 /* Clock definitions */
39 #define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
40 _parent_names, _parents, _parent) \
41 static struct clk tegra_##_name = { \
42 .hw = &tegra_##_name##_hw.hw, \
47 .parent_names = _parent_names, \
48 .parents = _parents, \
49 .num_parents = ARRAY_SIZE(_parent_names), \
53 static struct clk tegra_clk_32k;
54 static struct clk_tegra tegra_clk_32k_hw = {
56 .clk = &tegra_clk_32k,
61 static struct clk tegra_clk_32k = {
64 .ops = &tegra_clk_32k_ops,
65 .hw = &tegra_clk_32k_hw.hw,
69 static struct clk tegra_clk_m;
70 static struct clk_tegra tegra_clk_m_hw = {
74 .flags = ENABLE_ON_INIT,
81 static struct clk tegra_clk_m = {
83 .ops = &tegra_clk_m_ops,
84 .hw = &tegra_clk_m_hw.hw,
88 #define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
89 _input_max, _cf_min, _cf_max, _vco_min, \
90 _vco_max, _freq_table, _lock_delay, _ops, \
91 _fixed_rate, _parent) \
92 static const char *tegra_##_name##_parent_names[] = { \
95 static struct clk *tegra_##_name##_parents[] = { \
98 static struct clk tegra_##_name; \
99 static struct clk_tegra tegra_##_name##_hw = { \
101 .clk = &tegra_##_name, \
105 .max_rate = _max_rate, \
107 .input_min = _input_min, \
108 .input_max = _input_max, \
111 .vco_min = _vco_min, \
112 .vco_max = _vco_max, \
113 .freq_table = _freq_table, \
114 .lock_delay = _lock_delay, \
115 .fixed_rate = _fixed_rate, \
118 static struct clk tegra_##_name = { \
121 .hw = &tegra_##_name##_hw.hw, \
122 .parent = &tegra_##_parent, \
123 .parent_names = tegra_##_name##_parent_names, \
124 .parents = tegra_##_name##_parents, \
128 #define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
129 _max_rate, _ops, _parent, _clk_flags) \
130 static const char *tegra_##_name##_parent_names[] = { \
133 static struct clk *tegra_##_name##_parents[] = { \
136 static struct clk tegra_##_name; \
137 static struct clk_tegra tegra_##_name##_hw = { \
139 .clk = &tegra_##_name, \
143 .max_rate = _max_rate, \
144 .reg_shift = _reg_shift, \
146 static struct clk tegra_##_name = { \
148 .ops = &tegra_pll_div_ops, \
149 .hw = &tegra_##_name##_hw.hw, \
150 .parent = &tegra_##_parent, \
151 .parent_names = tegra_##_name##_parent_names, \
152 .parents = tegra_##_name##_parents, \
154 .flags = _clk_flags, \
158 static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
159 {32768, 12000000, 366, 1, 1, 0},
160 {32768, 13000000, 397, 1, 1, 0},
161 {32768, 19200000, 586, 1, 1, 0},
162 {32768, 26000000, 793, 1, 1, 0},
166 DEFINE_PLL(pll_s, PLL_ALT_MISC_REG, 0xf0, 26000000, 32768, 32768, 0,
167 0, 12000000, 26000000, tegra_pll_s_freq_table, 300,
168 tegra_pll_ops, 0, clk_32k);
170 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
171 { 12000000, 600000000, 600, 12, 1, 8 },
172 { 13000000, 600000000, 600, 13, 1, 8 },
173 { 19200000, 600000000, 500, 16, 1, 6 },
174 { 26000000, 600000000, 600, 26, 1, 8 },
175 { 0, 0, 0, 0, 0, 0 },
178 DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 600000000, 2000000, 31000000, 1000000,
179 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
180 tegra_pll_ops, 0, clk_m);
182 DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 600000000,
183 tegra_pll_div_ops, pll_c, 0);
185 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
186 { 12000000, 666000000, 666, 12, 1, 8},
187 { 13000000, 666000000, 666, 13, 1, 8},
188 { 19200000, 666000000, 555, 16, 1, 8},
189 { 26000000, 666000000, 666, 26, 1, 8},
190 { 12000000, 600000000, 600, 12, 1, 8},
191 { 13000000, 600000000, 600, 13, 1, 8},
192 { 19200000, 600000000, 375, 12, 1, 6},
193 { 26000000, 600000000, 600, 26, 1, 8},
194 { 0, 0, 0, 0, 0, 0 },
197 DEFINE_PLL(pll_m, PLL_HAS_CPCON, 0x90, 800000000, 2000000, 31000000, 1000000,
198 6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300,
199 tegra_pll_ops, 0, clk_m);
201 DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
202 tegra_pll_div_ops, pll_m, 0);
204 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
205 { 12000000, 216000000, 432, 12, 2, 8},
206 { 13000000, 216000000, 432, 13, 2, 8},
207 { 19200000, 216000000, 90, 4, 2, 1},
208 { 26000000, 216000000, 432, 26, 2, 8},
209 { 12000000, 432000000, 432, 12, 1, 8},
210 { 13000000, 432000000, 432, 13, 1, 8},
211 { 19200000, 432000000, 90, 4, 1, 1},
212 { 26000000, 432000000, 432, 26, 1, 8},
213 { 0, 0, 0, 0, 0, 0 },
217 DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
218 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
219 tegra_pll_p_freq_table, 300, tegra_pll_ops, 216000000, clk_m);
221 DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 0,
222 432000000, tegra_pll_div_ops, pll_p, 0);
223 DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 16,
224 432000000, tegra_pll_div_ops, pll_p, 0);
225 DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 0,
226 432000000, tegra_pll_div_ops, pll_p, 0);
227 DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 16,
228 432000000, tegra_pll_div_ops, pll_p, 0);
230 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
231 { 28800000, 56448000, 49, 25, 1, 1},
232 { 28800000, 73728000, 64, 25, 1, 1},
233 { 28800000, 24000000, 5, 6, 1, 1},
234 { 0, 0, 0, 0, 0, 0 },
237 DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
238 6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300,
239 tegra_pll_ops, 0, pll_p_out1);
241 DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
242 tegra_pll_div_ops, pll_a, 0);
244 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
245 { 12000000, 216000000, 216, 12, 1, 4},
246 { 13000000, 216000000, 216, 13, 1, 4},
247 { 19200000, 216000000, 135, 12, 1, 3},
248 { 26000000, 216000000, 216, 26, 1, 4},
250 { 12000000, 594000000, 594, 12, 1, 8},
251 { 13000000, 594000000, 594, 13, 1, 8},
252 { 19200000, 594000000, 495, 16, 1, 8},
253 { 26000000, 594000000, 594, 26, 1, 8},
255 { 12000000, 1000000000, 1000, 12, 1, 12},
256 { 13000000, 1000000000, 1000, 13, 1, 12},
257 { 19200000, 1000000000, 625, 12, 1, 8},
258 { 26000000, 1000000000, 1000, 26, 1, 12},
260 { 0, 0, 0, 0, 0, 0 },
263 DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
264 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
265 1000, tegra_pll_ops, 0, clk_m);
267 DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
268 tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);
270 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
271 { 12000000, 480000000, 960, 12, 2, 0},
272 { 13000000, 480000000, 960, 13, 2, 0},
273 { 19200000, 480000000, 200, 4, 2, 0},
274 { 26000000, 480000000, 960, 26, 2, 0},
275 { 0, 0, 0, 0, 0, 0 },
278 DEFINE_PLL(pll_u, PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000,
279 48000000, 960000000, tegra_pll_u_freq_table, 1000,
280 tegra_pll_ops, 0, clk_m);
282 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
284 { 12000000, 1000000000, 1000, 12, 1, 12},
285 { 13000000, 1000000000, 1000, 13, 1, 12},
286 { 19200000, 1000000000, 625, 12, 1, 8},
287 { 26000000, 1000000000, 1000, 26, 1, 12},
290 { 12000000, 912000000, 912, 12, 1, 12},
291 { 13000000, 912000000, 912, 13, 1, 12},
292 { 19200000, 912000000, 760, 16, 1, 8},
293 { 26000000, 912000000, 912, 26, 1, 12},
296 { 12000000, 816000000, 816, 12, 1, 12},
297 { 13000000, 816000000, 816, 13, 1, 12},
298 { 19200000, 816000000, 680, 16, 1, 8},
299 { 26000000, 816000000, 816, 26, 1, 12},
302 { 12000000, 760000000, 760, 12, 1, 12},
303 { 13000000, 760000000, 760, 13, 1, 12},
304 { 19200000, 760000000, 950, 24, 1, 8},
305 { 26000000, 760000000, 760, 26, 1, 12},
308 { 12000000, 750000000, 750, 12, 1, 12},
309 { 13000000, 750000000, 750, 13, 1, 12},
310 { 19200000, 750000000, 625, 16, 1, 8},
311 { 26000000, 750000000, 750, 26, 1, 12},
314 { 12000000, 608000000, 608, 12, 1, 12},
315 { 13000000, 608000000, 608, 13, 1, 12},
316 { 19200000, 608000000, 380, 12, 1, 8},
317 { 26000000, 608000000, 608, 26, 1, 12},
320 { 12000000, 456000000, 456, 12, 1, 12},
321 { 13000000, 456000000, 456, 13, 1, 12},
322 { 19200000, 456000000, 380, 16, 1, 8},
323 { 26000000, 456000000, 456, 26, 1, 12},
326 { 12000000, 312000000, 312, 12, 1, 12},
327 { 13000000, 312000000, 312, 13, 1, 12},
328 { 19200000, 312000000, 260, 16, 1, 8},
329 { 26000000, 312000000, 312, 26, 1, 12},
331 { 0, 0, 0, 0, 0, 0 },
334 DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG, 0xe0, 1000000000, 2000000,
335 31000000, 1000000, 6000000, 20000000, 1200000000,
336 tegra_pll_x_freq_table, 300, tegra_pllx_ops, 0, clk_m);
338 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
339 { 12000000, 100000000, 200, 24, 1, 0 },
340 { 0, 0, 0, 0, 0, 0 },
343 DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 12000000, 12000000, 0, 0,
344 0, 0, tegra_pll_e_freq_table, 0, tegra_plle_ops, 0, clk_m);
346 static const char *tegra_common_parent_names[] = {
350 static struct clk *tegra_common_parents[] = {
354 static struct clk tegra_clk_d;
355 static struct clk_tegra tegra_clk_d_hw = {
359 .flags = PERIPH_NO_RESET,
362 .max_rate = 52000000,
368 static struct clk tegra_clk_d = {
370 .hw = &tegra_clk_d_hw.hw,
371 .ops = &tegra_clk_double_ops,
372 .parent = &tegra_clk_m,
373 .parent_names = tegra_common_parent_names,
374 .parents = tegra_common_parents,
375 .num_parents = ARRAY_SIZE(tegra_common_parent_names),
378 static struct clk tegra_cdev1;
379 static struct clk_tegra tegra_cdev1_hw = {
383 .fixed_rate = 26000000,
388 static struct clk tegra_cdev1 = {
390 .hw = &tegra_cdev1_hw.hw,
391 .ops = &tegra_cdev_clk_ops,
392 .flags = CLK_IS_ROOT,
395 /* dap_mclk2, belongs to the cdev2 pingroup. */
396 static struct clk tegra_cdev2;
397 static struct clk_tegra tegra_cdev2_hw = {
401 .fixed_rate = 26000000,
406 static struct clk tegra_cdev2 = {
408 .hw = &tegra_cdev2_hw.hw,
409 .ops = &tegra_cdev_clk_ops,
410 .flags = CLK_IS_ROOT,
413 /* initialized before peripheral clocks */
414 static struct clk_mux_sel mux_audio_sync_clk[8+1];
415 static const struct audio_sources {
418 } mux_audio_sync_clk_sources[] = {
419 { .name = "spdif_in", .value = 0 },
420 { .name = "i2s1", .value = 1 },
421 { .name = "i2s2", .value = 2 },
422 { .name = "pll_a_out0", .value = 4 },
423 #if 0 /* FIXME: not implemented */
424 { .name = "ac97", .value = 3 },
425 { .name = "ext_audio_clk2", .value = 5 },
426 { .name = "ext_audio_clk1", .value = 6 },
427 { .name = "ext_vimclk", .value = 7 },
432 static const char *audio_parent_names[] = {
443 static struct clk *audio_parents[] = {
454 static struct clk tegra_audio;
455 static struct clk_tegra tegra_audio_hw = {
460 .max_rate = 73728000,
462 DEFINE_CLK_TEGRA(audio, 0, &tegra_audio_sync_clk_ops, 0, audio_parent_names,
463 audio_parents, NULL);
465 static const char *audio_2x_parent_names[] = {
469 static struct clk *audio_2x_parents[] = {
473 static struct clk tegra_audio_2x;
474 static struct clk_tegra tegra_audio_2x_hw = {
476 .clk = &tegra_audio_2x,
478 .flags = PERIPH_NO_RESET,
479 .max_rate = 48000000,
486 DEFINE_CLK_TEGRA(audio_2x, 0, &tegra_clk_double_ops, 0, audio_2x_parent_names,
487 audio_2x_parents, &tegra_audio);
489 static struct clk_lookup tegra_audio_clk_lookups[] = {
490 { .con_id = "audio", .clk = &tegra_audio },
491 { .con_id = "audio_2x", .clk = &tegra_audio_2x }
494 /* This is called after peripheral clocks are initialized, as the
495 * audio_sync clock depends on some of the peripheral clocks.
498 static void init_audio_sync_clock_mux(void)
501 struct clk_mux_sel *sel = mux_audio_sync_clk;
502 const struct audio_sources *src = mux_audio_sync_clk_sources;
503 struct clk_lookup *lookup;
505 for (i = 0; src->name; i++, sel++, src++) {
506 sel->input = tegra_get_clock_by_name(src->name);
508 pr_err("%s: could not find clk %s\n", __func__,
510 audio_parents[src->value] = sel->input;
511 sel->value = src->value;
514 lookup = tegra_audio_clk_lookups;
515 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
516 struct clk *c = lookup->clk;
517 struct clk_tegra *clk = to_clk_tegra(c->hw);
519 INIT_LIST_HEAD(&clk->shared_bus_list);
520 clk->lookup.con_id = lookup->con_id;
522 clkdev_add(&clk->lookup);
527 static const char *mux_cclk[] = {
540 static struct clk *mux_cclk_p[] = {
552 static const char *mux_sclk[] = {
563 static struct clk *mux_sclk_p[] = {
574 static struct clk tegra_cclk;
575 static struct clk_tegra tegra_cclk_hw = {
580 .max_rate = 1000000000,
582 DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk,
585 static const char *mux_twd[] = {
589 static struct clk *mux_twd_p[] = {
593 static struct clk tegra_clk_twd;
594 static struct clk_tegra tegra_clk_twd_hw = {
596 .clk = &tegra_clk_twd,
598 .max_rate = 1000000000,
603 static struct clk tegra_clk_twd = {
605 .ops = &tegra_twd_ops,
606 .hw = &tegra_clk_twd_hw.hw,
607 .parent = &tegra_cclk,
608 .parent_names = mux_twd,
609 .parents = mux_twd_p,
610 .num_parents = ARRAY_SIZE(mux_twd),
613 static struct clk tegra_sclk;
614 static struct clk_tegra tegra_sclk_hw = {
619 .max_rate = 240000000,
620 .min_rate = 120000000,
622 DEFINE_CLK_TEGRA(sclk, 0, &tegra_super_ops, 0, mux_sclk,
625 static const char *tegra_cop_parent_names[] = {
629 static struct clk *tegra_cop_parents[] = {
633 static struct clk tegra_cop;
634 static struct clk_tegra tegra_cop_hw = {
638 .max_rate = 240000000,
639 .reset = &tegra2_cop_clk_reset,
641 DEFINE_CLK_TEGRA(cop, 0, &tegra_cop_ops, CLK_SET_RATE_PARENT,
642 tegra_cop_parent_names, tegra_cop_parents, &tegra_sclk);
644 static const char *tegra_hclk_parent_names[] = {
648 static struct clk *tegra_hclk_parents[] = {
652 static struct clk tegra_hclk;
653 static struct clk_tegra tegra_hclk_hw = {
660 .max_rate = 240000000,
662 DEFINE_CLK_TEGRA(hclk, 0, &tegra_bus_ops, 0, tegra_hclk_parent_names,
663 tegra_hclk_parents, &tegra_sclk);
665 static const char *tegra_pclk_parent_names[] = {
669 static struct clk *tegra_pclk_parents[] = {
673 static struct clk tegra_pclk;
674 static struct clk_tegra tegra_pclk_hw = {
681 .max_rate = 120000000,
683 DEFINE_CLK_TEGRA(pclk, 0, &tegra_bus_ops, 0, tegra_pclk_parent_names,
684 tegra_pclk_parents, &tegra_hclk);
686 static const char *tegra_blink_parent_names[] = {
690 static struct clk *tegra_blink_parents[] = {
694 static struct clk tegra_blink;
695 static struct clk_tegra tegra_blink_hw = {
702 DEFINE_CLK_TEGRA(blink, 0, &tegra_blink_clk_ops, 0, tegra_blink_parent_names,
703 tegra_blink_parents, &tegra_clk_32k);
705 static const char *mux_pllm_pllc_pllp_plla[] = {
712 static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
719 static const char *mux_pllm_pllc_pllp_clkm[] = {
726 static struct clk *mux_pllm_pllc_pllp_clkm_p[] = {
733 static const char *mux_pllp_pllc_pllm_clkm[] = {
740 static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
747 static const char *mux_pllaout0_audio2x_pllp_clkm[] = {
754 static struct clk *mux_pllaout0_audio2x_pllp_clkm_p[] = {
761 static const char *mux_pllp_plld_pllc_clkm[] = {
768 static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
775 static const char *mux_pllp_pllc_audio_clkm_clk32[] = {
783 static struct clk *mux_pllp_pllc_audio_clkm_clk32_p[] = {
791 static const char *mux_pllp_pllc_pllm[] = {
797 static struct clk *mux_pllp_pllc_pllm_p[] = {
803 static const char *mux_clk_m[] = {
807 static struct clk *mux_clk_m_p[] = {
811 static const char *mux_pllp_out3[] = {
815 static struct clk *mux_pllp_out3_p[] = {
819 static const char *mux_plld[] = {
823 static struct clk *mux_plld_p[] = {
827 static const char *mux_clk_32k[] = {
831 static struct clk *mux_clk_32k_p[] = {
835 static const char *mux_pclk[] = {
839 static struct clk *mux_pclk_p[] = {
843 static struct clk tegra_emc;
844 static struct clk_tegra tegra_emc_hw = {
849 .max_rate = 800000000,
850 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
851 .reset = &tegra2_periph_clk_reset,
856 DEFINE_CLK_TEGRA(emc, 0, &tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm,
857 mux_pllm_pllc_pllp_clkm_p, NULL);
859 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
860 _max, _inputs, _flags) \
861 static struct clk tegra_##_name; \
862 static struct clk_tegra tegra_##_name##_hw = { \
864 .clk = &tegra_##_name, \
874 .clk_num = _clk_num, \
876 .reset = tegra2_periph_clk_reset, \
878 static struct clk tegra_##_name = { \
880 .ops = &tegra_periph_clk_ops, \
881 .hw = &tegra_##_name##_hw.hw, \
882 .parent_names = _inputs, \
883 .parents = _inputs##_p, \
884 .num_parents = ARRAY_SIZE(_inputs), \
887 PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0);
888 PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET);
889 PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
890 PERIPH_CLK(i2s1, "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
891 PERIPH_CLK(i2s2, "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
892 PERIPH_CLK(spdif_out, "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
893 PERIPH_CLK(spdif_in, "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71);
894 PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM);
895 PERIPH_CLK(spi, "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
896 PERIPH_CLK(xio, "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
897 PERIPH_CLK(twc, "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
898 PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
899 PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
900 PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
901 PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
902 PERIPH_CLK(ide, "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
903 PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
904 PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
905 PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
906 PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
907 PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
908 PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
909 PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
910 PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
911 PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
912 PERIPH_CLK(vde, "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage and process_id */
913 PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
914 /* FIXME: what is la? */
915 PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
916 PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
917 PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
918 PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
919 PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
920 PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
921 PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
922 PERIPH_CLK(dvc, "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
923 PERIPH_CLK(i2c1_i2c, "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
924 PERIPH_CLK(i2c2_i2c, "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
925 PERIPH_CLK(i2c3_i2c, "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
926 PERIPH_CLK(dvc_i2c, "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
927 PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
928 PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
929 PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
930 PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
931 PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
932 PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET); /* scales with voltage and process_id */
933 PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
934 PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
935 PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET); /* scales with voltage and process_id */
936 PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
937 PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
938 PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
939 PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
940 PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
941 PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
942 PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
943 PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
944 PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
945 PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
946 PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
947 PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
948 PERIPH_CLK(dsi, "dsi", NULL, 48, 0, 500000000, mux_plld, 0); /* scales with voltage */
949 PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0);
950 PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
951 PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
952 PERIPH_CLK(pex, NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
953 PERIPH_CLK(afi, NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
954 PERIPH_CLK(pcie_xclk, NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
956 static struct clk *tegra_list_clks[] = {
1025 #define CLK_DUPLICATE(_name, _dev, _con) \
1034 /* Some clocks may be used by different drivers depending on the board
1035 * configuration. List those here to register them twice in the clock lookup
1036 * table under two names.
1038 static struct clk_duplicate tegra_clk_duplicates[] = {
1039 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
1040 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
1041 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
1042 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
1043 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
1044 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1045 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1046 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1047 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
1048 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
1049 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
1050 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
1051 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
1052 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
1053 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
1054 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
1055 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1056 CLK_DUPLICATE("cclk", NULL, "cpu"),
1057 CLK_DUPLICATE("twd", "smp_twd", NULL),
1060 #define CLK(dev, con, ck) \
1067 static struct clk *tegra_ptr_clks[] = {
1100 static void tegra2_init_one_clock(struct clk *c)
1102 struct clk_tegra *clk = to_clk_tegra(c->hw);
1105 ret = __clk_init(NULL, c);
1107 pr_err("clk init failed %s\n", __clk_get_name(c));
1109 INIT_LIST_HEAD(&clk->shared_bus_list);
1110 if (!clk->lookup.dev_id && !clk->lookup.con_id)
1111 clk->lookup.con_id = c->name;
1112 clk->lookup.clk = c;
1113 clkdev_add(&clk->lookup);
1117 void __init tegra2_init_clocks(void)
1122 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1123 tegra2_init_one_clock(tegra_ptr_clks[i]);
1125 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1126 tegra2_init_one_clock(tegra_list_clks[i]);
1128 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1129 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1131 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1132 tegra_clk_duplicates[i].name);
1136 tegra_clk_duplicates[i].lookup.clk = c;
1137 clkdev_add(&tegra_clk_duplicates[i].lookup);
1140 init_audio_sync_clock_mux();