2 * arch/arm/mach-tegra/tegra2_clocks.c
4 * Copyright (C) 2010 Google, Inc.
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/spinlock.h>
24 #include <linux/delay.h>
26 #include <linux/clkdev.h>
27 #include <linux/clk.h>
29 #include <mach/iomap.h>
30 #include <mach/suspend.h>
34 #include "tegra2_emc.h"
36 #define RST_DEVICES 0x004
37 #define RST_DEVICES_SET 0x300
38 #define RST_DEVICES_CLR 0x304
39 #define RST_DEVICES_NUM 3
41 #define CLK_OUT_ENB 0x010
42 #define CLK_OUT_ENB_SET 0x320
43 #define CLK_OUT_ENB_CLR 0x324
44 #define CLK_OUT_ENB_NUM 3
46 #define CLK_MASK_ARM 0x44
47 #define MISC_CLK_ENB 0x48
50 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
51 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
52 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
53 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
54 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
55 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
57 #define OSC_FREQ_DET 0x58
58 #define OSC_FREQ_DET_TRIG (1<<31)
60 #define OSC_FREQ_DET_STATUS 0x5C
61 #define OSC_FREQ_DET_BUSY (1<<31)
62 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
64 #define PERIPH_CLK_SOURCE_I2S1 0x100
65 #define PERIPH_CLK_SOURCE_EMC 0x19c
66 #define PERIPH_CLK_SOURCE_OSC 0x1fc
67 #define PERIPH_CLK_SOURCE_NUM \
68 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
70 #define PERIPH_CLK_SOURCE_MASK (3<<30)
71 #define PERIPH_CLK_SOURCE_SHIFT 30
72 #define PERIPH_CLK_SOURCE_ENABLE (1<<28)
73 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
74 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
75 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
77 #define SDMMC_CLK_INT_FB_SEL (1 << 23)
78 #define SDMMC_CLK_INT_FB_DLY_SHIFT 16
79 #define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
82 #define PLL_BASE_BYPASS (1<<31)
83 #define PLL_BASE_ENABLE (1<<30)
84 #define PLL_BASE_REF_ENABLE (1<<29)
85 #define PLL_BASE_OVERRIDE (1<<28)
86 #define PLL_BASE_DIVP_MASK (0x7<<20)
87 #define PLL_BASE_DIVP_SHIFT 20
88 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
89 #define PLL_BASE_DIVN_SHIFT 8
90 #define PLL_BASE_DIVM_MASK (0x1F)
91 #define PLL_BASE_DIVM_SHIFT 0
93 #define PLL_OUT_RATIO_MASK (0xFF<<8)
94 #define PLL_OUT_RATIO_SHIFT 8
95 #define PLL_OUT_OVERRIDE (1<<2)
96 #define PLL_OUT_CLKEN (1<<1)
97 #define PLL_OUT_RESET_DISABLE (1<<0)
99 #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
101 #define PLL_MISC_DCCON_SHIFT 20
102 #define PLL_MISC_CPCON_SHIFT 8
103 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
104 #define PLL_MISC_LFCON_SHIFT 4
105 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
106 #define PLL_MISC_VCOCON_SHIFT 0
107 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
109 #define PLLU_BASE_POST_DIV (1<<20)
111 #define PLLD_MISC_CLKENABLE (1<<30)
112 #define PLLD_MISC_DIV_RST (1<<23)
113 #define PLLD_MISC_DCCON_SHIFT 12
115 #define PLLE_MISC_READY (1 << 15)
117 #define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
118 #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
119 #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
121 #define SUPER_CLK_MUX 0x00
122 #define SUPER_STATE_SHIFT 28
123 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
124 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
125 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
126 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
127 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
128 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
129 #define SUPER_SOURCE_MASK 0xF
130 #define SUPER_FIQ_SOURCE_SHIFT 12
131 #define SUPER_IRQ_SOURCE_SHIFT 8
132 #define SUPER_RUN_SOURCE_SHIFT 4
133 #define SUPER_IDLE_SOURCE_SHIFT 0
135 #define SUPER_CLK_DIVIDER 0x04
137 #define BUS_CLK_DISABLE (1<<3)
138 #define BUS_CLK_DIV_MASK 0x3
141 #define PMC_CTRL_BLINK_ENB (1 << 7)
143 #define PMC_DPD_PADS_ORIDE 0x1c
144 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
146 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
147 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
148 #define PMC_BLINK_TIMER_ENB (1 << 15)
149 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
150 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
152 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
153 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
156 * Some clocks share a register with other clocks. Any clock op that
157 * non-atomically modifies a register used by another clock must lock
158 * clock_register_lock first.
160 static DEFINE_SPINLOCK(clock_register_lock);
162 #define clk_writel(value, reg) \
163 __raw_writel(value, (u32)reg_clk_base + (reg))
164 #define clk_readl(reg) \
165 __raw_readl((u32)reg_clk_base + (reg))
166 #define pmc_writel(value, reg) \
167 __raw_writel(value, (u32)reg_pmc_base + (reg))
168 #define pmc_readl(reg) \
169 __raw_readl((u32)reg_pmc_base + (reg))
171 unsigned long clk_measure_input_freq(void)
173 u32 clock_autodetect;
174 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
175 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
176 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
177 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
179 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
181 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
183 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
186 pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
192 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
194 s64 divider_u71 = parent_rate * 2;
195 divider_u71 += rate - 1;
196 do_div(divider_u71, rate);
198 if (divider_u71 - 2 < 0)
201 if (divider_u71 - 2 > 255)
204 return divider_u71 - 2;
207 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
211 divider_u16 = parent_rate;
212 divider_u16 += rate - 1;
213 do_div(divider_u16, rate);
215 if (divider_u16 - 1 < 0)
218 if (divider_u16 - 1 > 255)
221 return divider_u16 - 1;
224 /* clk_m functions */
225 static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
227 u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
229 c->rate = clk_measure_input_freq();
232 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
235 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
238 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
241 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
244 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
247 clk_writel(auto_clock_control, OSC_CTRL);
251 static void tegra2_clk_m_init(struct clk *c)
253 pr_debug("%s on clock %s\n", __func__, c->name);
254 tegra2_clk_m_autodetect_rate(c);
257 static int tegra2_clk_m_enable(struct clk *c)
259 pr_debug("%s on clock %s\n", __func__, c->name);
263 static void tegra2_clk_m_disable(struct clk *c)
265 pr_debug("%s on clock %s\n", __func__, c->name);
269 static struct clk_ops tegra_clk_m_ops = {
270 .init = tegra2_clk_m_init,
271 .enable = tegra2_clk_m_enable,
272 .disable = tegra2_clk_m_disable,
275 void tegra2_periph_reset_assert(struct clk *c)
277 BUG_ON(!c->ops->reset);
278 c->ops->reset(c, true);
281 void tegra2_periph_reset_deassert(struct clk *c)
283 BUG_ON(!c->ops->reset);
284 c->ops->reset(c, false);
287 /* super clock functions */
288 /* "super clocks" on tegra have two-stage muxes and a clock skipping
289 * super divider. We will ignore the clock skipping divider, since we
290 * can't lower the voltage when using the clock skip, but we can if we
291 * lower the PLL frequency.
293 static void tegra2_super_clk_init(struct clk *c)
298 const struct clk_mux_sel *sel;
299 val = clk_readl(c->reg + SUPER_CLK_MUX);
301 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
302 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
303 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
304 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
305 source = (val >> shift) & SUPER_SOURCE_MASK;
306 for (sel = c->inputs; sel->input != NULL; sel++) {
307 if (sel->value == source)
310 BUG_ON(sel->input == NULL);
311 c->parent = sel->input;
314 static int tegra2_super_clk_enable(struct clk *c)
316 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
320 static void tegra2_super_clk_disable(struct clk *c)
322 pr_debug("%s on clock %s\n", __func__, c->name);
324 /* oops - don't disable the CPU clock! */
328 static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
331 const struct clk_mux_sel *sel;
334 val = clk_readl(c->reg + SUPER_CLK_MUX);;
335 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
336 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
337 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
338 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
339 for (sel = c->inputs; sel->input != NULL; sel++) {
340 if (sel->input == p) {
341 val &= ~(SUPER_SOURCE_MASK << shift);
342 val |= sel->value << shift;
347 clk_writel(val, c->reg);
349 if (c->refcnt && c->parent)
350 clk_disable(c->parent);
360 * Super clocks have "clock skippers" instead of dividers. Dividing using
361 * a clock skipper does not allow the voltage to be scaled down, so instead
362 * adjust the rate of the parent clock. This requires that the parent of a
363 * super clock have no other children, otherwise the rate will change
364 * underneath the other children.
366 static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
368 return clk_set_rate(c->parent, rate);
371 static struct clk_ops tegra_super_ops = {
372 .init = tegra2_super_clk_init,
373 .enable = tegra2_super_clk_enable,
374 .disable = tegra2_super_clk_disable,
375 .set_parent = tegra2_super_clk_set_parent,
376 .set_rate = tegra2_super_clk_set_rate,
379 /* virtual cpu clock functions */
380 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
381 To change the frequency of these clocks, the parent pll may need to be
382 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
383 and then the clock moved back to the pll. To hide this sequence, a virtual
386 static void tegra2_cpu_clk_init(struct clk *c)
390 static int tegra2_cpu_clk_enable(struct clk *c)
395 static void tegra2_cpu_clk_disable(struct clk *c)
397 pr_debug("%s on clock %s\n", __func__, c->name);
399 /* oops - don't disable the CPU clock! */
403 static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
407 * Take an extra reference to the main pll so it doesn't turn
408 * off when we move the cpu off of it
410 clk_enable(c->u.cpu.main);
412 ret = clk_set_parent(c->parent, c->u.cpu.backup);
414 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
418 if (rate == clk_get_rate(c->u.cpu.backup))
421 ret = clk_set_rate(c->u.cpu.main, rate);
423 pr_err("Failed to change cpu pll to %lu\n", rate);
427 ret = clk_set_parent(c->parent, c->u.cpu.main);
429 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
434 clk_disable(c->u.cpu.main);
438 static struct clk_ops tegra_cpu_ops = {
439 .init = tegra2_cpu_clk_init,
440 .enable = tegra2_cpu_clk_enable,
441 .disable = tegra2_cpu_clk_disable,
442 .set_rate = tegra2_cpu_clk_set_rate,
445 /* virtual cop clock functions. Used to acquire the fake 'cop' clock to
446 * reset the COP block (i.e. AVP) */
447 static void tegra2_cop_clk_reset(struct clk *c, bool assert)
449 unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
451 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
452 clk_writel(1 << 1, reg);
455 static struct clk_ops tegra_cop_ops = {
456 .reset = tegra2_cop_clk_reset,
459 /* bus clock functions */
460 static void tegra2_bus_clk_init(struct clk *c)
462 u32 val = clk_readl(c->reg);
463 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
464 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
468 static int tegra2_bus_clk_enable(struct clk *c)
473 spin_lock_irqsave(&clock_register_lock, flags);
475 val = clk_readl(c->reg);
476 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
477 clk_writel(val, c->reg);
479 spin_unlock_irqrestore(&clock_register_lock, flags);
484 static void tegra2_bus_clk_disable(struct clk *c)
489 spin_lock_irqsave(&clock_register_lock, flags);
491 val = clk_readl(c->reg);
492 val |= BUS_CLK_DISABLE << c->reg_shift;
493 clk_writel(val, c->reg);
495 spin_unlock_irqrestore(&clock_register_lock, flags);
498 static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
501 unsigned long parent_rate = clk_get_rate(c->parent);
506 spin_lock_irqsave(&clock_register_lock, flags);
508 val = clk_readl(c->reg);
509 for (i = 1; i <= 4; i++) {
510 if (rate == parent_rate / i) {
511 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
512 val |= (i - 1) << c->reg_shift;
513 clk_writel(val, c->reg);
521 spin_unlock_irqrestore(&clock_register_lock, flags);
526 static struct clk_ops tegra_bus_ops = {
527 .init = tegra2_bus_clk_init,
528 .enable = tegra2_bus_clk_enable,
529 .disable = tegra2_bus_clk_disable,
530 .set_rate = tegra2_bus_clk_set_rate,
533 /* Blink output functions */
535 static void tegra2_blink_clk_init(struct clk *c)
539 val = pmc_readl(PMC_CTRL);
540 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
542 val = pmc_readl(c->reg);
544 if (val & PMC_BLINK_TIMER_ENB) {
547 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
548 PMC_BLINK_TIMER_DATA_ON_MASK;
549 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
550 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
552 /* each tick in the blink timer is 4 32KHz clocks */
559 static int tegra2_blink_clk_enable(struct clk *c)
563 val = pmc_readl(PMC_DPD_PADS_ORIDE);
564 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
566 val = pmc_readl(PMC_CTRL);
567 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
572 static void tegra2_blink_clk_disable(struct clk *c)
576 val = pmc_readl(PMC_CTRL);
577 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
579 val = pmc_readl(PMC_DPD_PADS_ORIDE);
580 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
583 static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
585 unsigned long parent_rate = clk_get_rate(c->parent);
586 if (rate >= parent_rate) {
588 pmc_writel(0, c->reg);
593 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
596 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
597 PMC_BLINK_TIMER_DATA_ON_SHIFT;
598 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
599 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
601 val |= PMC_BLINK_TIMER_ENB;
602 pmc_writel(val, c->reg);
608 static struct clk_ops tegra_blink_clk_ops = {
609 .init = &tegra2_blink_clk_init,
610 .enable = &tegra2_blink_clk_enable,
611 .disable = &tegra2_blink_clk_disable,
612 .set_rate = &tegra2_blink_clk_set_rate,
616 static int tegra2_pll_clk_wait_for_lock(struct clk *c)
618 udelay(c->u.pll.lock_delay);
623 static void tegra2_pll_clk_init(struct clk *c)
625 u32 val = clk_readl(c->reg + PLL_BASE);
627 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
629 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
630 pr_warning("Clock %s has unknown fixed frequency\n", c->name);
633 } else if (val & PLL_BASE_BYPASS) {
637 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
638 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
640 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
642 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
646 static int tegra2_pll_clk_enable(struct clk *c)
649 pr_debug("%s on clock %s\n", __func__, c->name);
651 val = clk_readl(c->reg + PLL_BASE);
652 val &= ~PLL_BASE_BYPASS;
653 val |= PLL_BASE_ENABLE;
654 clk_writel(val, c->reg + PLL_BASE);
656 tegra2_pll_clk_wait_for_lock(c);
661 static void tegra2_pll_clk_disable(struct clk *c)
664 pr_debug("%s on clock %s\n", __func__, c->name);
666 val = clk_readl(c->reg);
667 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
668 clk_writel(val, c->reg);
671 static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
674 unsigned long input_rate;
675 const struct clk_pll_freq_table *sel;
677 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
679 input_rate = clk_get_rate(c->parent);
680 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
681 if (sel->input_rate == input_rate && sel->output_rate == rate) {
683 c->div = sel->m * sel->p;
685 val = clk_readl(c->reg + PLL_BASE);
686 if (c->flags & PLL_FIXED)
687 val |= PLL_BASE_OVERRIDE;
688 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
690 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
691 (sel->n << PLL_BASE_DIVN_SHIFT);
692 BUG_ON(sel->p < 1 || sel->p > 2);
693 if (c->flags & PLLU) {
695 val |= PLLU_BASE_POST_DIV;
698 val |= 1 << PLL_BASE_DIVP_SHIFT;
700 clk_writel(val, c->reg + PLL_BASE);
702 if (c->flags & PLL_HAS_CPCON) {
703 val = clk_readl(c->reg + PLL_MISC(c));
704 val &= ~PLL_MISC_CPCON_MASK;
705 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
706 clk_writel(val, c->reg + PLL_MISC(c));
710 tegra2_pll_clk_enable(c);
718 static struct clk_ops tegra_pll_ops = {
719 .init = tegra2_pll_clk_init,
720 .enable = tegra2_pll_clk_enable,
721 .disable = tegra2_pll_clk_disable,
722 .set_rate = tegra2_pll_clk_set_rate,
725 static void tegra2_pllx_clk_init(struct clk *c)
727 tegra2_pll_clk_init(c);
729 if (tegra_sku_id() == 7)
730 c->max_rate = 750000000;
733 static struct clk_ops tegra_pllx_ops = {
734 .init = tegra2_pllx_clk_init,
735 .enable = tegra2_pll_clk_enable,
736 .disable = tegra2_pll_clk_disable,
737 .set_rate = tegra2_pll_clk_set_rate,
740 static int tegra2_plle_clk_enable(struct clk *c)
744 pr_debug("%s on clock %s\n", __func__, c->name);
748 val = clk_readl(c->reg + PLL_BASE);
749 if (!(val & PLLE_MISC_READY))
752 val = clk_readl(c->reg + PLL_BASE);
753 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
754 clk_writel(val, c->reg + PLL_BASE);
759 static struct clk_ops tegra_plle_ops = {
760 .init = tegra2_pll_clk_init,
761 .enable = tegra2_plle_clk_enable,
762 .set_rate = tegra2_pll_clk_set_rate,
765 /* Clock divider ops */
766 static void tegra2_pll_div_clk_init(struct clk *c)
768 u32 val = clk_readl(c->reg);
770 val >>= c->reg_shift;
771 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
772 if (!(val & PLL_OUT_RESET_DISABLE))
775 if (c->flags & DIV_U71) {
776 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
777 c->div = (divu71 + 2);
779 } else if (c->flags & DIV_2) {
788 static int tegra2_pll_div_clk_enable(struct clk *c)
794 pr_debug("%s: %s\n", __func__, c->name);
795 if (c->flags & DIV_U71) {
796 spin_lock_irqsave(&clock_register_lock, flags);
797 val = clk_readl(c->reg);
798 new_val = val >> c->reg_shift;
801 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
803 val &= ~(0xFFFF << c->reg_shift);
804 val |= new_val << c->reg_shift;
805 clk_writel(val, c->reg);
806 spin_unlock_irqrestore(&clock_register_lock, flags);
808 } else if (c->flags & DIV_2) {
809 BUG_ON(!(c->flags & PLLD));
810 spin_lock_irqsave(&clock_register_lock, flags);
811 val = clk_readl(c->reg);
812 val &= ~PLLD_MISC_DIV_RST;
813 clk_writel(val, c->reg);
814 spin_unlock_irqrestore(&clock_register_lock, flags);
820 static void tegra2_pll_div_clk_disable(struct clk *c)
826 pr_debug("%s: %s\n", __func__, c->name);
827 if (c->flags & DIV_U71) {
828 spin_lock_irqsave(&clock_register_lock, flags);
829 val = clk_readl(c->reg);
830 new_val = val >> c->reg_shift;
833 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
835 val &= ~(0xFFFF << c->reg_shift);
836 val |= new_val << c->reg_shift;
837 clk_writel(val, c->reg);
838 spin_unlock_irqrestore(&clock_register_lock, flags);
839 } else if (c->flags & DIV_2) {
840 BUG_ON(!(c->flags & PLLD));
841 spin_lock_irqsave(&clock_register_lock, flags);
842 val = clk_readl(c->reg);
843 val |= PLLD_MISC_DIV_RST;
844 clk_writel(val, c->reg);
845 spin_unlock_irqrestore(&clock_register_lock, flags);
849 static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
854 unsigned long parent_rate = clk_get_rate(c->parent);
857 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
858 if (c->flags & DIV_U71) {
859 divider_u71 = clk_div71_get_divider(parent_rate, rate);
860 if (divider_u71 >= 0) {
861 spin_lock_irqsave(&clock_register_lock, flags);
862 val = clk_readl(c->reg);
863 new_val = val >> c->reg_shift;
865 if (c->flags & DIV_U71_FIXED)
866 new_val |= PLL_OUT_OVERRIDE;
867 new_val &= ~PLL_OUT_RATIO_MASK;
868 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
870 val &= ~(0xFFFF << c->reg_shift);
871 val |= new_val << c->reg_shift;
872 clk_writel(val, c->reg);
873 c->div = divider_u71 + 2;
875 spin_unlock_irqrestore(&clock_register_lock, flags);
878 } else if (c->flags & DIV_2) {
879 if (parent_rate == rate * 2)
885 static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
888 unsigned long parent_rate = clk_get_rate(c->parent);
889 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
891 if (c->flags & DIV_U71) {
892 divider = clk_div71_get_divider(parent_rate, rate);
895 return parent_rate * 2 / (divider + 2);
896 } else if (c->flags & DIV_2) {
897 return parent_rate / 2;
902 static struct clk_ops tegra_pll_div_ops = {
903 .init = tegra2_pll_div_clk_init,
904 .enable = tegra2_pll_div_clk_enable,
905 .disable = tegra2_pll_div_clk_disable,
906 .set_rate = tegra2_pll_div_clk_set_rate,
907 .round_rate = tegra2_pll_div_clk_round_rate,
912 static void tegra2_periph_clk_init(struct clk *c)
914 u32 val = clk_readl(c->reg);
915 const struct clk_mux_sel *mux = 0;
916 const struct clk_mux_sel *sel;
917 if (c->flags & MUX) {
918 for (sel = c->inputs; sel->input != NULL; sel++) {
919 if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
924 c->parent = mux->input;
926 c->parent = c->inputs[0].input;
929 if (c->flags & DIV_U71) {
930 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
933 } else if (c->flags & DIV_U16) {
934 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
943 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
944 PERIPH_CLK_TO_ENB_BIT(c)))
946 if (!(c->flags & PERIPH_NO_RESET))
947 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
948 PERIPH_CLK_TO_ENB_BIT(c))
952 static int tegra2_periph_clk_enable(struct clk *c)
955 pr_debug("%s on clock %s\n", __func__, c->name);
957 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
958 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
959 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
960 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
961 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
962 if (c->flags & PERIPH_EMC_ENB) {
963 /* The EMC peripheral clock has 2 extra enable bits */
964 /* FIXME: Do they need to be disabled? */
965 val = clk_readl(c->reg);
967 clk_writel(val, c->reg);
972 static void tegra2_periph_clk_disable(struct clk *c)
974 pr_debug("%s on clock %s\n", __func__, c->name);
976 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
977 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
980 static void tegra2_periph_clk_reset(struct clk *c, bool assert)
982 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
984 pr_debug("%s %s on clock %s\n", __func__,
985 assert ? "assert" : "deassert", c->name);
986 if (!(c->flags & PERIPH_NO_RESET))
987 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
988 base + PERIPH_CLK_TO_ENB_SET_REG(c));
991 static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
994 const struct clk_mux_sel *sel;
995 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
996 for (sel = c->inputs; sel->input != NULL; sel++) {
997 if (sel->input == p) {
998 val = clk_readl(c->reg);
999 val &= ~PERIPH_CLK_SOURCE_MASK;
1000 val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
1005 clk_writel(val, c->reg);
1007 if (c->refcnt && c->parent)
1008 clk_disable(c->parent);
1018 static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
1022 unsigned long parent_rate = clk_get_rate(c->parent);
1024 if (c->flags & DIV_U71) {
1025 divider = clk_div71_get_divider(parent_rate, rate);
1027 val = clk_readl(c->reg);
1028 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1030 clk_writel(val, c->reg);
1031 c->div = divider + 2;
1035 } else if (c->flags & DIV_U16) {
1036 divider = clk_div16_get_divider(parent_rate, rate);
1038 val = clk_readl(c->reg);
1039 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1041 clk_writel(val, c->reg);
1042 c->div = divider + 1;
1046 } else if (parent_rate <= rate) {
1054 static long tegra2_periph_clk_round_rate(struct clk *c,
1058 unsigned long parent_rate = clk_get_rate(c->parent);
1059 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1061 if (c->flags & DIV_U71) {
1062 divider = clk_div71_get_divider(parent_rate, rate);
1066 return parent_rate * 2 / (divider + 2);
1067 } else if (c->flags & DIV_U16) {
1068 divider = clk_div16_get_divider(parent_rate, rate);
1071 return parent_rate / (divider + 1);
1076 static struct clk_ops tegra_periph_clk_ops = {
1077 .init = &tegra2_periph_clk_init,
1078 .enable = &tegra2_periph_clk_enable,
1079 .disable = &tegra2_periph_clk_disable,
1080 .set_parent = &tegra2_periph_clk_set_parent,
1081 .set_rate = &tegra2_periph_clk_set_rate,
1082 .round_rate = &tegra2_periph_clk_round_rate,
1083 .reset = &tegra2_periph_clk_reset,
1086 /* The SDMMC controllers have extra bits in the clock source register that
1087 * adjust the delay between the clock and data to compenstate for delays
1089 void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
1093 delay = clamp(delay, 0, 15);
1094 reg = clk_readl(c->reg);
1095 reg &= ~SDMMC_CLK_INT_FB_DLY_MASK;
1096 reg |= SDMMC_CLK_INT_FB_SEL;
1097 reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
1098 clk_writel(reg, c->reg);
1101 /* External memory controller clock ops */
1102 static void tegra2_emc_clk_init(struct clk *c)
1104 tegra2_periph_clk_init(c);
1105 c->max_rate = clk_get_rate_locked(c);
1108 static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
1110 long new_rate = rate;
1112 new_rate = tegra_emc_round_rate(new_rate);
1116 BUG_ON(new_rate != tegra2_periph_clk_round_rate(c, new_rate));
1121 static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
1125 * The Tegra2 memory controller has an interlock with the clock
1126 * block that allows memory shadowed registers to be updated,
1127 * and then transfer them to the main registers at the same
1128 * time as the clock update without glitches.
1130 ret = tegra_emc_set_rate(rate);
1134 ret = tegra2_periph_clk_set_rate(c, rate);
1140 static struct clk_ops tegra_emc_clk_ops = {
1141 .init = &tegra2_emc_clk_init,
1142 .enable = &tegra2_periph_clk_enable,
1143 .disable = &tegra2_periph_clk_disable,
1144 .set_parent = &tegra2_periph_clk_set_parent,
1145 .set_rate = &tegra2_emc_clk_set_rate,
1146 .round_rate = &tegra2_emc_clk_round_rate,
1147 .reset = &tegra2_periph_clk_reset,
1150 /* Clock doubler ops */
1151 static void tegra2_clk_double_init(struct clk *c)
1156 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1157 PERIPH_CLK_TO_ENB_BIT(c)))
1161 static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
1163 if (rate != 2 * clk_get_rate(c->parent))
1170 static struct clk_ops tegra_clk_double_ops = {
1171 .init = &tegra2_clk_double_init,
1172 .enable = &tegra2_periph_clk_enable,
1173 .disable = &tegra2_periph_clk_disable,
1174 .set_rate = &tegra2_clk_double_set_rate,
1177 /* Audio sync clock ops */
1178 static void tegra2_audio_sync_clk_init(struct clk *c)
1181 const struct clk_mux_sel *sel;
1182 u32 val = clk_readl(c->reg);
1183 c->state = (val & (1<<4)) ? OFF : ON;
1185 for (sel = c->inputs; sel->input != NULL; sel++)
1186 if (sel->value == source)
1188 BUG_ON(sel->input == NULL);
1189 c->parent = sel->input;
1192 static int tegra2_audio_sync_clk_enable(struct clk *c)
1194 clk_writel(0, c->reg);
1198 static void tegra2_audio_sync_clk_disable(struct clk *c)
1200 clk_writel(1, c->reg);
1203 static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
1206 const struct clk_mux_sel *sel;
1207 for (sel = c->inputs; sel->input != NULL; sel++) {
1208 if (sel->input == p) {
1209 val = clk_readl(c->reg);
1216 clk_writel(val, c->reg);
1218 if (c->refcnt && c->parent)
1219 clk_disable(c->parent);
1229 static struct clk_ops tegra_audio_sync_clk_ops = {
1230 .init = tegra2_audio_sync_clk_init,
1231 .enable = tegra2_audio_sync_clk_enable,
1232 .disable = tegra2_audio_sync_clk_disable,
1233 .set_parent = tegra2_audio_sync_clk_set_parent,
1236 /* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1238 static void tegra2_cdev_clk_init(struct clk *c)
1240 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1241 * currently done in the pinmux code. */
1243 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1244 PERIPH_CLK_TO_ENB_BIT(c)))
1248 static int tegra2_cdev_clk_enable(struct clk *c)
1250 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1251 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1255 static void tegra2_cdev_clk_disable(struct clk *c)
1257 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1258 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1261 static struct clk_ops tegra_cdev_clk_ops = {
1262 .init = &tegra2_cdev_clk_init,
1263 .enable = &tegra2_cdev_clk_enable,
1264 .disable = &tegra2_cdev_clk_disable,
1267 /* shared bus ops */
1269 * Some clocks may have multiple downstream users that need to request a
1270 * higher clock rate. Shared bus clocks provide a unique shared_bus_user
1271 * clock to each user. The frequency of the bus is set to the highest
1272 * enabled shared_bus_user clock, with a minimum value set by the
1275 static int tegra_clk_shared_bus_update(struct clk *bus)
1278 unsigned long rate = bus->min_rate;
1280 list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node)
1281 if (c->u.shared_bus_user.enabled)
1282 rate = max(c->u.shared_bus_user.rate, rate);
1284 if (rate == clk_get_rate_locked(bus))
1287 return clk_set_rate_locked(bus, rate);
1290 static void tegra_clk_shared_bus_init(struct clk *c)
1292 unsigned long flags;
1294 c->max_rate = c->parent->max_rate;
1295 c->u.shared_bus_user.rate = c->parent->max_rate;
1299 spin_lock_irqsave(&c->parent->spinlock, flags);
1301 list_add_tail(&c->u.shared_bus_user.node,
1302 &c->parent->shared_bus_list);
1304 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1307 static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
1309 unsigned long flags;
1312 rate = clk_round_rate(c->parent, rate);
1316 spin_lock_irqsave(&c->parent->spinlock, flags);
1318 c->u.shared_bus_user.rate = rate;
1319 ret = tegra_clk_shared_bus_update(c->parent);
1321 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1326 static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
1328 return clk_round_rate(c->parent, rate);
1331 static int tegra_clk_shared_bus_enable(struct clk *c)
1333 unsigned long flags;
1336 spin_lock_irqsave(&c->parent->spinlock, flags);
1338 c->u.shared_bus_user.enabled = true;
1339 ret = tegra_clk_shared_bus_update(c->parent);
1341 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1346 static void tegra_clk_shared_bus_disable(struct clk *c)
1348 unsigned long flags;
1351 spin_lock_irqsave(&c->parent->spinlock, flags);
1353 c->u.shared_bus_user.enabled = false;
1354 ret = tegra_clk_shared_bus_update(c->parent);
1357 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1360 static struct clk_ops tegra_clk_shared_bus_ops = {
1361 .init = tegra_clk_shared_bus_init,
1362 .enable = tegra_clk_shared_bus_enable,
1363 .disable = tegra_clk_shared_bus_disable,
1364 .set_rate = tegra_clk_shared_bus_set_rate,
1365 .round_rate = tegra_clk_shared_bus_round_rate,
1369 /* Clock definitions */
1370 static struct clk tegra_clk_32k = {
1377 static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
1378 {32768, 12000000, 366, 1, 1, 0},
1379 {32768, 13000000, 397, 1, 1, 0},
1380 {32768, 19200000, 586, 1, 1, 0},
1381 {32768, 26000000, 793, 1, 1, 0},
1385 static struct clk tegra_pll_s = {
1387 .flags = PLL_ALT_MISC_REG,
1388 .ops = &tegra_pll_ops,
1389 .parent = &tegra_clk_32k,
1390 .max_rate = 26000000,
1395 .cf_min = 0, /* FIXME */
1396 .cf_max = 0, /* FIXME */
1397 .vco_min = 12000000,
1398 .vco_max = 26000000,
1399 .freq_table = tegra_pll_s_freq_table,
1404 static struct clk_mux_sel tegra_clk_m_sel[] = {
1405 { .input = &tegra_clk_32k, .value = 0},
1406 { .input = &tegra_pll_s, .value = 1},
1410 static struct clk tegra_clk_m = {
1412 .flags = ENABLE_ON_INIT,
1413 .ops = &tegra_clk_m_ops,
1414 .inputs = tegra_clk_m_sel,
1417 .max_rate = 26000000,
1420 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
1421 { 0, 0, 0, 0, 0, 0 },
1424 static struct clk tegra_pll_c = {
1426 .flags = PLL_HAS_CPCON,
1427 .ops = &tegra_pll_ops,
1429 .parent = &tegra_clk_m,
1430 .max_rate = 600000000,
1432 .input_min = 2000000,
1433 .input_max = 31000000,
1436 .vco_min = 20000000,
1437 .vco_max = 1400000000,
1438 .freq_table = tegra_pll_c_freq_table,
1443 static struct clk tegra_pll_c_out1 = {
1444 .name = "pll_c_out1",
1445 .ops = &tegra_pll_div_ops,
1447 .parent = &tegra_pll_c,
1450 .max_rate = 600000000,
1453 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
1454 { 12000000, 666000000, 666, 12, 1, 8},
1455 { 13000000, 666000000, 666, 13, 1, 8},
1456 { 19200000, 666000000, 555, 16, 1, 8},
1457 { 26000000, 666000000, 666, 26, 1, 8},
1458 { 12000000, 600000000, 600, 12, 1, 8},
1459 { 13000000, 600000000, 600, 13, 1, 8},
1460 { 19200000, 600000000, 375, 12, 1, 6},
1461 { 26000000, 600000000, 600, 26, 1, 8},
1462 { 0, 0, 0, 0, 0, 0 },
1465 static struct clk tegra_pll_m = {
1467 .flags = PLL_HAS_CPCON,
1468 .ops = &tegra_pll_ops,
1470 .parent = &tegra_clk_m,
1471 .max_rate = 800000000,
1473 .input_min = 2000000,
1474 .input_max = 31000000,
1477 .vco_min = 20000000,
1478 .vco_max = 1200000000,
1479 .freq_table = tegra_pll_m_freq_table,
1484 static struct clk tegra_pll_m_out1 = {
1485 .name = "pll_m_out1",
1486 .ops = &tegra_pll_div_ops,
1488 .parent = &tegra_pll_m,
1491 .max_rate = 600000000,
1494 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
1495 { 12000000, 216000000, 432, 12, 2, 8},
1496 { 13000000, 216000000, 432, 13, 2, 8},
1497 { 19200000, 216000000, 90, 4, 2, 1},
1498 { 26000000, 216000000, 432, 26, 2, 8},
1499 { 12000000, 432000000, 432, 12, 1, 8},
1500 { 13000000, 432000000, 432, 13, 1, 8},
1501 { 19200000, 432000000, 90, 4, 1, 1},
1502 { 26000000, 432000000, 432, 26, 1, 8},
1503 { 0, 0, 0, 0, 0, 0 },
1506 static struct clk tegra_pll_p = {
1508 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
1509 .ops = &tegra_pll_ops,
1511 .parent = &tegra_clk_m,
1512 .max_rate = 432000000,
1514 .input_min = 2000000,
1515 .input_max = 31000000,
1518 .vco_min = 20000000,
1519 .vco_max = 1400000000,
1520 .freq_table = tegra_pll_p_freq_table,
1525 static struct clk tegra_pll_p_out1 = {
1526 .name = "pll_p_out1",
1527 .ops = &tegra_pll_div_ops,
1528 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1529 .parent = &tegra_pll_p,
1532 .max_rate = 432000000,
1535 static struct clk tegra_pll_p_out2 = {
1536 .name = "pll_p_out2",
1537 .ops = &tegra_pll_div_ops,
1538 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1539 .parent = &tegra_pll_p,
1542 .max_rate = 432000000,
1545 static struct clk tegra_pll_p_out3 = {
1546 .name = "pll_p_out3",
1547 .ops = &tegra_pll_div_ops,
1548 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1549 .parent = &tegra_pll_p,
1552 .max_rate = 432000000,
1555 static struct clk tegra_pll_p_out4 = {
1556 .name = "pll_p_out4",
1557 .ops = &tegra_pll_div_ops,
1558 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1559 .parent = &tegra_pll_p,
1562 .max_rate = 432000000,
1565 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
1566 { 28800000, 56448000, 49, 25, 1, 1},
1567 { 28800000, 73728000, 64, 25, 1, 1},
1568 { 28800000, 24000000, 5, 6, 1, 1},
1569 { 0, 0, 0, 0, 0, 0 },
1572 static struct clk tegra_pll_a = {
1574 .flags = PLL_HAS_CPCON,
1575 .ops = &tegra_pll_ops,
1577 .parent = &tegra_pll_p_out1,
1578 .max_rate = 73728000,
1580 .input_min = 2000000,
1581 .input_max = 31000000,
1584 .vco_min = 20000000,
1585 .vco_max = 1400000000,
1586 .freq_table = tegra_pll_a_freq_table,
1591 static struct clk tegra_pll_a_out0 = {
1592 .name = "pll_a_out0",
1593 .ops = &tegra_pll_div_ops,
1595 .parent = &tegra_pll_a,
1598 .max_rate = 73728000,
1601 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
1602 { 12000000, 216000000, 216, 12, 1, 4},
1603 { 13000000, 216000000, 216, 13, 1, 4},
1604 { 19200000, 216000000, 135, 12, 1, 3},
1605 { 26000000, 216000000, 216, 26, 1, 4},
1607 { 12000000, 594000000, 594, 12, 1, 8},
1608 { 13000000, 594000000, 594, 13, 1, 8},
1609 { 19200000, 594000000, 495, 16, 1, 8},
1610 { 26000000, 594000000, 594, 26, 1, 8},
1612 { 12000000, 1000000000, 1000, 12, 1, 12},
1613 { 13000000, 1000000000, 1000, 13, 1, 12},
1614 { 19200000, 1000000000, 625, 12, 1, 8},
1615 { 26000000, 1000000000, 1000, 26, 1, 12},
1617 { 0, 0, 0, 0, 0, 0 },
1620 static struct clk tegra_pll_d = {
1622 .flags = PLL_HAS_CPCON | PLLD,
1623 .ops = &tegra_pll_ops,
1625 .parent = &tegra_clk_m,
1626 .max_rate = 1000000000,
1628 .input_min = 2000000,
1629 .input_max = 40000000,
1632 .vco_min = 40000000,
1633 .vco_max = 1000000000,
1634 .freq_table = tegra_pll_d_freq_table,
1639 static struct clk tegra_pll_d_out0 = {
1640 .name = "pll_d_out0",
1641 .ops = &tegra_pll_div_ops,
1642 .flags = DIV_2 | PLLD,
1643 .parent = &tegra_pll_d,
1644 .max_rate = 500000000,
1647 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
1648 { 12000000, 480000000, 960, 12, 2, 0},
1649 { 13000000, 480000000, 960, 13, 2, 0},
1650 { 19200000, 480000000, 200, 4, 2, 0},
1651 { 26000000, 480000000, 960, 26, 2, 0},
1652 { 0, 0, 0, 0, 0, 0 },
1655 static struct clk tegra_pll_u = {
1658 .ops = &tegra_pll_ops,
1660 .parent = &tegra_clk_m,
1661 .max_rate = 480000000,
1663 .input_min = 2000000,
1664 .input_max = 40000000,
1667 .vco_min = 480000000,
1668 .vco_max = 960000000,
1669 .freq_table = tegra_pll_u_freq_table,
1674 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
1676 { 12000000, 1000000000, 1000, 12, 1, 12},
1677 { 13000000, 1000000000, 1000, 13, 1, 12},
1678 { 19200000, 1000000000, 625, 12, 1, 8},
1679 { 26000000, 1000000000, 1000, 26, 1, 12},
1682 { 12000000, 912000000, 912, 12, 1, 12},
1683 { 13000000, 912000000, 912, 13, 1, 12},
1684 { 19200000, 912000000, 760, 16, 1, 8},
1685 { 26000000, 912000000, 912, 26, 1, 12},
1688 { 12000000, 816000000, 816, 12, 1, 12},
1689 { 13000000, 816000000, 816, 13, 1, 12},
1690 { 19200000, 816000000, 680, 16, 1, 8},
1691 { 26000000, 816000000, 816, 26, 1, 12},
1694 { 12000000, 760000000, 760, 12, 1, 12},
1695 { 13000000, 760000000, 760, 13, 1, 12},
1696 { 19200000, 760000000, 950, 24, 1, 8},
1697 { 26000000, 760000000, 760, 26, 1, 12},
1700 { 12000000, 608000000, 608, 12, 1, 12},
1701 { 13000000, 608000000, 608, 13, 1, 12},
1702 { 19200000, 608000000, 380, 12, 1, 8},
1703 { 26000000, 608000000, 608, 26, 1, 12},
1706 { 12000000, 456000000, 456, 12, 1, 12},
1707 { 13000000, 456000000, 456, 13, 1, 12},
1708 { 19200000, 456000000, 380, 16, 1, 8},
1709 { 26000000, 456000000, 456, 26, 1, 12},
1712 { 12000000, 312000000, 312, 12, 1, 12},
1713 { 13000000, 312000000, 312, 13, 1, 12},
1714 { 19200000, 312000000, 260, 16, 1, 8},
1715 { 26000000, 312000000, 312, 26, 1, 12},
1717 { 0, 0, 0, 0, 0, 0 },
1720 static struct clk tegra_pll_x = {
1722 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1723 .ops = &tegra_pllx_ops,
1725 .parent = &tegra_clk_m,
1726 .max_rate = 1000000000,
1728 .input_min = 2000000,
1729 .input_max = 31000000,
1732 .vco_min = 20000000,
1733 .vco_max = 1200000000,
1734 .freq_table = tegra_pll_x_freq_table,
1739 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
1740 { 12000000, 100000000, 200, 24, 1, 0 },
1741 { 0, 0, 0, 0, 0, 0 },
1744 static struct clk tegra_pll_e = {
1746 .flags = PLL_ALT_MISC_REG,
1747 .ops = &tegra_plle_ops,
1748 .parent = &tegra_clk_m,
1750 .max_rate = 100000000,
1752 .input_min = 12000000,
1753 .input_max = 12000000,
1754 .freq_table = tegra_pll_e_freq_table,
1758 static struct clk tegra_clk_d = {
1760 .flags = PERIPH_NO_RESET,
1761 .ops = &tegra_clk_double_ops,
1764 .parent = &tegra_clk_m,
1765 .max_rate = 52000000,
1771 /* dap_mclk1, belongs to the cdev1 pingroup. */
1772 static struct clk tegra_dev1_clk = {
1774 .ops = &tegra_cdev_clk_ops,
1776 .max_rate = 26000000,
1782 /* dap_mclk2, belongs to the cdev2 pingroup. */
1783 static struct clk tegra_dev2_clk = {
1785 .ops = &tegra_cdev_clk_ops,
1787 .max_rate = 26000000,
1793 /* initialized before peripheral clocks */
1794 static struct clk_mux_sel mux_audio_sync_clk[8+1];
1795 static const struct audio_sources {
1798 } mux_audio_sync_clk_sources[] = {
1799 { .name = "spdif_in", .value = 0 },
1800 { .name = "i2s1", .value = 1 },
1801 { .name = "i2s2", .value = 2 },
1802 { .name = "pll_a_out0", .value = 4 },
1803 #if 0 /* FIXME: not implemented */
1804 { .name = "ac97", .value = 3 },
1805 { .name = "ext_audio_clk2", .value = 5 },
1806 { .name = "ext_audio_clk1", .value = 6 },
1807 { .name = "ext_vimclk", .value = 7 },
1812 static struct clk tegra_clk_audio = {
1814 .inputs = mux_audio_sync_clk,
1816 .max_rate = 73728000,
1817 .ops = &tegra_audio_sync_clk_ops
1820 static struct clk tegra_clk_audio_2x = {
1822 .flags = PERIPH_NO_RESET,
1823 .max_rate = 48000000,
1824 .ops = &tegra_clk_double_ops,
1827 .parent = &tegra_clk_audio,
1833 struct clk_lookup tegra_audio_clk_lookups[] = {
1834 { .con_id = "audio", .clk = &tegra_clk_audio },
1835 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
1838 /* This is called after peripheral clocks are initialized, as the
1839 * audio_sync clock depends on some of the peripheral clocks.
1842 static void init_audio_sync_clock_mux(void)
1845 struct clk_mux_sel *sel = mux_audio_sync_clk;
1846 const struct audio_sources *src = mux_audio_sync_clk_sources;
1847 struct clk_lookup *lookup;
1849 for (i = 0; src->name; i++, sel++, src++) {
1850 sel->input = tegra_get_clock_by_name(src->name);
1852 pr_err("%s: could not find clk %s\n", __func__,
1854 sel->value = src->value;
1857 lookup = tegra_audio_clk_lookups;
1858 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
1859 clk_init(lookup->clk);
1864 static struct clk_mux_sel mux_cclk[] = {
1865 { .input = &tegra_clk_m, .value = 0},
1866 { .input = &tegra_pll_c, .value = 1},
1867 { .input = &tegra_clk_32k, .value = 2},
1868 { .input = &tegra_pll_m, .value = 3},
1869 { .input = &tegra_pll_p, .value = 4},
1870 { .input = &tegra_pll_p_out4, .value = 5},
1871 { .input = &tegra_pll_p_out3, .value = 6},
1872 { .input = &tegra_clk_d, .value = 7},
1873 { .input = &tegra_pll_x, .value = 8},
1877 static struct clk_mux_sel mux_sclk[] = {
1878 { .input = &tegra_clk_m, .value = 0},
1879 { .input = &tegra_pll_c_out1, .value = 1},
1880 { .input = &tegra_pll_p_out4, .value = 2},
1881 { .input = &tegra_pll_p_out3, .value = 3},
1882 { .input = &tegra_pll_p_out2, .value = 4},
1883 { .input = &tegra_clk_d, .value = 5},
1884 { .input = &tegra_clk_32k, .value = 6},
1885 { .input = &tegra_pll_m_out1, .value = 7},
1889 static struct clk tegra_clk_cclk = {
1893 .ops = &tegra_super_ops,
1894 .max_rate = 1000000000,
1897 static struct clk tegra_clk_sclk = {
1901 .ops = &tegra_super_ops,
1902 .max_rate = 240000000,
1903 .min_rate = 120000000,
1906 static struct clk tegra_clk_virtual_cpu = {
1908 .parent = &tegra_clk_cclk,
1909 .ops = &tegra_cpu_ops,
1910 .max_rate = 1000000000,
1912 .main = &tegra_pll_x,
1913 .backup = &tegra_pll_p,
1917 static struct clk tegra_clk_cop = {
1919 .parent = &tegra_clk_sclk,
1920 .ops = &tegra_cop_ops,
1921 .max_rate = 240000000,
1924 static struct clk tegra_clk_hclk = {
1927 .parent = &tegra_clk_sclk,
1930 .ops = &tegra_bus_ops,
1931 .max_rate = 240000000,
1934 static struct clk tegra_clk_pclk = {
1937 .parent = &tegra_clk_hclk,
1940 .ops = &tegra_bus_ops,
1941 .max_rate = 120000000,
1944 static struct clk tegra_clk_blink = {
1946 .parent = &tegra_clk_32k,
1948 .ops = &tegra_blink_clk_ops,
1952 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
1953 { .input = &tegra_pll_m, .value = 0},
1954 { .input = &tegra_pll_c, .value = 1},
1955 { .input = &tegra_pll_p, .value = 2},
1956 { .input = &tegra_pll_a_out0, .value = 3},
1960 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
1961 { .input = &tegra_pll_m, .value = 0},
1962 { .input = &tegra_pll_c, .value = 1},
1963 { .input = &tegra_pll_p, .value = 2},
1964 { .input = &tegra_clk_m, .value = 3},
1968 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
1969 { .input = &tegra_pll_p, .value = 0},
1970 { .input = &tegra_pll_c, .value = 1},
1971 { .input = &tegra_pll_m, .value = 2},
1972 { .input = &tegra_clk_m, .value = 3},
1976 static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
1977 {.input = &tegra_pll_a_out0, .value = 0},
1978 {.input = &tegra_clk_audio_2x, .value = 1},
1979 {.input = &tegra_pll_p, .value = 2},
1980 {.input = &tegra_clk_m, .value = 3},
1984 static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
1985 {.input = &tegra_pll_p, .value = 0},
1986 {.input = &tegra_pll_d_out0, .value = 1},
1987 {.input = &tegra_pll_c, .value = 2},
1988 {.input = &tegra_clk_m, .value = 3},
1992 static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
1993 {.input = &tegra_pll_p, .value = 0},
1994 {.input = &tegra_pll_c, .value = 1},
1995 {.input = &tegra_clk_audio, .value = 2},
1996 {.input = &tegra_clk_m, .value = 3},
1997 {.input = &tegra_clk_32k, .value = 4},
2001 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
2002 {.input = &tegra_pll_p, .value = 0},
2003 {.input = &tegra_pll_c, .value = 1},
2004 {.input = &tegra_pll_m, .value = 2},
2008 static struct clk_mux_sel mux_clk_m[] = {
2009 { .input = &tegra_clk_m, .value = 0},
2013 static struct clk_mux_sel mux_pllp_out3[] = {
2014 { .input = &tegra_pll_p_out3, .value = 0},
2018 static struct clk_mux_sel mux_plld[] = {
2019 { .input = &tegra_pll_d, .value = 0},
2023 static struct clk_mux_sel mux_clk_32k[] = {
2024 { .input = &tegra_clk_32k, .value = 0},
2028 static struct clk_mux_sel mux_pclk[] = {
2029 { .input = &tegra_clk_pclk, .value = 0},
2033 static struct clk tegra_clk_emc = {
2035 .ops = &tegra_emc_clk_ops,
2037 .max_rate = 800000000,
2038 .inputs = mux_pllm_pllc_pllp_clkm,
2039 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
2045 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
2052 .ops = &tegra_periph_clk_ops, \
2054 .inputs = _inputs, \
2058 .clk_num = _clk_num, \
2062 #define SHARED_CLK(_name, _dev, _con, _parent) \
2069 .ops = &tegra_clk_shared_bus_ops, \
2070 .parent = _parent, \
2073 struct clk tegra_list_clks[] = {
2074 PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 108000000, mux_pclk, 0),
2075 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
2076 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
2077 PERIPH_CLK("i2s1", "i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2078 PERIPH_CLK("i2s2", "i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2079 /* FIXME: spdif has 2 clocks but 1 enable */
2080 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2081 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
2082 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71),
2083 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2084 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2085 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2086 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2087 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2088 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2089 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2090 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2091 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2092 /* FIXME: vfir shares an enable with uartb */
2093 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2094 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2095 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2096 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2097 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2098 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
2099 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
2100 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
2101 PERIPH_CLK("vde", "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
2102 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
2103 /* FIXME: what is la? */
2104 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2105 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2106 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2107 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2108 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2109 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2110 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2111 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2112 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2113 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2114 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2115 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2116 PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2117 PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2118 PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2119 PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2120 PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2121 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
2122 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2123 /* FIXME: vi and vi_sensor share an enable */
2124 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2125 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
2126 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2127 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2128 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2129 /* FIXME: cve and tvo share an enable */
2130 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2131 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2132 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2133 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2134 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
2135 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
2136 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2137 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2138 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2139 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
2140 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0),
2141 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
2142 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
2143 PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2144 PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2145 PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2147 SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sclk),
2148 SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc),
2149 SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc),
2150 SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc),
2151 SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc),
2152 SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc),
2153 SHARED_CLK("host.emc", "tegra_grhost", "emc", &tegra_clk_emc),
2154 SHARED_CLK("usbd.emc", "fsl-tegra-udc", "emc", &tegra_clk_emc),
2155 SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc),
2156 SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc),
2157 SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc),
2160 #define CLK_DUPLICATE(_name, _dev, _con) \
2169 /* Some clocks may be used by different drivers depending on the board
2170 * configuration. List those here to register them twice in the clock lookup
2171 * table under two names.
2173 struct clk_duplicate tegra_clk_duplicates[] = {
2174 CLK_DUPLICATE("uarta", "tegra_uart.0", NULL),
2175 CLK_DUPLICATE("uartb", "tegra_uart.1", NULL),
2176 CLK_DUPLICATE("uartc", "tegra_uart.2", NULL),
2177 CLK_DUPLICATE("uartd", "tegra_uart.3", NULL),
2178 CLK_DUPLICATE("uarte", "tegra_uart.4", NULL),
2179 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2180 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2181 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2182 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2183 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2184 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
2185 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
2186 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
2187 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
2188 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
2189 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
2190 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
2191 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
2192 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
2193 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
2194 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
2197 #define CLK(dev, con, ck) \
2204 struct clk *tegra_ptr_clks[] = {
2231 &tegra_clk_virtual_cpu,
2237 static void tegra2_init_one_clock(struct clk *c)
2240 INIT_LIST_HEAD(&c->shared_bus_list);
2241 if (!c->lookup.dev_id && !c->lookup.con_id)
2242 c->lookup.con_id = c->name;
2244 clkdev_add(&c->lookup);
2247 void __init tegra2_init_clocks(void)
2252 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
2253 tegra2_init_one_clock(tegra_ptr_clks[i]);
2255 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
2256 tegra2_init_one_clock(&tegra_list_clks[i]);
2258 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
2259 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
2261 pr_err("%s: Unknown duplicate clock %s\n", __func__,
2262 tegra_clk_duplicates[i].name);
2266 tegra_clk_duplicates[i].lookup.clk = c;
2267 clkdev_add(&tegra_clk_duplicates[i].lookup);
2270 init_audio_sync_clock_mux();
2274 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
2275 PERIPH_CLK_SOURCE_NUM + 22];
2277 void tegra_clk_suspend(void)
2279 unsigned long off, i;
2280 u32 *ctx = clk_rst_suspend;
2282 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
2283 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
2284 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2285 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
2286 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2287 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE);
2288 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2289 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
2290 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2291 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE);
2292 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2294 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
2295 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
2296 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
2298 *ctx++ = clk_readl(tegra_clk_cclk.reg);
2299 *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2301 *ctx++ = clk_readl(tegra_clk_sclk.reg);
2302 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2303 *ctx++ = clk_readl(tegra_clk_pclk.reg);
2305 *ctx++ = clk_readl(tegra_clk_audio.reg);
2307 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2309 if (off == PERIPH_CLK_SOURCE_EMC)
2311 *ctx++ = clk_readl(off);
2315 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2316 *ctx++ = clk_readl(off);
2319 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2320 *ctx++ = clk_readl(off);
2322 *ctx++ = clk_readl(MISC_CLK_ENB);
2323 *ctx++ = clk_readl(CLK_MASK_ARM);
2325 BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend));
2328 void tegra_clk_resume(void)
2330 unsigned long off, i;
2331 const u32 *ctx = clk_rst_suspend;
2334 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
2336 clk_writel(val, OSC_CTRL);
2338 clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
2339 clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2340 clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
2341 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2342 clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE);
2343 clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2344 clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE);
2345 clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2346 clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE);
2347 clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2350 clk_writel(*ctx++, tegra_pll_m_out1.reg);
2351 clk_writel(*ctx++, tegra_pll_a_out0.reg);
2352 clk_writel(*ctx++, tegra_pll_c_out1.reg);
2354 clk_writel(*ctx++, tegra_clk_cclk.reg);
2355 clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2357 clk_writel(*ctx++, tegra_clk_sclk.reg);
2358 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2359 clk_writel(*ctx++, tegra_clk_pclk.reg);
2361 clk_writel(*ctx++, tegra_clk_audio.reg);
2363 /* enable all clocks before configuring clock sources */
2364 clk_writel(0xbffffff9ul, CLK_OUT_ENB);
2365 clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
2366 clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
2369 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2371 if (off == PERIPH_CLK_SOURCE_EMC)
2373 clk_writel(*ctx++, off);
2378 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2379 clk_writel(*ctx++, off);
2383 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2384 clk_writel(*ctx++, off);
2387 clk_writel(*ctx++, MISC_CLK_ENB);
2388 clk_writel(*ctx++, CLK_MASK_ARM);