2 * Copyright (C) 2011 Google, Inc.
5 * Colin Cross <ccross@android.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/kernel.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
22 #include <linux/module.h>
24 #include <mach/iomap.h>
26 #include "tegra2_emc.h"
28 #ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE
29 static bool emc_enable = true;
31 static bool emc_enable;
33 module_param(emc_enable, bool, 0644);
35 static void __iomem *emc = IO_ADDRESS(TEGRA_EMC_BASE);
36 static const struct tegra_emc_table *tegra_emc_table;
37 static int tegra_emc_table_size;
39 static inline void emc_writel(u32 val, unsigned long addr)
41 writel(val, emc + addr);
44 static inline u32 emc_readl(unsigned long addr)
46 return readl(emc + addr);
49 static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
68 0x74, /* BURST_REFRESH_NUM */
79 0xa0, /* TCLKSTABLE */
82 0xac, /* QUSE_EXTRA */
83 0x114, /* FBIO_CFG6 */
86 0x104, /* FBIO_CFG5 */
87 0x2bc, /* CFG_DIG_DLL */
88 0x2c0, /* DLL_XFORM_DQS */
89 0x2c4, /* DLL_XFORM_QUSE */
90 0x2e0, /* ZCAL_REF_CNT */
91 0x2e4, /* ZCAL_WAIT_CNT */
92 0x2a8, /* AUTO_CAL_INTERVAL */
93 0x2d0, /* CFG_CLKTRIM_0 */
94 0x2d4, /* CFG_CLKTRIM_1 */
95 0x2d8, /* CFG_CLKTRIM_2 */
98 /* Select the closest EMC rate that is higher than the requested rate */
99 long tegra_emc_round_rate(unsigned long rate)
103 unsigned long distance = ULONG_MAX;
105 if (!tegra_emc_table)
111 pr_debug("%s: %lu\n", __func__, rate);
114 * The EMC clock rate is twice the bus rate, and the bus rate is
117 rate = rate / 2 / 1000;
119 for (i = 0; i < tegra_emc_table_size; i++) {
120 if (tegra_emc_table[i].rate >= rate &&
121 (tegra_emc_table[i].rate - rate) < distance) {
122 distance = tegra_emc_table[i].rate - rate;
130 pr_debug("%s: using %lu\n", __func__, tegra_emc_table[best].rate);
132 return tegra_emc_table[best].rate * 2 * 1000;
136 * The EMC registers have shadow registers. When the EMC clock is updated
137 * in the clock controller, the shadow registers are copied to the active
138 * registers, allowing glitchless memory bus frequency changes.
139 * This function updates the shadow registers for a new clock frequency,
140 * and relies on the clock lock on the emc clock to avoid races between
141 * multiple frequency changes
143 int tegra_emc_set_rate(unsigned long rate)
148 if (!tegra_emc_table)
152 * The EMC clock rate is twice the bus rate, and the bus rate is
155 rate = rate / 2 / 1000;
157 for (i = 0; i < tegra_emc_table_size; i++)
158 if (tegra_emc_table[i].rate == rate)
161 if (i >= tegra_emc_table_size)
164 pr_debug("%s: setting to %lu\n", __func__, rate);
166 for (j = 0; j < TEGRA_EMC_NUM_REGS; j++)
167 emc_writel(tegra_emc_table[i].regs[j], emc_reg_addr[j]);
169 emc_readl(tegra_emc_table[i].regs[TEGRA_EMC_NUM_REGS - 1]);
174 void tegra_init_emc(const struct tegra_emc_table *table, int table_size)
176 tegra_emc_table = table;
177 tegra_emc_table_size = table_size;