2 * arch/arm/mach-tegra/tegra30_clocks.c
4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/list.h>
24 #include <linux/spinlock.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
28 #include <linux/clk.h>
29 #include <linux/cpufreq.h>
30 #include <linux/syscore_ops.h>
32 #include <asm/clkdev.h>
37 #include "tegra_cpu_car.h"
39 #define USE_PLL_LOCK_BITS 0
41 #define RST_DEVICES_L 0x004
42 #define RST_DEVICES_H 0x008
43 #define RST_DEVICES_U 0x00C
44 #define RST_DEVICES_V 0x358
45 #define RST_DEVICES_W 0x35C
46 #define RST_DEVICES_SET_L 0x300
47 #define RST_DEVICES_CLR_L 0x304
48 #define RST_DEVICES_SET_V 0x430
49 #define RST_DEVICES_CLR_V 0x434
50 #define RST_DEVICES_NUM 5
52 #define CLK_OUT_ENB_L 0x010
53 #define CLK_OUT_ENB_H 0x014
54 #define CLK_OUT_ENB_U 0x018
55 #define CLK_OUT_ENB_V 0x360
56 #define CLK_OUT_ENB_W 0x364
57 #define CLK_OUT_ENB_SET_L 0x320
58 #define CLK_OUT_ENB_CLR_L 0x324
59 #define CLK_OUT_ENB_SET_V 0x440
60 #define CLK_OUT_ENB_CLR_V 0x444
61 #define CLK_OUT_ENB_NUM 5
63 #define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1)
64 #define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1)
66 #define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32))
67 #define PERIPH_CLK_TO_RST_REG(c) \
68 periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4)
69 #define PERIPH_CLK_TO_RST_SET_REG(c) \
70 periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8)
71 #define PERIPH_CLK_TO_RST_CLR_REG(c) \
72 periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8)
74 #define PERIPH_CLK_TO_ENB_REG(c) \
75 periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4)
76 #define PERIPH_CLK_TO_ENB_SET_REG(c) \
77 periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8)
78 #define PERIPH_CLK_TO_ENB_CLR_REG(c) \
79 periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8)
81 #define CLK_MASK_ARM 0x44
82 #define MISC_CLK_ENB 0x48
85 #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
86 #define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28)
87 #define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28)
88 #define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28)
89 #define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28)
90 #define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28)
91 #define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28)
92 #define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28)
93 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
95 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
96 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
97 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
98 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
100 #define OSC_FREQ_DET 0x58
101 #define OSC_FREQ_DET_TRIG (1<<31)
103 #define OSC_FREQ_DET_STATUS 0x5C
104 #define OSC_FREQ_DET_BUSY (1<<31)
105 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
107 #define PERIPH_CLK_SOURCE_I2S1 0x100
108 #define PERIPH_CLK_SOURCE_EMC 0x19c
109 #define PERIPH_CLK_SOURCE_OSC 0x1fc
110 #define PERIPH_CLK_SOURCE_NUM1 \
111 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
113 #define PERIPH_CLK_SOURCE_G3D2 0x3b0
114 #define PERIPH_CLK_SOURCE_SE 0x42c
115 #define PERIPH_CLK_SOURCE_NUM2 \
116 ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1)
118 #define AUDIO_DLY_CLK 0x49c
119 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
120 #define PERIPH_CLK_SOURCE_NUM3 \
121 ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
123 #define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \
124 PERIPH_CLK_SOURCE_NUM2 + \
125 PERIPH_CLK_SOURCE_NUM3)
127 #define CPU_SOFTRST_CTRL 0x380
129 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
130 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
131 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
132 #define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8
133 #define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50
134 #define PERIPH_CLK_UART_DIV_ENB (1<<24)
135 #define PERIPH_CLK_VI_SEL_EX_SHIFT 24
136 #define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)
137 #define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8)
138 #define PERIPH_CLK_DTV_POLARITY_INV (1<<25)
140 #define AUDIO_SYNC_SOURCE_MASK 0x0F
141 #define AUDIO_SYNC_DISABLE_BIT 0x10
142 #define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4)
145 #define PLL_BASE_BYPASS (1<<31)
146 #define PLL_BASE_ENABLE (1<<30)
147 #define PLL_BASE_REF_ENABLE (1<<29)
148 #define PLL_BASE_OVERRIDE (1<<28)
149 #define PLL_BASE_LOCK (1<<27)
150 #define PLL_BASE_DIVP_MASK (0x7<<20)
151 #define PLL_BASE_DIVP_SHIFT 20
152 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
153 #define PLL_BASE_DIVN_SHIFT 8
154 #define PLL_BASE_DIVM_MASK (0x1F)
155 #define PLL_BASE_DIVM_SHIFT 0
157 #define PLL_OUT_RATIO_MASK (0xFF<<8)
158 #define PLL_OUT_RATIO_SHIFT 8
159 #define PLL_OUT_OVERRIDE (1<<2)
160 #define PLL_OUT_CLKEN (1<<1)
161 #define PLL_OUT_RESET_DISABLE (1<<0)
163 #define PLL_MISC(c) \
164 (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
165 #define PLL_MISC_LOCK_ENABLE(c) \
166 (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))
168 #define PLL_MISC_DCCON_SHIFT 20
169 #define PLL_MISC_CPCON_SHIFT 8
170 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
171 #define PLL_MISC_LFCON_SHIFT 4
172 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
173 #define PLL_MISC_VCOCON_SHIFT 0
174 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
175 #define PLLD_MISC_CLKENABLE (1<<30)
177 #define PLLU_BASE_POST_DIV (1<<20)
179 #define PLLD_BASE_DSIB_MUX_SHIFT 25
180 #define PLLD_BASE_DSIB_MUX_MASK (1<<PLLD_BASE_DSIB_MUX_SHIFT)
181 #define PLLD_BASE_CSI_CLKENABLE (1<<26)
182 #define PLLD_MISC_DSI_CLKENABLE (1<<30)
183 #define PLLD_MISC_DIV_RST (1<<23)
184 #define PLLD_MISC_DCCON_SHIFT 12
186 #define PLLDU_LFCON_SET_DIVN 600
188 /* FIXME: OUT_OF_TABLE_CPCON per pll */
189 #define OUT_OF_TABLE_CPCON 0x8
191 #define SUPER_CLK_MUX 0x00
192 #define SUPER_STATE_SHIFT 28
193 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
194 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
195 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
196 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
197 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
198 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
199 #define SUPER_LP_DIV2_BYPASS (0x1 << 16)
200 #define SUPER_SOURCE_MASK 0xF
201 #define SUPER_FIQ_SOURCE_SHIFT 12
202 #define SUPER_IRQ_SOURCE_SHIFT 8
203 #define SUPER_RUN_SOURCE_SHIFT 4
204 #define SUPER_IDLE_SOURCE_SHIFT 0
206 #define SUPER_CLK_DIVIDER 0x04
207 #define SUPER_CLOCK_DIV_U71_SHIFT 16
208 #define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT)
209 /* guarantees safe cpu backup */
210 #define SUPER_CLOCK_DIV_U71_MIN 0x2
212 #define BUS_CLK_DISABLE (1<<3)
213 #define BUS_CLK_DIV_MASK 0x3
216 #define PMC_CTRL_BLINK_ENB (1 << 7)
218 #define PMC_DPD_PADS_ORIDE 0x1c
219 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
221 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
222 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
223 #define PMC_BLINK_TIMER_ENB (1 << 15)
224 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
225 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
227 #define PMC_PLLP_WB0_OVERRIDE 0xf8
228 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12)
230 #define UTMIP_PLL_CFG2 0x488
231 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
232 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
233 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
234 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
235 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
237 #define UTMIP_PLL_CFG1 0x484
238 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
239 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
240 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
241 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
242 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
244 #define PLLE_BASE_CML_ENABLE (1<<31)
245 #define PLLE_BASE_ENABLE (1<<30)
246 #define PLLE_BASE_DIVCML_SHIFT 24
247 #define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT)
248 #define PLLE_BASE_DIVP_SHIFT 16
249 #define PLLE_BASE_DIVP_MASK (0x3f<<PLLE_BASE_DIVP_SHIFT)
250 #define PLLE_BASE_DIVN_SHIFT 8
251 #define PLLE_BASE_DIVN_MASK (0xFF<<PLLE_BASE_DIVN_SHIFT)
252 #define PLLE_BASE_DIVM_SHIFT 0
253 #define PLLE_BASE_DIVM_MASK (0xFF<<PLLE_BASE_DIVM_SHIFT)
254 #define PLLE_BASE_DIV_MASK \
255 (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \
256 PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK)
257 #define PLLE_BASE_DIV(m, n, p, cml) \
258 (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \
259 ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT))
261 #define PLLE_MISC_SETUP_BASE_SHIFT 16
262 #define PLLE_MISC_SETUP_BASE_MASK (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT)
263 #define PLLE_MISC_READY (1<<15)
264 #define PLLE_MISC_LOCK (1<<11)
265 #define PLLE_MISC_LOCK_ENABLE (1<<9)
266 #define PLLE_MISC_SETUP_EX_SHIFT 2
267 #define PLLE_MISC_SETUP_EX_MASK (0x3<<PLLE_MISC_SETUP_EX_SHIFT)
268 #define PLLE_MISC_SETUP_MASK \
269 (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK)
270 #define PLLE_MISC_SETUP_VALUE \
271 ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT))
273 #define PLLE_SS_CTRL 0x68
274 #define PLLE_SS_INCINTRV_SHIFT 24
275 #define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)
276 #define PLLE_SS_INC_SHIFT 16
277 #define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)
278 #define PLLE_SS_MAX_SHIFT 0
279 #define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT)
280 #define PLLE_SS_COEFFICIENTS_MASK \
281 (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
282 #define PLLE_SS_COEFFICIENTS_12MHZ \
283 ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
284 (0x24<<PLLE_SS_MAX_SHIFT))
285 #define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10))
287 #define PLLE_AUX 0x48c
288 #define PLLE_AUX_PLLP_SEL (1<<2)
289 #define PLLE_AUX_CML_SATA_ENABLE (1<<1)
290 #define PLLE_AUX_CML_PCIE_ENABLE (1<<0)
292 #define PMC_SATA_PWRGT 0x1ac
293 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE (1<<5)
294 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1<<4)
296 #define ROUND_DIVIDER_UP 0
297 #define ROUND_DIVIDER_DOWN 1
299 /* FIXME: recommended safety delay after lock is detected */
300 #define PLL_POST_LOCK_DELAY 100
302 /* Tegra CPU clock and reset control regs */
303 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
304 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
305 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
306 #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
307 #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
309 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
310 #define CPU_RESET(cpu) (0x1111ul << (cpu))
313 * Structure defining the fields for USB UTMI clocks Parameters.
315 struct utmi_clk_param {
316 /* Oscillator Frequency in KHz */
318 /* UTMIP PLL Enable Delay Count */
319 u8 enable_delay_count;
320 /* UTMIP PLL Stable count */
322 /* UTMIP PLL Active delay count */
323 u8 active_delay_count;
324 /* UTMIP PLL Xtal frequency count */
328 static const struct utmi_clk_param utmi_parameters[] = {
330 .osc_frequency = 13000000,
331 .enable_delay_count = 0x02,
332 .stable_count = 0x33,
333 .active_delay_count = 0x05,
334 .xtal_freq_count = 0x7F
337 .osc_frequency = 19200000,
338 .enable_delay_count = 0x03,
339 .stable_count = 0x4B,
340 .active_delay_count = 0x06,
341 .xtal_freq_count = 0xBB},
343 .osc_frequency = 12000000,
344 .enable_delay_count = 0x02,
345 .stable_count = 0x2F,
346 .active_delay_count = 0x04,
347 .xtal_freq_count = 0x76
350 .osc_frequency = 26000000,
351 .enable_delay_count = 0x04,
352 .stable_count = 0x66,
353 .active_delay_count = 0x09,
354 .xtal_freq_count = 0xFE
357 .osc_frequency = 16800000,
358 .enable_delay_count = 0x03,
359 .stable_count = 0x41,
360 .active_delay_count = 0x0A,
361 .xtal_freq_count = 0xA4
365 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
366 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
367 static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
369 #define MISC_GP_HIDREV 0x804
372 * Some peripheral clocks share an enable bit, so refcount the enable bits
373 * in registers CLK_ENABLE_L, ... CLK_ENABLE_W
375 static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
377 #define clk_writel(value, reg) \
378 __raw_writel(value, reg_clk_base + (reg))
379 #define clk_readl(reg) \
380 __raw_readl(reg_clk_base + (reg))
381 #define pmc_writel(value, reg) \
382 __raw_writel(value, reg_pmc_base + (reg))
383 #define pmc_readl(reg) \
384 __raw_readl(reg_pmc_base + (reg))
385 #define chipid_readl() \
386 __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV)
388 #define clk_writel_delay(value, reg) \
390 __raw_writel((value), reg_clk_base + (reg)); \
394 static inline int clk_set_div(struct clk_tegra *c, u32 n)
396 struct clk *clk = c->hw.clk;
398 return clk_set_rate(clk,
399 (__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n);
402 static inline u32 periph_clk_to_reg(
403 struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs)
405 u32 reg = c->u.periph.clk_num / 32;
406 BUG_ON(reg >= RST_DEVICES_NUM);
408 reg = reg_L + (reg * offs);
410 reg = reg_V + ((reg - 3) * offs);
414 static unsigned long clk_measure_input_freq(void)
416 u32 clock_autodetect;
417 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
418 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
419 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
420 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
422 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
424 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
426 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
428 } else if (clock_autodetect >= 1025 - 3 && clock_autodetect <= 1025 + 3) {
430 } else if (clock_autodetect >= 2344 - 3 && clock_autodetect <= 2344 + 3) {
432 } else if (clock_autodetect >= 2928 - 3 && clock_autodetect <= 2928 + 3) {
435 pr_err("%s: Unexpected clock autodetect value %d", __func__,
442 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate,
443 u32 flags, u32 round_mode)
445 s64 divider_u71 = parent_rate;
449 if (!(flags & DIV_U71_INT))
451 if (round_mode == ROUND_DIVIDER_UP)
452 divider_u71 += rate - 1;
453 do_div(divider_u71, rate);
454 if (flags & DIV_U71_INT)
457 if (divider_u71 - 2 < 0)
460 if (divider_u71 - 2 > 255)
463 return divider_u71 - 2;
466 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
470 divider_u16 = parent_rate;
473 divider_u16 += rate - 1;
474 do_div(divider_u16, rate);
476 if (divider_u16 - 1 < 0)
479 if (divider_u16 - 1 > 0xFFFF)
482 return divider_u16 - 1;
485 static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
486 unsigned long parent_rate)
488 return to_clk_tegra(hw)->fixed_rate;
491 struct clk_ops tegra30_clk_32k_ops = {
492 .recalc_rate = tegra30_clk_fixed_recalc_rate,
495 /* clk_m functions */
496 static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw,
497 unsigned long parent_rate)
499 if (!to_clk_tegra(hw)->fixed_rate)
500 to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
501 return to_clk_tegra(hw)->fixed_rate;
504 static void tegra30_clk_m_init(struct clk_hw *hw)
506 u32 osc_ctrl = clk_readl(OSC_CTRL);
507 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
508 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
510 switch (to_clk_tegra(hw)->fixed_rate) {
512 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
513 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
516 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
517 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
520 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
521 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
524 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
525 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
528 auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ;
529 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
532 auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ;
533 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
536 auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ;
537 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
540 pr_err("%s: Unexpected clock rate %ld", __func__,
541 to_clk_tegra(hw)->fixed_rate);
544 clk_writel(auto_clock_control, OSC_CTRL);
547 struct clk_ops tegra30_clk_m_ops = {
548 .init = tegra30_clk_m_init,
549 .recalc_rate = tegra30_clk_m_recalc_rate,
552 static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw,
553 unsigned long parent_rate)
555 struct clk_tegra *c = to_clk_tegra(hw);
556 u64 rate = parent_rate;
558 if (c->mul != 0 && c->div != 0) {
560 rate += c->div - 1; /* round up */
561 do_div(rate, c->div);
567 struct clk_ops tegra_clk_m_div_ops = {
568 .recalc_rate = tegra30_clk_m_div_recalc_rate,
571 /* PLL reference divider functions */
572 static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw,
573 unsigned long parent_rate)
575 struct clk_tegra *c = to_clk_tegra(hw);
576 unsigned long rate = parent_rate;
577 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
579 switch (pll_ref_div) {
580 case OSC_CTRL_PLL_REF_DIV_1:
583 case OSC_CTRL_PLL_REF_DIV_2:
586 case OSC_CTRL_PLL_REF_DIV_4:
590 pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div);
595 if (c->mul != 0 && c->div != 0) {
597 rate += c->div - 1; /* round up */
598 do_div(rate, c->div);
604 struct clk_ops tegra_pll_ref_ops = {
605 .recalc_rate = tegra30_pll_ref_recalc_rate,
608 /* super clock functions */
609 /* "super clocks" on tegra30 have two-stage muxes, fractional 7.1 divider and
610 * clock skipping super divider. We will ignore the clock skipping divider,
611 * since we can't lower the voltage when using the clock skip, but we can if
612 * we lower the PLL frequency. We will use 7.1 divider for CPU super-clock
613 * only when its parent is a fixed rate PLL, since we can't change PLL rate
616 static void tegra30_super_clk_init(struct clk_hw *hw)
618 struct clk_tegra *c = to_clk_tegra(hw);
619 struct clk_tegra *p =
620 to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk)));
623 if (c->flags & DIV_U71) {
624 /* Init safe 7.1 divider value (does not affect PLLX path) */
625 clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
626 c->reg + SUPER_CLK_DIVIDER);
629 if (!(p->flags & PLLX))
630 c->div += SUPER_CLOCK_DIV_U71_MIN;
632 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
635 static u8 tegra30_super_clk_get_parent(struct clk_hw *hw)
637 struct clk_tegra *c = to_clk_tegra(hw);
642 val = clk_readl(c->reg + SUPER_CLK_MUX);
643 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
644 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
645 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
646 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
647 source = (val >> shift) & SUPER_SOURCE_MASK;
648 if (c->flags & DIV_2)
649 source |= val & SUPER_LP_DIV2_BYPASS;
654 static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index)
656 struct clk_tegra *c = to_clk_tegra(hw);
657 struct clk_tegra *p =
658 to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk)));
662 val = clk_readl(c->reg + SUPER_CLK_MUX);
663 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
664 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
665 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
666 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
668 /* For LP mode super-clock switch between PLLX direct
669 and divided-by-2 outputs is allowed only when other
670 than PLLX clock source is current parent */
671 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
672 ((index ^ val) & SUPER_LP_DIV2_BYPASS)) {
675 val ^= SUPER_LP_DIV2_BYPASS;
676 clk_writel_delay(val, c->reg);
678 val &= ~(SUPER_SOURCE_MASK << shift);
679 val |= (index & SUPER_SOURCE_MASK) << shift;
681 /* 7.1 divider for CPU super-clock does not affect
683 if (c->flags & DIV_U71) {
685 if (!(p->flags & PLLX)) {
686 div = clk_readl(c->reg +
688 div &= SUPER_CLOCK_DIV_U71_MASK;
689 div >>= SUPER_CLOCK_DIV_U71_SHIFT;
694 clk_writel_delay(val, c->reg);
700 * Do not use super clocks "skippers", since dividing using a clock skipper
701 * does not allow the voltage to be scaled down. Instead adjust the rate of
702 * the parent clock. This requires that the parent of a super clock have no
703 * other children, otherwise the rate will change underneath the other
704 * children. Special case: if fixed rate PLL is CPU super clock parent the
705 * rate of this PLL can't be changed, and it has many other children. In
706 * this case use 7.1 fractional divider to adjust the super clock rate.
708 static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
709 unsigned long parent_rate)
711 struct clk_tegra *c = to_clk_tegra(hw);
712 struct clk *parent = __clk_get_parent(hw->clk);
713 struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
715 if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
716 int div = clk_div71_get_divider(parent_rate,
717 rate, c->flags, ROUND_DIVIDER_DOWN);
718 div = max(div, SUPER_CLOCK_DIV_U71_MIN);
720 clk_writel(div << SUPER_CLOCK_DIV_U71_SHIFT,
721 c->reg + SUPER_CLK_DIVIDER);
729 static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw,
730 unsigned long parent_rate)
732 struct clk_tegra *c = to_clk_tegra(hw);
733 u64 rate = parent_rate;
735 if (c->mul != 0 && c->div != 0) {
737 rate += c->div - 1; /* round up */
738 do_div(rate, c->div);
744 static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
745 unsigned long *prate)
747 struct clk_tegra *c = to_clk_tegra(hw);
748 struct clk *parent = __clk_get_parent(hw->clk);
749 struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
753 if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
754 div = clk_div71_get_divider(*prate,
755 rate, c->flags, ROUND_DIVIDER_DOWN);
756 div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2;
758 rate += div - 1; /* round up */
759 do_div(rate, c->div);
766 struct clk_ops tegra30_super_ops = {
767 .init = tegra30_super_clk_init,
768 .set_parent = tegra30_super_clk_set_parent,
769 .get_parent = tegra30_super_clk_get_parent,
770 .recalc_rate = tegra30_super_clk_recalc_rate,
771 .round_rate = tegra30_super_clk_round_rate,
772 .set_rate = tegra30_super_clk_set_rate,
775 static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw,
776 unsigned long parent_rate)
778 struct clk_tegra *c = to_clk_tegra(hw);
779 u64 rate = parent_rate;
781 if (c->mul != 0 && c->div != 0) {
783 rate += c->div - 1; /* round up */
784 do_div(rate, c->div);
790 struct clk_ops tegra30_twd_ops = {
791 .recalc_rate = tegra30_twd_clk_recalc_rate,
794 /* bus clock functions */
795 static int tegra30_bus_clk_is_enabled(struct clk_hw *hw)
797 struct clk_tegra *c = to_clk_tegra(hw);
798 u32 val = clk_readl(c->reg);
800 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
804 static int tegra30_bus_clk_enable(struct clk_hw *hw)
806 struct clk_tegra *c = to_clk_tegra(hw);
809 val = clk_readl(c->reg);
810 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
811 clk_writel(val, c->reg);
816 static void tegra30_bus_clk_disable(struct clk_hw *hw)
818 struct clk_tegra *c = to_clk_tegra(hw);
821 val = clk_readl(c->reg);
822 val |= BUS_CLK_DISABLE << c->reg_shift;
823 clk_writel(val, c->reg);
826 static unsigned long tegra30_bus_clk_recalc_rate(struct clk_hw *hw,
829 struct clk_tegra *c = to_clk_tegra(hw);
830 u32 val = clk_readl(c->reg);
833 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
836 if (c->mul != 0 && c->div != 0) {
838 rate += c->div - 1; /* round up */
839 do_div(rate, c->div);
844 static int tegra30_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
845 unsigned long parent_rate)
847 struct clk_tegra *c = to_clk_tegra(hw);
852 val = clk_readl(c->reg);
853 for (i = 1; i <= 4; i++) {
854 if (rate == parent_rate / i) {
855 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
856 val |= (i - 1) << c->reg_shift;
857 clk_writel(val, c->reg);
868 static long tegra30_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
869 unsigned long *prate)
871 unsigned long parent_rate = *prate;
874 if (rate >= parent_rate)
877 divider = parent_rate;
879 do_div(divider, rate);
886 do_div(parent_rate, divider);
891 struct clk_ops tegra30_bus_ops = {
892 .is_enabled = tegra30_bus_clk_is_enabled,
893 .enable = tegra30_bus_clk_enable,
894 .disable = tegra30_bus_clk_disable,
895 .set_rate = tegra30_bus_clk_set_rate,
896 .round_rate = tegra30_bus_clk_round_rate,
897 .recalc_rate = tegra30_bus_clk_recalc_rate,
900 /* Blink output functions */
901 static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
903 struct clk_tegra *c = to_clk_tegra(hw);
906 val = pmc_readl(PMC_CTRL);
907 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
911 static int tegra30_blink_clk_enable(struct clk_hw *hw)
915 val = pmc_readl(PMC_DPD_PADS_ORIDE);
916 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
918 val = pmc_readl(PMC_CTRL);
919 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
924 static void tegra30_blink_clk_disable(struct clk_hw *hw)
928 val = pmc_readl(PMC_CTRL);
929 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
931 val = pmc_readl(PMC_DPD_PADS_ORIDE);
932 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
935 static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
936 unsigned long parent_rate)
938 struct clk_tegra *c = to_clk_tegra(hw);
940 if (rate >= parent_rate) {
942 pmc_writel(0, c->reg);
947 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
950 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
951 PMC_BLINK_TIMER_DATA_ON_SHIFT;
952 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
953 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
955 val |= PMC_BLINK_TIMER_ENB;
956 pmc_writel(val, c->reg);
962 static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw,
963 unsigned long parent_rate)
965 struct clk_tegra *c = to_clk_tegra(hw);
966 u64 rate = parent_rate;
973 val = pmc_readl(c->reg);
975 if (val & PMC_BLINK_TIMER_ENB) {
976 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
977 PMC_BLINK_TIMER_DATA_ON_MASK;
978 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
979 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
981 /* each tick in the blink timer is 4 32KHz clocks */
987 if (mul != 0 && div != 0) {
989 rate += div - 1; /* round up */
995 static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
996 unsigned long *prate)
1000 long round_rate = *prate;
1004 if (rate >= *prate) {
1007 div = DIV_ROUND_UP(*prate / 8, rate);
1012 round_rate += div - 1;
1013 do_div(round_rate, div);
1018 struct clk_ops tegra30_blink_clk_ops = {
1019 .is_enabled = tegra30_blink_clk_is_enabled,
1020 .enable = tegra30_blink_clk_enable,
1021 .disable = tegra30_blink_clk_disable,
1022 .recalc_rate = tegra30_blink_clk_recalc_rate,
1023 .round_rate = tegra30_blink_clk_round_rate,
1024 .set_rate = tegra30_blink_clk_set_rate,
1027 static void tegra30_utmi_param_configure(struct clk_hw *hw)
1029 unsigned long main_rate =
1030 __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
1034 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1035 if (main_rate == utmi_parameters[i].osc_frequency)
1039 if (i >= ARRAY_SIZE(utmi_parameters)) {
1040 pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate);
1044 reg = clk_readl(UTMIP_PLL_CFG2);
1046 /* Program UTMIP PLL stable and active counts */
1047 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1048 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1049 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
1050 utmi_parameters[i].stable_count);
1052 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1054 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
1055 utmi_parameters[i].active_delay_count);
1057 /* Remove power downs from UTMIP PLL control bits */
1058 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1059 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1060 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1062 clk_writel(reg, UTMIP_PLL_CFG2);
1064 /* Program UTMIP PLL delay and oscillator frequency counts */
1065 reg = clk_readl(UTMIP_PLL_CFG1);
1066 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1068 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
1069 utmi_parameters[i].enable_delay_count);
1071 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1072 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
1073 utmi_parameters[i].xtal_freq_count);
1075 /* Remove power downs from UTMIP PLL control bits */
1076 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1077 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1078 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1080 clk_writel(reg, UTMIP_PLL_CFG1);
1084 static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg,
1089 #if USE_PLL_LOCK_BITS
1091 for (i = 0; i < c->u.pll.lock_delay; i++) {
1092 if (clk_readl(lock_reg) & lock_bit) {
1093 udelay(PLL_POST_LOCK_DELAY);
1096 udelay(2); /* timeout = 2 * lock time */
1098 pr_err("Timed out waiting for lock bit on pll %s",
1099 __clk_get_name(hw->clk));
1102 udelay(c->u.pll.lock_delay);
1107 static int tegra30_pll_clk_is_enabled(struct clk_hw *hw)
1109 struct clk_tegra *c = to_clk_tegra(hw);
1110 u32 val = clk_readl(c->reg + PLL_BASE);
1112 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
1116 static void tegra30_pll_clk_init(struct clk_hw *hw)
1118 struct clk_tegra *c = to_clk_tegra(hw);
1120 if (c->flags & PLLU)
1121 tegra30_utmi_param_configure(hw);
1124 static int tegra30_pll_clk_enable(struct clk_hw *hw)
1126 struct clk_tegra *c = to_clk_tegra(hw);
1128 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1130 #if USE_PLL_LOCK_BITS
1131 val = clk_readl(c->reg + PLL_MISC(c));
1132 val |= PLL_MISC_LOCK_ENABLE(c);
1133 clk_writel(val, c->reg + PLL_MISC(c));
1135 val = clk_readl(c->reg + PLL_BASE);
1136 val &= ~PLL_BASE_BYPASS;
1137 val |= PLL_BASE_ENABLE;
1138 clk_writel(val, c->reg + PLL_BASE);
1140 if (c->flags & PLLM) {
1141 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
1142 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
1143 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
1146 tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
1151 static void tegra30_pll_clk_disable(struct clk_hw *hw)
1153 struct clk_tegra *c = to_clk_tegra(hw);
1155 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1157 val = clk_readl(c->reg);
1158 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1159 clk_writel(val, c->reg);
1161 if (c->flags & PLLM) {
1162 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
1163 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
1164 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
1168 static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1169 unsigned long parent_rate)
1171 struct clk_tegra *c = to_clk_tegra(hw);
1172 u32 val, p_div, old_base;
1173 unsigned long input_rate;
1174 const struct clk_pll_freq_table *sel;
1175 struct clk_pll_freq_table cfg;
1177 if (c->flags & PLL_FIXED) {
1179 if (rate != c->u.pll.fixed_rate) {
1180 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
1181 __func__, __clk_get_name(hw->clk),
1182 c->u.pll.fixed_rate, rate);
1188 if (c->flags & PLLM) {
1189 if (rate != __clk_get_rate(hw->clk)) {
1190 pr_err("%s: Can not change memory %s rate in flight\n",
1191 __func__, __clk_get_name(hw->clk));
1197 input_rate = parent_rate;
1199 /* Check if the target rate is tabulated */
1200 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1201 if (sel->input_rate == input_rate && sel->output_rate == rate) {
1202 if (c->flags & PLLU) {
1203 BUG_ON(sel->p < 1 || sel->p > 2);
1205 p_div = PLLU_BASE_POST_DIV;
1208 for (val = sel->p; val > 1; val >>= 1)
1210 p_div <<= PLL_BASE_DIVP_SHIFT;
1216 /* Configure out-of-table rate */
1217 if (sel->input_rate == 0) {
1218 unsigned long cfreq;
1219 BUG_ON(c->flags & PLLU);
1222 switch (input_rate) {
1225 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
1228 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
1232 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
1235 pr_err("%s: Unexpected reference rate %lu\n",
1236 __func__, input_rate);
1240 /* Raise VCO to guarantee 0.5% accuracy */
1241 for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
1242 cfg.output_rate <<= 1)
1245 cfg.p = 0x1 << p_div;
1246 cfg.m = input_rate / cfreq;
1247 cfg.n = cfg.output_rate / cfreq;
1248 cfg.cpcon = OUT_OF_TABLE_CPCON;
1250 if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
1251 (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
1252 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
1253 (cfg.output_rate > c->u.pll.vco_max)) {
1254 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
1255 __func__, __clk_get_name(hw->clk), rate);
1258 p_div <<= PLL_BASE_DIVP_SHIFT;
1262 c->div = sel->m * sel->p;
1264 old_base = val = clk_readl(c->reg + PLL_BASE);
1265 val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK |
1266 ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK));
1267 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
1268 (sel->n << PLL_BASE_DIVN_SHIFT) | p_div;
1269 if (val == old_base)
1272 if (c->state == ON) {
1273 tegra30_pll_clk_disable(hw);
1274 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1276 clk_writel(val, c->reg + PLL_BASE);
1278 if (c->flags & PLL_HAS_CPCON) {
1279 val = clk_readl(c->reg + PLL_MISC(c));
1280 val &= ~PLL_MISC_CPCON_MASK;
1281 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
1282 if (c->flags & (PLLU | PLLD)) {
1283 val &= ~PLL_MISC_LFCON_MASK;
1284 if (sel->n >= PLLDU_LFCON_SET_DIVN)
1285 val |= 0x1 << PLL_MISC_LFCON_SHIFT;
1286 } else if (c->flags & (PLLX | PLLM)) {
1287 val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
1288 if (rate >= (c->u.pll.vco_max >> 1))
1289 val |= 0x1 << PLL_MISC_DCCON_SHIFT;
1291 clk_writel(val, c->reg + PLL_MISC(c));
1295 tegra30_pll_clk_enable(hw);
1297 c->u.pll.fixed_rate = rate;
1302 static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
1303 unsigned long *prate)
1305 struct clk_tegra *c = to_clk_tegra(hw);
1306 unsigned long input_rate = *prate;
1307 u64 output_rate = *prate;
1308 const struct clk_pll_freq_table *sel;
1309 struct clk_pll_freq_table cfg;
1315 if (c->flags & PLL_FIXED)
1316 return c->u.pll.fixed_rate;
1318 if (c->flags & PLLM)
1319 return __clk_get_rate(hw->clk);
1322 /* Check if the target rate is tabulated */
1323 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1324 if (sel->input_rate == input_rate && sel->output_rate == rate) {
1325 if (c->flags & PLLU) {
1326 BUG_ON(sel->p < 1 || sel->p > 2);
1328 p_div = PLLU_BASE_POST_DIV;
1331 for (val = sel->p; val > 1; val >>= 1)
1333 p_div <<= PLL_BASE_DIVP_SHIFT;
1339 if (sel->input_rate == 0) {
1340 unsigned long cfreq;
1341 BUG_ON(c->flags & PLLU);
1344 switch (input_rate) {
1347 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
1350 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
1354 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
1357 pr_err("%s: Unexpected reference rate %lu\n",
1358 __func__, input_rate);
1362 /* Raise VCO to guarantee 0.5% accuracy */
1363 for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
1364 cfg.output_rate <<= 1)
1367 cfg.p = 0x1 << p_div;
1368 cfg.m = input_rate / cfreq;
1369 cfg.n = cfg.output_rate / cfreq;
1373 div = sel->m * sel->p;
1376 output_rate += div - 1; /* round up */
1377 do_div(output_rate, div);
1382 static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw,
1383 unsigned long parent_rate)
1385 struct clk_tegra *c = to_clk_tegra(hw);
1386 u64 rate = parent_rate;
1387 u32 val = clk_readl(c->reg + PLL_BASE);
1389 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
1390 const struct clk_pll_freq_table *sel;
1391 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1392 if (sel->input_rate == parent_rate &&
1393 sel->output_rate == c->u.pll.fixed_rate) {
1395 c->div = sel->m * sel->p;
1399 pr_err("Clock %s has unknown fixed frequency\n",
1400 __clk_get_name(hw->clk));
1402 } else if (val & PLL_BASE_BYPASS) {
1406 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
1407 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
1408 if (c->flags & PLLU)
1409 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
1411 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
1412 PLL_BASE_DIVP_SHIFT));
1415 if (c->mul != 0 && c->div != 0) {
1417 rate += c->div - 1; /* round up */
1418 do_div(rate, c->div);
1424 struct clk_ops tegra30_pll_ops = {
1425 .is_enabled = tegra30_pll_clk_is_enabled,
1426 .init = tegra30_pll_clk_init,
1427 .enable = tegra30_pll_clk_enable,
1428 .disable = tegra30_pll_clk_disable,
1429 .recalc_rate = tegra30_pll_recalc_rate,
1430 .round_rate = tegra30_pll_round_rate,
1431 .set_rate = tegra30_pll_clk_set_rate,
1434 int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
1435 enum tegra_clk_ex_param p, u32 setting)
1437 struct clk_tegra *c = to_clk_tegra(hw);
1441 case TEGRA_CLK_PLLD_CSI_OUT_ENB:
1442 mask = PLLD_BASE_CSI_CLKENABLE;
1443 reg = c->reg + PLL_BASE;
1445 case TEGRA_CLK_PLLD_DSI_OUT_ENB:
1446 mask = PLLD_MISC_DSI_CLKENABLE;
1447 reg = c->reg + PLL_MISC(c);
1449 case TEGRA_CLK_PLLD_MIPI_MUX_SEL:
1450 if (!(c->flags & PLL_ALT_MISC_REG)) {
1451 mask = PLLD_BASE_DSIB_MUX_MASK;
1452 reg = c->reg + PLL_BASE;
1455 /* fall through - error since PLLD2 does not have MUX_SEL control */
1460 val = clk_readl(reg);
1465 clk_writel(val, reg);
1469 static int tegra30_plle_clk_is_enabled(struct clk_hw *hw)
1471 struct clk_tegra *c = to_clk_tegra(hw);
1474 val = clk_readl(c->reg + PLL_BASE);
1475 c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
1479 static void tegra30_plle_clk_disable(struct clk_hw *hw)
1481 struct clk_tegra *c = to_clk_tegra(hw);
1484 val = clk_readl(c->reg + PLL_BASE);
1485 val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
1486 clk_writel(val, c->reg + PLL_BASE);
1489 static void tegra30_plle_training(struct clk_tegra *c)
1493 /* PLLE is already disabled, and setup cleared;
1494 * create falling edge on PLLE IDDQ input */
1495 val = pmc_readl(PMC_SATA_PWRGT);
1496 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
1497 pmc_writel(val, PMC_SATA_PWRGT);
1499 val = pmc_readl(PMC_SATA_PWRGT);
1500 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
1501 pmc_writel(val, PMC_SATA_PWRGT);
1503 val = pmc_readl(PMC_SATA_PWRGT);
1504 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
1505 pmc_writel(val, PMC_SATA_PWRGT);
1508 val = clk_readl(c->reg + PLL_MISC(c));
1509 } while (!(val & PLLE_MISC_READY));
1512 static int tegra30_plle_configure(struct clk_hw *hw, bool force_training)
1514 struct clk_tegra *c = to_clk_tegra(hw);
1515 struct clk *parent = __clk_get_parent(hw->clk);
1516 const struct clk_pll_freq_table *sel;
1519 unsigned long rate = c->u.pll.fixed_rate;
1520 unsigned long input_rate = __clk_get_rate(parent);
1522 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1523 if (sel->input_rate == input_rate && sel->output_rate == rate)
1527 if (sel->input_rate == 0)
1530 /* disable PLLE, clear setup fiels */
1531 tegra30_plle_clk_disable(hw);
1533 val = clk_readl(c->reg + PLL_MISC(c));
1534 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
1535 clk_writel(val, c->reg + PLL_MISC(c));
1538 val = clk_readl(c->reg + PLL_MISC(c));
1539 if (force_training || (!(val & PLLE_MISC_READY)))
1540 tegra30_plle_training(c);
1542 /* configure dividers, setup, disable SS */
1543 val = clk_readl(c->reg + PLL_BASE);
1544 val &= ~PLLE_BASE_DIV_MASK;
1545 val |= PLLE_BASE_DIV(sel->m, sel->n, sel->p, sel->cpcon);
1546 clk_writel(val, c->reg + PLL_BASE);
1548 c->div = sel->m * sel->p;
1550 val = clk_readl(c->reg + PLL_MISC(c));
1551 val |= PLLE_MISC_SETUP_VALUE;
1552 val |= PLLE_MISC_LOCK_ENABLE;
1553 clk_writel(val, c->reg + PLL_MISC(c));
1555 val = clk_readl(PLLE_SS_CTRL);
1556 val |= PLLE_SS_DISABLE;
1557 clk_writel(val, PLLE_SS_CTRL);
1559 /* enable and lock PLLE*/
1560 val = clk_readl(c->reg + PLL_BASE);
1561 val |= (PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
1562 clk_writel(val, c->reg + PLL_BASE);
1564 tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
1569 static int tegra30_plle_clk_enable(struct clk_hw *hw)
1571 struct clk_tegra *c = to_clk_tegra(hw);
1573 return tegra30_plle_configure(hw, !c->set);
1576 static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw,
1577 unsigned long parent_rate)
1579 struct clk_tegra *c = to_clk_tegra(hw);
1580 unsigned long rate = parent_rate;
1583 val = clk_readl(c->reg + PLL_BASE);
1584 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
1585 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
1586 c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
1588 if (c->mul != 0 && c->div != 0) {
1590 rate += c->div - 1; /* round up */
1591 do_div(rate, c->div);
1596 struct clk_ops tegra30_plle_ops = {
1597 .is_enabled = tegra30_plle_clk_is_enabled,
1598 .enable = tegra30_plle_clk_enable,
1599 .disable = tegra30_plle_clk_disable,
1600 .recalc_rate = tegra30_plle_clk_recalc_rate,
1603 /* Clock divider ops */
1604 static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw)
1606 struct clk_tegra *c = to_clk_tegra(hw);
1608 if (c->flags & DIV_U71) {
1609 u32 val = clk_readl(c->reg);
1610 val >>= c->reg_shift;
1611 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
1612 if (!(val & PLL_OUT_RESET_DISABLE))
1620 static int tegra30_pll_div_clk_enable(struct clk_hw *hw)
1622 struct clk_tegra *c = to_clk_tegra(hw);
1626 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
1627 if (c->flags & DIV_U71) {
1628 val = clk_readl(c->reg);
1629 new_val = val >> c->reg_shift;
1632 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
1634 val &= ~(0xFFFF << c->reg_shift);
1635 val |= new_val << c->reg_shift;
1636 clk_writel_delay(val, c->reg);
1638 } else if (c->flags & DIV_2) {
1644 static void tegra30_pll_div_clk_disable(struct clk_hw *hw)
1646 struct clk_tegra *c = to_clk_tegra(hw);
1650 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
1651 if (c->flags & DIV_U71) {
1652 val = clk_readl(c->reg);
1653 new_val = val >> c->reg_shift;
1656 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
1658 val &= ~(0xFFFF << c->reg_shift);
1659 val |= new_val << c->reg_shift;
1660 clk_writel_delay(val, c->reg);
1664 static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1665 unsigned long parent_rate)
1667 struct clk_tegra *c = to_clk_tegra(hw);
1672 if (c->flags & DIV_U71) {
1673 divider_u71 = clk_div71_get_divider(
1674 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1675 if (divider_u71 >= 0) {
1676 val = clk_readl(c->reg);
1677 new_val = val >> c->reg_shift;
1679 if (c->flags & DIV_U71_FIXED)
1680 new_val |= PLL_OUT_OVERRIDE;
1681 new_val &= ~PLL_OUT_RATIO_MASK;
1682 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
1684 val &= ~(0xFFFF << c->reg_shift);
1685 val |= new_val << c->reg_shift;
1686 clk_writel_delay(val, c->reg);
1687 c->div = divider_u71 + 2;
1689 c->fixed_rate = rate;
1692 } else if (c->flags & DIV_2) {
1693 c->fixed_rate = rate;
1700 static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw,
1701 unsigned long parent_rate)
1703 struct clk_tegra *c = to_clk_tegra(hw);
1704 u64 rate = parent_rate;
1706 if (c->flags & DIV_U71) {
1708 u32 val = clk_readl(c->reg);
1709 val >>= c->reg_shift;
1711 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
1712 c->div = (divu71 + 2);
1714 } else if (c->flags & DIV_2) {
1715 if (c->flags & (PLLD | PLLX)) {
1724 if (c->mul != 0 && c->div != 0) {
1726 rate += c->div - 1; /* round up */
1727 do_div(rate, c->div);
1733 static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw,
1734 unsigned long rate, unsigned long *prate)
1736 struct clk_tegra *c = to_clk_tegra(hw);
1737 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1741 parent_rate = *prate;
1743 if (c->flags & DIV_U71) {
1744 divider = clk_div71_get_divider(
1745 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1748 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1749 } else if (c->flags & DIV_2) {
1757 struct clk_ops tegra30_pll_div_ops = {
1758 .is_enabled = tegra30_pll_div_clk_is_enabled,
1759 .enable = tegra30_pll_div_clk_enable,
1760 .disable = tegra30_pll_div_clk_disable,
1761 .set_rate = tegra30_pll_div_clk_set_rate,
1762 .recalc_rate = tegra30_pll_div_clk_recalc_rate,
1763 .round_rate = tegra30_pll_div_clk_round_rate,
1766 /* Periph clk ops */
1767 static inline u32 periph_clk_source_mask(struct clk_tegra *c)
1769 if (c->flags & MUX8)
1771 else if (c->flags & MUX_PWM)
1773 else if (c->flags & MUX_CLK_OUT)
1774 return 3 << (c->u.periph.clk_num + 4);
1775 else if (c->flags & PLLD)
1776 return PLLD_BASE_DSIB_MUX_MASK;
1781 static inline u32 periph_clk_source_shift(struct clk_tegra *c)
1783 if (c->flags & MUX8)
1785 else if (c->flags & MUX_PWM)
1787 else if (c->flags & MUX_CLK_OUT)
1788 return c->u.periph.clk_num + 4;
1789 else if (c->flags & PLLD)
1790 return PLLD_BASE_DSIB_MUX_SHIFT;
1795 static int tegra30_periph_clk_is_enabled(struct clk_hw *hw)
1797 struct clk_tegra *c = to_clk_tegra(hw);
1800 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
1802 if (!(c->flags & PERIPH_NO_RESET))
1803 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
1808 static int tegra30_periph_clk_enable(struct clk_hw *hw)
1810 struct clk_tegra *c = to_clk_tegra(hw);
1812 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
1813 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
1816 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c));
1817 if (!(c->flags & PERIPH_NO_RESET) &&
1818 !(c->flags & PERIPH_MANUAL_RESET)) {
1819 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) &
1820 PERIPH_CLK_TO_BIT(c)) {
1821 udelay(5); /* reset propagation delay */
1822 clk_writel(PERIPH_CLK_TO_BIT(c),
1823 PERIPH_CLK_TO_RST_CLR_REG(c));
1829 static void tegra30_periph_clk_disable(struct clk_hw *hw)
1831 struct clk_tegra *c = to_clk_tegra(hw);
1834 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1836 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
1839 /* If peripheral is in the APB bus then read the APB bus to
1840 * flush the write operation in apb bus. This will avoid the
1841 * peripheral access after disabling clock*/
1842 if (c->flags & PERIPH_ON_APB)
1843 val = chipid_readl();
1845 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
1848 void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert)
1850 struct clk_tegra *c = to_clk_tegra(hw);
1853 if (!(c->flags & PERIPH_NO_RESET)) {
1855 /* If peripheral is in the APB bus then read the APB
1856 * bus to flush the write operation in apb bus. This
1857 * will avoid the peripheral access after disabling
1859 if (c->flags & PERIPH_ON_APB)
1860 val = chipid_readl();
1862 clk_writel(PERIPH_CLK_TO_BIT(c),
1863 PERIPH_CLK_TO_RST_SET_REG(c));
1865 clk_writel(PERIPH_CLK_TO_BIT(c),
1866 PERIPH_CLK_TO_RST_CLR_REG(c));
1870 static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index)
1872 struct clk_tegra *c = to_clk_tegra(hw);
1875 if (!(c->flags & MUX))
1876 return (index == 0) ? 0 : (-EINVAL);
1878 val = clk_readl(c->reg);
1879 val &= ~periph_clk_source_mask(c);
1880 val |= (index << periph_clk_source_shift(c));
1881 clk_writel_delay(val, c->reg);
1885 static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw)
1887 struct clk_tegra *c = to_clk_tegra(hw);
1888 u32 val = clk_readl(c->reg);
1889 int source = (val & periph_clk_source_mask(c)) >>
1890 periph_clk_source_shift(c);
1892 if (!(c->flags & MUX))
1898 static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1899 unsigned long parent_rate)
1901 struct clk_tegra *c = to_clk_tegra(hw);
1905 if (c->flags & DIV_U71) {
1906 divider = clk_div71_get_divider(
1907 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1909 val = clk_readl(c->reg);
1910 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1912 if (c->flags & DIV_U71_UART) {
1914 val |= PERIPH_CLK_UART_DIV_ENB;
1916 val &= ~PERIPH_CLK_UART_DIV_ENB;
1918 clk_writel_delay(val, c->reg);
1919 c->div = divider + 2;
1923 } else if (c->flags & DIV_U16) {
1924 divider = clk_div16_get_divider(parent_rate, rate);
1926 val = clk_readl(c->reg);
1927 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1929 clk_writel_delay(val, c->reg);
1930 c->div = divider + 1;
1934 } else if (parent_rate <= rate) {
1942 static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1943 unsigned long *prate)
1945 struct clk_tegra *c = to_clk_tegra(hw);
1946 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1950 parent_rate = *prate;
1952 if (c->flags & DIV_U71) {
1953 divider = clk_div71_get_divider(
1954 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1958 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1959 } else if (c->flags & DIV_U16) {
1960 divider = clk_div16_get_divider(parent_rate, rate);
1963 return DIV_ROUND_UP(parent_rate, divider + 1);
1968 static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw,
1969 unsigned long parent_rate)
1971 struct clk_tegra *c = to_clk_tegra(hw);
1972 u64 rate = parent_rate;
1973 u32 val = clk_readl(c->reg);
1975 if (c->flags & DIV_U71) {
1976 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1977 if ((c->flags & DIV_U71_UART) &&
1978 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
1981 if (c->flags & DIV_U71_IDLE) {
1982 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
1983 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1984 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
1985 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1986 clk_writel(val, c->reg);
1988 c->div = divu71 + 2;
1990 } else if (c->flags & DIV_U16) {
1991 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1992 c->div = divu16 + 1;
1999 if (c->mul != 0 && c->div != 0) {
2001 rate += c->div - 1; /* round up */
2002 do_div(rate, c->div);
2007 struct clk_ops tegra30_periph_clk_ops = {
2008 .is_enabled = tegra30_periph_clk_is_enabled,
2009 .enable = tegra30_periph_clk_enable,
2010 .disable = tegra30_periph_clk_disable,
2011 .set_parent = tegra30_periph_clk_set_parent,
2012 .get_parent = tegra30_periph_clk_get_parent,
2013 .set_rate = tegra30_periph_clk_set_rate,
2014 .round_rate = tegra30_periph_clk_round_rate,
2015 .recalc_rate = tegra30_periph_clk_recalc_rate,
2018 static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
2020 struct clk *d = clk_get_sys(NULL, "pll_d");
2021 /* The DSIB parent selection bit is in PLLD base
2022 register - can not do direct r-m-w, must be
2023 protected by PLLD lock */
2025 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
2030 struct clk_ops tegra30_dsib_clk_ops = {
2031 .is_enabled = tegra30_periph_clk_is_enabled,
2032 .enable = &tegra30_periph_clk_enable,
2033 .disable = &tegra30_periph_clk_disable,
2034 .set_parent = &tegra30_dsib_clk_set_parent,
2035 .get_parent = &tegra30_periph_clk_get_parent,
2036 .set_rate = &tegra30_periph_clk_set_rate,
2037 .round_rate = &tegra30_periph_clk_round_rate,
2038 .recalc_rate = &tegra30_periph_clk_recalc_rate,
2041 /* Periph extended clock configuration ops */
2042 int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
2043 enum tegra_clk_ex_param p, u32 setting)
2045 struct clk_tegra *c = to_clk_tegra(hw);
2047 if (p == TEGRA_CLK_VI_INP_SEL) {
2048 u32 val = clk_readl(c->reg);
2049 val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
2050 val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) &
2051 PERIPH_CLK_VI_SEL_EX_MASK;
2052 clk_writel(val, c->reg);
2058 int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
2059 enum tegra_clk_ex_param p, u32 setting)
2061 struct clk_tegra *c = to_clk_tegra(hw);
2063 if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
2064 u32 val = clk_readl(c->reg);
2066 val |= PERIPH_CLK_NAND_DIV_EX_ENB;
2068 val &= ~PERIPH_CLK_NAND_DIV_EX_ENB;
2069 clk_writel(val, c->reg);
2075 int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
2076 enum tegra_clk_ex_param p, u32 setting)
2078 struct clk_tegra *c = to_clk_tegra(hw);
2080 if (p == TEGRA_CLK_DTV_INVERT) {
2081 u32 val = clk_readl(c->reg);
2083 val |= PERIPH_CLK_DTV_POLARITY_INV;
2085 val &= ~PERIPH_CLK_DTV_POLARITY_INV;
2086 clk_writel(val, c->reg);
2092 /* Output clock ops */
2094 static DEFINE_SPINLOCK(clk_out_lock);
2096 static int tegra30_clk_out_is_enabled(struct clk_hw *hw)
2098 struct clk_tegra *c = to_clk_tegra(hw);
2099 u32 val = pmc_readl(c->reg);
2101 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
2107 static int tegra30_clk_out_enable(struct clk_hw *hw)
2109 struct clk_tegra *c = to_clk_tegra(hw);
2111 unsigned long flags;
2113 spin_lock_irqsave(&clk_out_lock, flags);
2114 val = pmc_readl(c->reg);
2115 val |= (0x1 << c->u.periph.clk_num);
2116 pmc_writel(val, c->reg);
2117 spin_unlock_irqrestore(&clk_out_lock, flags);
2122 static void tegra30_clk_out_disable(struct clk_hw *hw)
2124 struct clk_tegra *c = to_clk_tegra(hw);
2126 unsigned long flags;
2128 spin_lock_irqsave(&clk_out_lock, flags);
2129 val = pmc_readl(c->reg);
2130 val &= ~(0x1 << c->u.periph.clk_num);
2131 pmc_writel(val, c->reg);
2132 spin_unlock_irqrestore(&clk_out_lock, flags);
2135 static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index)
2137 struct clk_tegra *c = to_clk_tegra(hw);
2139 unsigned long flags;
2141 spin_lock_irqsave(&clk_out_lock, flags);
2142 val = pmc_readl(c->reg);
2143 val &= ~periph_clk_source_mask(c);
2144 val |= (index << periph_clk_source_shift(c));
2145 pmc_writel(val, c->reg);
2146 spin_unlock_irqrestore(&clk_out_lock, flags);
2151 static u8 tegra30_clk_out_get_parent(struct clk_hw *hw)
2153 struct clk_tegra *c = to_clk_tegra(hw);
2154 u32 val = pmc_readl(c->reg);
2157 source = (val & periph_clk_source_mask(c)) >>
2158 periph_clk_source_shift(c);
2162 struct clk_ops tegra_clk_out_ops = {
2163 .is_enabled = tegra30_clk_out_is_enabled,
2164 .enable = tegra30_clk_out_enable,
2165 .disable = tegra30_clk_out_disable,
2166 .set_parent = tegra30_clk_out_set_parent,
2167 .get_parent = tegra30_clk_out_get_parent,
2168 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2171 /* Clock doubler ops */
2172 static int tegra30_clk_double_is_enabled(struct clk_hw *hw)
2174 struct clk_tegra *c = to_clk_tegra(hw);
2177 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
2182 static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
2183 unsigned long parent_rate)
2185 struct clk_tegra *c = to_clk_tegra(hw);
2188 if (rate == parent_rate) {
2189 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
2190 clk_writel(val, c->reg);
2194 } else if (rate == 2 * parent_rate) {
2195 val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
2196 clk_writel(val, c->reg);
2204 static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw,
2205 unsigned long parent_rate)
2207 struct clk_tegra *c = to_clk_tegra(hw);
2208 u64 rate = parent_rate;
2210 u32 val = clk_readl(c->reg);
2211 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
2214 if (c->mul != 0 && c->div != 0) {
2216 rate += c->div - 1; /* round up */
2217 do_div(rate, c->div);
2223 static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
2224 unsigned long *prate)
2226 unsigned long output_rate = *prate;
2228 do_div(output_rate, 2);
2232 struct clk_ops tegra30_clk_double_ops = {
2233 .is_enabled = tegra30_clk_double_is_enabled,
2234 .enable = tegra30_periph_clk_enable,
2235 .disable = tegra30_periph_clk_disable,
2236 .recalc_rate = tegra30_clk_double_recalc_rate,
2237 .round_rate = tegra30_clk_double_round_rate,
2238 .set_rate = tegra30_clk_double_set_rate,
2241 /* Audio sync clock ops */
2242 struct clk_ops tegra_sync_source_ops = {
2243 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2246 static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw)
2248 struct clk_tegra *c = to_clk_tegra(hw);
2249 u32 val = clk_readl(c->reg);
2250 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
2254 static int tegra30_audio_sync_clk_enable(struct clk_hw *hw)
2256 struct clk_tegra *c = to_clk_tegra(hw);
2257 u32 val = clk_readl(c->reg);
2258 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
2262 static void tegra30_audio_sync_clk_disable(struct clk_hw *hw)
2264 struct clk_tegra *c = to_clk_tegra(hw);
2265 u32 val = clk_readl(c->reg);
2266 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
2269 static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
2271 struct clk_tegra *c = to_clk_tegra(hw);
2274 val = clk_readl(c->reg);
2275 val &= ~AUDIO_SYNC_SOURCE_MASK;
2278 clk_writel(val, c->reg);
2282 static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw)
2284 struct clk_tegra *c = to_clk_tegra(hw);
2285 u32 val = clk_readl(c->reg);
2288 source = val & AUDIO_SYNC_SOURCE_MASK;
2292 struct clk_ops tegra30_audio_sync_clk_ops = {
2293 .is_enabled = tegra30_audio_sync_clk_is_enabled,
2294 .enable = tegra30_audio_sync_clk_enable,
2295 .disable = tegra30_audio_sync_clk_disable,
2296 .set_parent = tegra30_audio_sync_clk_set_parent,
2297 .get_parent = tegra30_audio_sync_clk_get_parent,
2298 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2301 /* cml0 (pcie), and cml1 (sata) clock ops */
2302 static int tegra30_cml_clk_is_enabled(struct clk_hw *hw)
2304 struct clk_tegra *c = to_clk_tegra(hw);
2305 u32 val = clk_readl(c->reg);
2306 c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
2310 static int tegra30_cml_clk_enable(struct clk_hw *hw)
2312 struct clk_tegra *c = to_clk_tegra(hw);
2314 u32 val = clk_readl(c->reg);
2315 val |= (0x1 << c->u.periph.clk_num);
2316 clk_writel(val, c->reg);
2321 static void tegra30_cml_clk_disable(struct clk_hw *hw)
2323 struct clk_tegra *c = to_clk_tegra(hw);
2325 u32 val = clk_readl(c->reg);
2326 val &= ~(0x1 << c->u.periph.clk_num);
2327 clk_writel(val, c->reg);
2330 struct clk_ops tegra_cml_clk_ops = {
2331 .is_enabled = tegra30_cml_clk_is_enabled,
2332 .enable = tegra30_cml_clk_enable,
2333 .disable = tegra30_cml_clk_disable,
2334 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2337 struct clk_ops tegra_pciex_clk_ops = {
2338 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2341 /* Tegra30 CPU clock and reset control functions */
2342 static void tegra30_wait_cpu_in_reset(u32 cpu)
2347 reg = readl(reg_clk_base +
2348 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
2350 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
2355 static void tegra30_put_cpu_in_reset(u32 cpu)
2357 writel(CPU_RESET(cpu),
2358 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
2362 static void tegra30_cpu_out_of_reset(u32 cpu)
2364 writel(CPU_RESET(cpu),
2365 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
2369 static void tegra30_enable_cpu_clock(u32 cpu)
2373 writel(CPU_CLOCK(cpu),
2374 reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
2375 reg = readl(reg_clk_base +
2376 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
2379 static void tegra30_disable_cpu_clock(u32 cpu)
2384 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
2385 writel(reg | CPU_CLOCK(cpu),
2386 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
2389 static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
2390 .wait_for_reset = tegra30_wait_cpu_in_reset,
2391 .put_in_reset = tegra30_put_cpu_in_reset,
2392 .out_of_reset = tegra30_cpu_out_of_reset,
2393 .enable_clock = tegra30_enable_cpu_clock,
2394 .disable_clock = tegra30_disable_cpu_clock,
2397 void __init tegra30_cpu_car_ops_init(void)
2399 tegra_cpu_car_ops = &tegra30_cpu_car_ops;