2 * arch/arch/mach-tegra/timer.c
4 * Copyright (C) 2010 Google, Inc.
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/err.h>
22 #include <linux/time.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/clockchips.h>
26 #include <linux/clocksource.h>
27 #include <linux/clk.h>
29 #include <linux/of_irq.h>
31 #include <asm/mach/time.h>
32 #include <asm/smp_twd.h>
33 #include <asm/sched_clock.h>
35 #include <mach/iomap.h>
40 #define RTC_SECONDS 0x08
41 #define RTC_SHADOW_SECONDS 0x0c
42 #define RTC_MILLISECONDS 0x10
44 #define TIMERUS_CNTR_1US 0x10
45 #define TIMERUS_USEC_CFG 0x14
46 #define TIMERUS_CNTR_FREEZE 0x4c
48 #define TIMER1_BASE 0x0
49 #define TIMER2_BASE 0x8
50 #define TIMER3_BASE 0x50
51 #define TIMER4_BASE 0x58
56 static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
57 static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE);
59 static struct timespec persistent_ts;
60 static u64 persistent_ms, last_persistent_ms;
62 #define timer_writel(value, reg) \
63 __raw_writel(value, timer_reg_base + (reg))
64 #define timer_readl(reg) \
65 __raw_readl(timer_reg_base + (reg))
67 static int tegra_timer_set_next_event(unsigned long cycles,
68 struct clock_event_device *evt)
72 reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
73 timer_writel(reg, TIMER3_BASE + TIMER_PTV);
78 static void tegra_timer_set_mode(enum clock_event_mode mode,
79 struct clock_event_device *evt)
83 timer_writel(0, TIMER3_BASE + TIMER_PTV);
86 case CLOCK_EVT_MODE_PERIODIC:
87 reg = 0xC0000000 | ((1000000/HZ)-1);
88 timer_writel(reg, TIMER3_BASE + TIMER_PTV);
90 case CLOCK_EVT_MODE_ONESHOT:
92 case CLOCK_EVT_MODE_UNUSED:
93 case CLOCK_EVT_MODE_SHUTDOWN:
94 case CLOCK_EVT_MODE_RESUME:
99 static struct clock_event_device tegra_clockevent = {
102 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
103 .set_next_event = tegra_timer_set_next_event,
104 .set_mode = tegra_timer_set_mode,
107 static u32 notrace tegra_read_sched_clock(void)
109 return timer_readl(TIMERUS_CNTR_1US);
113 * tegra_rtc_read - Reads the Tegra RTC registers
114 * Care must be taken that this funciton is not called while the
115 * tegra_rtc driver could be executing to avoid race conditions
116 * on the RTC shadow register
118 static u64 tegra_rtc_read_ms(void)
120 u32 ms = readl(rtc_base + RTC_MILLISECONDS);
121 u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
122 return (u64)s * MSEC_PER_SEC + ms;
126 * tegra_read_persistent_clock - Return time from a persistent clock.
128 * Reads the time from a source which isn't disabled during PM, the
129 * 32k sync timer. Convert the cycles elapsed since last read into
130 * nsecs and adds to a monotonically increasing timespec.
131 * Care must be taken that this funciton is not called while the
132 * tegra_rtc driver could be executing to avoid race conditions
133 * on the RTC shadow register
135 static void tegra_read_persistent_clock(struct timespec *ts)
138 struct timespec *tsp = &persistent_ts;
140 last_persistent_ms = persistent_ms;
141 persistent_ms = tegra_rtc_read_ms();
142 delta = persistent_ms - last_persistent_ms;
144 timespec_add_ns(tsp, delta * NSEC_PER_MSEC);
148 static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
150 struct clock_event_device *evt = (struct clock_event_device *)dev_id;
151 timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
152 evt->event_handler(evt);
156 static struct irqaction tegra_timer_irq = {
158 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
159 .handler = tegra_timer_interrupt,
160 .dev_id = &tegra_clockevent,
163 static const struct of_device_id timer_match[] __initconst = {
164 { .compatible = "nvidia,tegra20-timer" },
168 static void __init tegra_init_timer(void)
170 struct device_node *np;
175 np = of_find_matching_node(NULL, timer_match);
177 pr_err("Failed to find timer DT node\n");
181 tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
182 if (tegra_timer_irq.irq <= 0) {
183 pr_err("Failed to map timer IRQ\n");
187 clk = clk_get_sys("timer", NULL);
189 pr_warn("Unable to get timer clock."
190 " Assuming 12Mhz input clock.\n");
193 clk_prepare_enable(clk);
194 rate = clk_get_rate(clk);
198 * rtc registers are used by read_persistent_clock, keep the rtc clock
201 clk = clk_get_sys("rtc-tegra", NULL);
203 pr_warn("Unable to get rtc-tegra clock\n");
205 clk_prepare_enable(clk);
211 timer_writel(0x000b, TIMERUS_USEC_CFG);
214 timer_writel(0x000c, TIMERUS_USEC_CFG);
217 timer_writel(0x045f, TIMERUS_USEC_CFG);
220 timer_writel(0x0019, TIMERUS_USEC_CFG);
223 WARN(1, "Unknown clock rate");
226 setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
228 if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
229 "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
230 printk(KERN_ERR "Failed to register clocksource\n");
234 ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
236 printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
240 clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
241 tegra_clockevent.max_delta_ns =
242 clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
243 tegra_clockevent.min_delta_ns =
244 clockevent_delta2ns(0x1, &tegra_clockevent);
245 tegra_clockevent.cpumask = cpu_all_mask;
246 tegra_clockevent.irq = tegra_timer_irq.irq;
247 clockevents_register_device(&tegra_clockevent);
248 #ifdef CONFIG_HAVE_ARM_TWD
249 twd_local_timer_of_register();
251 register_persistent_clock(NULL, tegra_read_persistent_clock);
254 struct sys_timer tegra_sys_timer = {
255 .init = tegra_init_timer,
259 static u32 usec_config;
261 void tegra_timer_suspend(void)
263 usec_config = timer_readl(TIMERUS_USEC_CFG);
266 void tegra_timer_resume(void)
268 timer_writel(usec_config, TIMERUS_USEC_CFG);