2 * arch/arm/mach-tegra/usb_phy.c
4 * Copyright (C) 2010 Google, Inc.
7 * Erik Gilling <konkers@google.com>
8 * Benoit Goby <benoit@android.com>
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 #include <linux/resource.h>
22 #include <linux/delay.h>
23 #include <linux/slab.h>
24 #include <linux/err.h>
25 #include <linux/export.h>
26 #include <linux/platform_device.h>
28 #include <linux/gpio.h>
29 #include <linux/of_gpio.h>
30 #include <linux/usb/otg.h>
31 #include <linux/usb/ulpi.h>
32 #include <asm/mach-types.h>
33 #include <mach/gpio-tegra.h>
34 #include <mach/usb_phy.h>
35 #include <mach/iomap.h>
37 #define ULPI_VIEWPORT 0x170
39 #define USB_PORTSC1 0x184
40 #define USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
41 #define USB_PORTSC1_PSPD(x) (((x) & 0x3) << 26)
42 #define USB_PORTSC1_PHCD (1 << 23)
43 #define USB_PORTSC1_WKOC (1 << 22)
44 #define USB_PORTSC1_WKDS (1 << 21)
45 #define USB_PORTSC1_WKCN (1 << 20)
46 #define USB_PORTSC1_PTC(x) (((x) & 0xf) << 16)
47 #define USB_PORTSC1_PP (1 << 12)
48 #define USB_PORTSC1_SUSP (1 << 7)
49 #define USB_PORTSC1_PE (1 << 2)
50 #define USB_PORTSC1_CCS (1 << 0)
52 #define USB_SUSP_CTRL 0x400
53 #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
54 #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
55 #define USB_SUSP_CLR (1 << 5)
56 #define USB_PHY_CLK_VALID (1 << 7)
57 #define UTMIP_RESET (1 << 11)
58 #define UHSIC_RESET (1 << 11)
59 #define UTMIP_PHY_ENABLE (1 << 12)
60 #define ULPI_PHY_ENABLE (1 << 13)
61 #define USB_SUSP_SET (1 << 14)
62 #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
64 #define USB1_LEGACY_CTRL 0x410
65 #define USB1_NO_LEGACY_MODE (1 << 0)
66 #define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
67 #define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
68 #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
70 #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
71 #define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
73 #define ULPI_TIMING_CTRL_0 0x424
74 #define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
75 #define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
77 #define ULPI_TIMING_CTRL_1 0x428
78 #define ULPI_DATA_TRIMMER_LOAD (1 << 0)
79 #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
80 #define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
81 #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
82 #define ULPI_DIR_TRIMMER_LOAD (1 << 24)
83 #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
85 #define UTMIP_PLL_CFG1 0x804
86 #define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
87 #define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
89 #define UTMIP_XCVR_CFG0 0x808
90 #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
91 #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
92 #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
93 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
94 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
95 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
96 #define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25)
98 #define UTMIP_BIAS_CFG0 0x80c
99 #define UTMIP_OTGPD (1 << 11)
100 #define UTMIP_BIASPD (1 << 10)
102 #define UTMIP_HSRX_CFG0 0x810
103 #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
104 #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
106 #define UTMIP_HSRX_CFG1 0x814
107 #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
109 #define UTMIP_TX_CFG0 0x820
110 #define UTMIP_FS_PREABMLE_J (1 << 19)
111 #define UTMIP_HS_DISCON_DISABLE (1 << 8)
113 #define UTMIP_MISC_CFG0 0x824
114 #define UTMIP_DPDM_OBSERVE (1 << 26)
115 #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
116 #define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
117 #define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
118 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
119 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
120 #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
122 #define UTMIP_MISC_CFG1 0x828
123 #define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
124 #define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
126 #define UTMIP_DEBOUNCE_CFG0 0x82c
127 #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
129 #define UTMIP_BAT_CHRG_CFG0 0x830
130 #define UTMIP_PD_CHRG (1 << 0)
132 #define UTMIP_SPARE_CFG0 0x834
133 #define FUSE_SETUP_SEL (1 << 3)
135 #define UTMIP_XCVR_CFG1 0x838
136 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
137 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
138 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
139 #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
141 #define UTMIP_BIAS_CFG1 0x83c
142 #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
144 static DEFINE_SPINLOCK(utmip_pad_lock);
145 static int utmip_pad_count;
147 struct tegra_xtal_freq {
156 static const struct tegra_xtal_freq tegra_freq_table[] = {
159 .enable_delay = 0x02,
160 .stable_count = 0x2F,
161 .active_delay = 0x04,
162 .xtal_freq_count = 0x76,
167 .enable_delay = 0x02,
168 .stable_count = 0x33,
169 .active_delay = 0x05,
170 .xtal_freq_count = 0x7F,
175 .enable_delay = 0x03,
176 .stable_count = 0x4B,
177 .active_delay = 0x06,
178 .xtal_freq_count = 0xBB,
183 .enable_delay = 0x04,
184 .stable_count = 0x66,
185 .active_delay = 0x09,
186 .xtal_freq_count = 0xFE,
191 static struct tegra_utmip_config utmip_default[] = {
193 .hssync_start_delay = 9,
194 .idle_wait_delay = 17,
202 .hssync_start_delay = 9,
203 .idle_wait_delay = 17,
212 static inline bool phy_is_ulpi(struct tegra_usb_phy *phy)
214 return (phy->instance == 1);
217 static int utmip_pad_open(struct tegra_usb_phy *phy)
219 phy->pad_clk = clk_get_sys("utmip-pad", NULL);
220 if (IS_ERR(phy->pad_clk)) {
221 pr_err("%s: can't get utmip pad clock\n", __func__);
222 return PTR_ERR(phy->pad_clk);
225 if (phy->instance == 0) {
226 phy->pad_regs = phy->regs;
228 phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE);
229 if (!phy->pad_regs) {
230 pr_err("%s: can't remap usb registers\n", __func__);
231 clk_put(phy->pad_clk);
238 static void utmip_pad_close(struct tegra_usb_phy *phy)
240 if (phy->instance != 0)
241 iounmap(phy->pad_regs);
242 clk_put(phy->pad_clk);
245 static void utmip_pad_power_on(struct tegra_usb_phy *phy)
247 unsigned long val, flags;
248 void __iomem *base = phy->pad_regs;
250 clk_enable(phy->pad_clk);
252 spin_lock_irqsave(&utmip_pad_lock, flags);
254 if (utmip_pad_count++ == 0) {
255 val = readl(base + UTMIP_BIAS_CFG0);
256 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
257 writel(val, base + UTMIP_BIAS_CFG0);
260 spin_unlock_irqrestore(&utmip_pad_lock, flags);
262 clk_disable(phy->pad_clk);
265 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
267 unsigned long val, flags;
268 void __iomem *base = phy->pad_regs;
270 if (!utmip_pad_count) {
271 pr_err("%s: utmip pad already powered off\n", __func__);
275 clk_enable(phy->pad_clk);
277 spin_lock_irqsave(&utmip_pad_lock, flags);
279 if (--utmip_pad_count == 0) {
280 val = readl(base + UTMIP_BIAS_CFG0);
281 val |= UTMIP_OTGPD | UTMIP_BIASPD;
282 writel(val, base + UTMIP_BIAS_CFG0);
285 spin_unlock_irqrestore(&utmip_pad_lock, flags);
287 clk_disable(phy->pad_clk);
292 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
294 unsigned long timeout = 2000;
296 if ((readl(reg) & mask) == result)
304 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
307 void __iomem *base = phy->regs;
309 if (phy->instance == 0) {
310 val = readl(base + USB_SUSP_CTRL);
312 writel(val, base + USB_SUSP_CTRL);
316 val = readl(base + USB_SUSP_CTRL);
317 val &= ~USB_SUSP_SET;
318 writel(val, base + USB_SUSP_CTRL);
321 if (phy->instance == 2) {
322 val = readl(base + USB_PORTSC1);
323 val |= USB_PORTSC1_PHCD;
324 writel(val, base + USB_PORTSC1);
327 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
328 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
331 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
334 void __iomem *base = phy->regs;
336 if (phy->instance == 0) {
337 val = readl(base + USB_SUSP_CTRL);
339 writel(val, base + USB_SUSP_CTRL);
343 val = readl(base + USB_SUSP_CTRL);
344 val &= ~USB_SUSP_CLR;
345 writel(val, base + USB_SUSP_CTRL);
348 if (phy->instance == 2) {
349 val = readl(base + USB_PORTSC1);
350 val &= ~USB_PORTSC1_PHCD;
351 writel(val, base + USB_PORTSC1);
354 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
356 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
359 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
362 void __iomem *base = phy->regs;
363 struct tegra_utmip_config *config = phy->config;
365 val = readl(base + USB_SUSP_CTRL);
367 writel(val, base + USB_SUSP_CTRL);
369 if (phy->instance == 0) {
370 val = readl(base + USB1_LEGACY_CTRL);
371 val |= USB1_NO_LEGACY_MODE;
372 writel(val, base + USB1_LEGACY_CTRL);
375 val = readl(base + UTMIP_TX_CFG0);
376 val &= ~UTMIP_FS_PREABMLE_J;
377 writel(val, base + UTMIP_TX_CFG0);
379 val = readl(base + UTMIP_HSRX_CFG0);
380 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
381 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
382 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
383 writel(val, base + UTMIP_HSRX_CFG0);
385 val = readl(base + UTMIP_HSRX_CFG1);
386 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
387 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
388 writel(val, base + UTMIP_HSRX_CFG1);
390 val = readl(base + UTMIP_DEBOUNCE_CFG0);
391 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
392 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
393 writel(val, base + UTMIP_DEBOUNCE_CFG0);
395 val = readl(base + UTMIP_MISC_CFG0);
396 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
397 writel(val, base + UTMIP_MISC_CFG0);
399 val = readl(base + UTMIP_MISC_CFG1);
400 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
401 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
402 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
403 writel(val, base + UTMIP_MISC_CFG1);
405 val = readl(base + UTMIP_PLL_CFG1);
406 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
407 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
408 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
409 writel(val, base + UTMIP_PLL_CFG1);
411 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
412 val = readl(base + USB_SUSP_CTRL);
413 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
414 writel(val, base + USB_SUSP_CTRL);
417 utmip_pad_power_on(phy);
419 val = readl(base + UTMIP_XCVR_CFG0);
420 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
421 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) |
422 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) |
423 UTMIP_XCVR_HSSLEW_MSB(~0));
424 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
425 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
426 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
427 writel(val, base + UTMIP_XCVR_CFG0);
429 val = readl(base + UTMIP_XCVR_CFG1);
430 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
431 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
432 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
433 writel(val, base + UTMIP_XCVR_CFG1);
435 val = readl(base + UTMIP_BAT_CHRG_CFG0);
436 val &= ~UTMIP_PD_CHRG;
437 writel(val, base + UTMIP_BAT_CHRG_CFG0);
439 val = readl(base + UTMIP_BIAS_CFG1);
440 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
441 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
442 writel(val, base + UTMIP_BIAS_CFG1);
444 if (phy->instance == 0) {
445 val = readl(base + UTMIP_SPARE_CFG0);
446 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE)
447 val &= ~FUSE_SETUP_SEL;
449 val |= FUSE_SETUP_SEL;
450 writel(val, base + UTMIP_SPARE_CFG0);
453 if (phy->instance == 2) {
454 val = readl(base + USB_SUSP_CTRL);
455 val |= UTMIP_PHY_ENABLE;
456 writel(val, base + USB_SUSP_CTRL);
459 val = readl(base + USB_SUSP_CTRL);
461 writel(val, base + USB_SUSP_CTRL);
463 if (phy->instance == 0) {
464 val = readl(base + USB1_LEGACY_CTRL);
465 val &= ~USB1_VBUS_SENSE_CTL_MASK;
466 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
467 writel(val, base + USB1_LEGACY_CTRL);
469 val = readl(base + USB_SUSP_CTRL);
470 val &= ~USB_SUSP_SET;
471 writel(val, base + USB_SUSP_CTRL);
474 utmi_phy_clk_enable(phy);
476 if (phy->instance == 2) {
477 val = readl(base + USB_PORTSC1);
478 val &= ~USB_PORTSC1_PTS(~0);
479 writel(val, base + USB_PORTSC1);
485 static void utmi_phy_power_off(struct tegra_usb_phy *phy)
488 void __iomem *base = phy->regs;
490 utmi_phy_clk_disable(phy);
492 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
493 val = readl(base + USB_SUSP_CTRL);
494 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
495 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
496 writel(val, base + USB_SUSP_CTRL);
499 val = readl(base + USB_SUSP_CTRL);
501 writel(val, base + USB_SUSP_CTRL);
503 val = readl(base + UTMIP_BAT_CHRG_CFG0);
504 val |= UTMIP_PD_CHRG;
505 writel(val, base + UTMIP_BAT_CHRG_CFG0);
507 val = readl(base + UTMIP_XCVR_CFG0);
508 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
509 UTMIP_FORCE_PDZI_POWERDOWN;
510 writel(val, base + UTMIP_XCVR_CFG0);
512 val = readl(base + UTMIP_XCVR_CFG1);
513 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
514 UTMIP_FORCE_PDDR_POWERDOWN;
515 writel(val, base + UTMIP_XCVR_CFG1);
517 utmip_pad_power_off(phy);
520 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
523 void __iomem *base = phy->regs;
525 val = readl(base + UTMIP_TX_CFG0);
526 val |= UTMIP_HS_DISCON_DISABLE;
527 writel(val, base + UTMIP_TX_CFG0);
530 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
533 void __iomem *base = phy->regs;
535 val = readl(base + UTMIP_TX_CFG0);
536 val &= ~UTMIP_HS_DISCON_DISABLE;
537 writel(val, base + UTMIP_TX_CFG0);
540 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
541 enum tegra_usb_phy_port_speed port_speed)
544 void __iomem *base = phy->regs;
546 val = readl(base + UTMIP_MISC_CFG0);
547 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
548 if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
549 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
551 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
552 writel(val, base + UTMIP_MISC_CFG0);
555 val = readl(base + UTMIP_MISC_CFG0);
556 val |= UTMIP_DPDM_OBSERVE;
557 writel(val, base + UTMIP_MISC_CFG0);
561 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
564 void __iomem *base = phy->regs;
566 val = readl(base + UTMIP_MISC_CFG0);
567 val &= ~UTMIP_DPDM_OBSERVE;
568 writel(val, base + UTMIP_MISC_CFG0);
572 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
576 void __iomem *base = phy->regs;
577 struct tegra_ulpi_config *config = phy->config;
579 gpio_direction_output(config->reset_gpio, 0);
581 gpio_direction_output(config->reset_gpio, 1);
583 clk_enable(phy->clk);
586 val = readl(base + USB_SUSP_CTRL);
588 writel(val, base + USB_SUSP_CTRL);
590 val = readl(base + ULPI_TIMING_CTRL_0);
591 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
592 writel(val, base + ULPI_TIMING_CTRL_0);
594 val = readl(base + USB_SUSP_CTRL);
595 val |= ULPI_PHY_ENABLE;
596 writel(val, base + USB_SUSP_CTRL);
599 writel(val, base + ULPI_TIMING_CTRL_1);
601 val |= ULPI_DATA_TRIMMER_SEL(4);
602 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
603 val |= ULPI_DIR_TRIMMER_SEL(4);
604 writel(val, base + ULPI_TIMING_CTRL_1);
607 val |= ULPI_DATA_TRIMMER_LOAD;
608 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
609 val |= ULPI_DIR_TRIMMER_LOAD;
610 writel(val, base + ULPI_TIMING_CTRL_1);
612 /* Fix VbusInvalid due to floating VBUS */
613 ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
615 pr_err("%s: ulpi write failed\n", __func__);
619 ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
621 pr_err("%s: ulpi write failed\n", __func__);
625 val = readl(base + USB_PORTSC1);
626 val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
627 writel(val, base + USB_PORTSC1);
629 val = readl(base + USB_SUSP_CTRL);
631 writel(val, base + USB_SUSP_CTRL);
634 val = readl(base + USB_SUSP_CTRL);
635 val &= ~USB_SUSP_CLR;
636 writel(val, base + USB_SUSP_CTRL);
641 static void ulpi_phy_power_off(struct tegra_usb_phy *phy)
644 void __iomem *base = phy->regs;
645 struct tegra_ulpi_config *config = phy->config;
647 /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
648 * Controller to immediately bring the ULPI PHY out of low power
650 val = readl(base + USB_PORTSC1);
651 val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
652 writel(val, base + USB_PORTSC1);
654 gpio_direction_output(config->reset_gpio, 0);
655 clk_disable(phy->clk);
658 struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
659 void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode)
661 struct tegra_usb_phy *phy;
662 struct tegra_ulpi_config *ulpi_config;
663 unsigned long parent_rate;
667 phy = kmalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
669 return ERR_PTR(-ENOMEM);
671 phy->instance = instance;
673 phy->config = config;
674 phy->mode = phy_mode;
677 if (phy_is_ulpi(phy)) {
678 pr_err("%s: ulpi phy configuration missing", __func__);
682 phy->config = &utmip_default[instance];
686 phy->pll_u = clk_get_sys(NULL, "pll_u");
687 if (IS_ERR(phy->pll_u)) {
688 pr_err("Can't get pll_u clock\n");
689 err = PTR_ERR(phy->pll_u);
692 clk_enable(phy->pll_u);
694 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
695 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
696 if (tegra_freq_table[i].freq == parent_rate) {
697 phy->freq = &tegra_freq_table[i];
702 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
707 if (phy_is_ulpi(phy)) {
708 ulpi_config = config;
709 phy->clk = clk_get_sys(NULL, ulpi_config->clk);
710 if (IS_ERR(phy->clk)) {
711 pr_err("%s: can't get ulpi clock\n", __func__);
715 if (!gpio_is_valid(ulpi_config->reset_gpio))
716 ulpi_config->reset_gpio =
717 of_get_named_gpio(dev->of_node,
718 "nvidia,phy-reset-gpio", 0);
719 if (!gpio_is_valid(ulpi_config->reset_gpio)) {
720 pr_err("%s: invalid reset gpio: %d\n", __func__,
721 ulpi_config->reset_gpio);
725 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
726 gpio_direction_output(ulpi_config->reset_gpio, 0);
727 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
728 phy->ulpi->io_priv = regs + ULPI_VIEWPORT;
730 err = utmip_pad_open(phy);
738 clk_disable(phy->pll_u);
744 EXPORT_SYMBOL_GPL(tegra_usb_phy_open);
746 int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
748 if (phy_is_ulpi(phy))
749 return ulpi_phy_power_on(phy);
751 return utmi_phy_power_on(phy);
753 EXPORT_SYMBOL_GPL(tegra_usb_phy_power_on);
755 void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
757 if (phy_is_ulpi(phy))
758 ulpi_phy_power_off(phy);
760 utmi_phy_power_off(phy);
762 EXPORT_SYMBOL_GPL(tegra_usb_phy_power_off);
764 void tegra_usb_phy_preresume(struct tegra_usb_phy *phy)
766 if (!phy_is_ulpi(phy))
767 utmi_phy_preresume(phy);
769 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
771 void tegra_usb_phy_postresume(struct tegra_usb_phy *phy)
773 if (!phy_is_ulpi(phy))
774 utmi_phy_postresume(phy);
776 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
778 void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
779 enum tegra_usb_phy_port_speed port_speed)
781 if (!phy_is_ulpi(phy))
782 utmi_phy_restore_start(phy, port_speed);
784 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
786 void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
788 if (!phy_is_ulpi(phy))
789 utmi_phy_restore_end(phy);
791 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
793 void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
795 if (!phy_is_ulpi(phy))
796 utmi_phy_clk_disable(phy);
798 EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_disable);
800 void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
802 if (!phy_is_ulpi(phy))
803 utmi_phy_clk_enable(phy);
805 EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_enable);
807 void tegra_usb_phy_close(struct tegra_usb_phy *phy)
809 if (phy_is_ulpi(phy))
812 utmip_pad_close(phy);
813 clk_disable(phy->pll_u);
817 EXPORT_SYMBOL_GPL(tegra_usb_phy_close);