arch/arm/mach-u300/core.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/core.c
   4  *
   5  *
   6  * Copyright (C) 2007-2012 ST-Ericsson SA
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Core platform support, IRQ handling and device definitions.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/bitops.h>
  16 #include <linux/device.h>
  17 #include <linux/mm.h>
  18 #include <linux/termios.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/amba/mmci.h>
  22 #include <linux/amba/serial.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/gpio.h>
  25 #include <linux/clk.h>
  26 #include <linux/err.h>
  27 #include <linux/mtd/nand.h>
  28 #include <linux/mtd/fsmc.h>
  29 #include <linux/pinctrl/machine.h>
  30 #include <linux/pinctrl/pinconf-generic.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/platform_data/clk-u300.h>
  33 #include <linux/platform_data/pinctrl-coh901.h>
  34
  35 #include <asm/types.h>
  36 #include <asm/setup.h>
  37 #include <asm/memory.h>
  38 #include <asm/hardware/vic.h>
  39 #include <asm/mach/map.h>
  40 #include <asm/mach-types.h>
  41 #include <asm/mach/arch.h>
  42
  43 #include <mach/coh901318.h>
  44 #include <mach/hardware.h>
  45 #include <mach/syscon.h>
  46 #include <mach/irqs.h>
  47
  48 #include "timer.h"
  49 #include "spi.h"
  50 #include "i2c.h"
  51 #include "u300-gpio.h"
  52 #include "dma_channels.h"
  53
  54 /*
  55  * Static I/O mappings that are needed for booting the U300 platforms. The
  56  * only things we need are the areas where we find the timer, syscon and
  57  * intcon, since the remaining device drivers will map their own memory
  58  * physical to virtual as the need arise.
  59  */
  60 static struct map_desc u300_io_desc[] __initdata = {
  61         {
  62                 .virtual        = U300_SLOW_PER_VIRT_BASE,
  63                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
  64                 .length         = SZ_64K,
  65                 .type           = MT_DEVICE,
  66         },
  67         {
  68                 .virtual        = U300_AHB_PER_VIRT_BASE,
  69                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
  70                 .length         = SZ_32K,
  71                 .type           = MT_DEVICE,
  72         },
  73         {
  74                 .virtual        = U300_FAST_PER_VIRT_BASE,
  75                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
  76                 .length         = SZ_32K,
  77                 .type           = MT_DEVICE,
  78         },
  79 };
  80
  81 static void __init u300_map_io(void)
  82 {
  83         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
  84 }
  85
  86 /*
  87  * Declaration of devices found on the U300 board and
  88  * their respective memory locations.
  89  */
  90
  91 static struct amba_pl011_data uart0_plat_data = {
  92 #ifdef CONFIG_COH901318
  93         .dma_filter = coh901318_filter_id,
  94         .dma_rx_param = (void *) U300_DMA_UART0_RX,
  95         .dma_tx_param = (void *) U300_DMA_UART0_TX,
  96 #endif
  97 };
  98
  99 /* Slow device at 0x3000 offset */
 100 static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
 101         { IRQ_U300_UART0 }, &uart0_plat_data);
 102
 103 /* The U335 have an additional UART1 on the APP CPU */
 104 static struct amba_pl011_data uart1_plat_data = {
 105 #ifdef CONFIG_COH901318
 106         .dma_filter = coh901318_filter_id,
 107         .dma_rx_param = (void *) U300_DMA_UART1_RX,
 108         .dma_tx_param = (void *) U300_DMA_UART1_TX,
 109 #endif
 110 };
 111
 112 /* Fast device at 0x7000 offset */
 113 static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
 114         { IRQ_U300_UART1 }, &uart1_plat_data);
 115
 116 /* AHB device at 0x4000 offset */
 117 static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
 118
 119 /* Fast device at 0x6000 offset */
 120 static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
 121         { IRQ_U300_SPI }, NULL);
 122
 123 /* Fast device at 0x1000 offset */
 124 #define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
 125
 126 static struct mmci_platform_data mmcsd_platform_data = {
 127         /*
 128          * Do not set ocr_mask or voltage translation function,
 129          * we have a regulator we can control instead.
 130          */
 131         .f_max = 24000000,
 132         .gpio_wp = -1,
 133         .gpio_cd = U300_GPIO_PIN_MMC_CD,
 134         .cd_invert = true,
 135         .capabilities = MMC_CAP_MMC_HIGHSPEED |
 136         MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
 137 #ifdef CONFIG_COH901318
 138         .dma_filter = coh901318_filter_id,
 139         .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
 140         /* Don't specify a TX channel, this RX channel is bidirectional */
 141 #endif
 142 };
 143
 144 static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
 145         U300_MMCSD_IRQS, &mmcsd_platform_data);
 146
 147 /*
 148  * The order of device declaration may be important, since some devices
 149  * have dependencies on other devices being initialized first.
 150  */
 151 static struct amba_device *amba_devs[] __initdata = {
 152         &uart0_device,
 153         &uart1_device,
 154         &pl022_device,
 155         &pl172_device,
 156         &mmcsd_device,
 157 };
 158
 159 /* Here follows a list of all hw resources that the platform devices
 160  * allocate. Note, clock dependencies are not included
 161  */
 162
 163 static struct resource gpio_resources[] = {
 164         {
 165                 .start = U300_GPIO_BASE,
 166                 .end   = (U300_GPIO_BASE + SZ_4K - 1),
 167                 .flags = IORESOURCE_MEM,
 168         },
 169         {
 170                 .name  = "gpio0",
 171                 .start = IRQ_U300_GPIO_PORT0,
 172                 .end   = IRQ_U300_GPIO_PORT0,
 173                 .flags = IORESOURCE_IRQ,
 174         },
 175         {
 176                 .name  = "gpio1",
 177                 .start = IRQ_U300_GPIO_PORT1,
 178                 .end   = IRQ_U300_GPIO_PORT1,
 179                 .flags = IORESOURCE_IRQ,
 180         },
 181         {
 182                 .name  = "gpio2",
 183                 .start = IRQ_U300_GPIO_PORT2,
 184                 .end   = IRQ_U300_GPIO_PORT2,
 185                 .flags = IORESOURCE_IRQ,
 186         },
 187         {
 188                 .name  = "gpio3",
 189                 .start = IRQ_U300_GPIO_PORT3,
 190                 .end   = IRQ_U300_GPIO_PORT3,
 191                 .flags = IORESOURCE_IRQ,
 192         },
 193         {
 194                 .name  = "gpio4",
 195                 .start = IRQ_U300_GPIO_PORT4,
 196                 .end   = IRQ_U300_GPIO_PORT4,
 197                 .flags = IORESOURCE_IRQ,
 198         },
 199         {
 200                 .name  = "gpio5",
 201                 .start = IRQ_U300_GPIO_PORT5,
 202                 .end   = IRQ_U300_GPIO_PORT5,
 203                 .flags = IORESOURCE_IRQ,
 204         },
 205         {
 206                 .name  = "gpio6",
 207                 .start = IRQ_U300_GPIO_PORT6,
 208                 .end   = IRQ_U300_GPIO_PORT6,
 209                 .flags = IORESOURCE_IRQ,
 210         },
 211 };
 212
 213 static struct resource keypad_resources[] = {
 214         {
 215                 .start = U300_KEYPAD_BASE,
 216                 .end   = U300_KEYPAD_BASE + SZ_4K - 1,
 217                 .flags = IORESOURCE_MEM,
 218         },
 219         {
 220                 .name  = "coh901461-press",
 221                 .start = IRQ_U300_KEYPAD_KEYBF,
 222                 .end   = IRQ_U300_KEYPAD_KEYBF,
 223                 .flags = IORESOURCE_IRQ,
 224         },
 225         {
 226                 .name  = "coh901461-release",
 227                 .start = IRQ_U300_KEYPAD_KEYBR,
 228                 .end   = IRQ_U300_KEYPAD_KEYBR,
 229                 .flags = IORESOURCE_IRQ,
 230         },
 231 };
 232
 233 static struct resource rtc_resources[] = {
 234         {
 235                 .start = U300_RTC_BASE,
 236                 .end   = U300_RTC_BASE + SZ_4K - 1,
 237                 .flags = IORESOURCE_MEM,
 238         },
 239         {
 240                 .start = IRQ_U300_RTC,
 241                 .end   = IRQ_U300_RTC,
 242                 .flags = IORESOURCE_IRQ,
 243         },
 244 };
 245
 246 /*
 247  * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
 248  * but these are not yet used by the driver.
 249  */
 250 static struct resource fsmc_resources[] = {
 251         {
 252                 .name  = "nand_data",
 253                 .start = U300_NAND_CS0_PHYS_BASE,
 254                 .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
 255                 .flags = IORESOURCE_MEM,
 256         },
 257         {
 258                 .name  = "fsmc_regs",
 259                 .start = U300_NAND_IF_PHYS_BASE,
 260                 .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
 261                 .flags = IORESOURCE_MEM,
 262         },
 263 };
 264
 265 static struct resource i2c0_resources[] = {
 266         {
 267                 .start = U300_I2C0_BASE,
 268                 .end   = U300_I2C0_BASE + SZ_4K - 1,
 269                 .flags = IORESOURCE_MEM,
 270         },
 271         {
 272                 .start = IRQ_U300_I2C0,
 273                 .end   = IRQ_U300_I2C0,
 274                 .flags = IORESOURCE_IRQ,
 275         },
 276 };
 277
 278 static struct resource i2c1_resources[] = {
 279         {
 280                 .start = U300_I2C1_BASE,
 281                 .end   = U300_I2C1_BASE + SZ_4K - 1,
 282                 .flags = IORESOURCE_MEM,
 283         },
 284         {
 285                 .start = IRQ_U300_I2C1,
 286                 .end   = IRQ_U300_I2C1,
 287                 .flags = IORESOURCE_IRQ,
 288         },
 289
 290 };
 291
 292 static struct resource wdog_resources[] = {
 293         {
 294                 .start = U300_WDOG_BASE,
 295                 .end   = U300_WDOG_BASE + SZ_4K - 1,
 296                 .flags = IORESOURCE_MEM,
 297         },
 298         {
 299                 .start = IRQ_U300_WDOG,
 300                 .end   = IRQ_U300_WDOG,
 301                 .flags = IORESOURCE_IRQ,
 302         }
 303 };
 304
 305 static struct resource dma_resource[] = {
 306         {
 307                 .start = U300_DMAC_BASE,
 308                 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
 309                 .flags =  IORESOURCE_MEM,
 310         },
 311         {
 312                 .start = IRQ_U300_DMA,
 313                 .end = IRQ_U300_DMA,
 314                 .flags =  IORESOURCE_IRQ,
 315         }
 316 };
 317
 318 /* points out all dma slave channels.
 319  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 320  * Select all channels from A to B, end of list is marked with -1,-1
 321  */
 322 static int dma_slave_channels[] = {
 323         U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
 324         U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
 325
 326 /* points out all dma memcpy channels. */
 327 static int dma_memcpy_channels[] = {
 328         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 329
 330 /** register dma for memory access
 331  *
 332  * active  1 means dma intends to access memory
 333  *         0 means dma wont access memory
 334  */
 335 static void coh901318_access_memory_state(struct device *dev, bool active)
 336 {
 337 }
 338
 339 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
 340                         COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
 341                         COH901318_CX_CFG_LCR_DISABLE | \
 342                         COH901318_CX_CFG_TC_IRQ_ENABLE | \
 343                         COH901318_CX_CFG_BE_IRQ_ENABLE)
 344 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
 345                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 346                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 347                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 348                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 349                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 350                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 351                         COH901318_CX_CTRL_TCP_DISABLE | \
 352                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 353                         COH901318_CX_CTRL_HSP_DISABLE | \
 354                         COH901318_CX_CTRL_HSS_DISABLE | \
 355                         COH901318_CX_CTRL_DDMA_LEGACY | \
 356                         COH901318_CX_CTRL_PRDD_SOURCE)
 357 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
 358                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 359                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 360                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 361                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 362                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 363                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 364                         COH901318_CX_CTRL_TCP_DISABLE | \
 365                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 366                         COH901318_CX_CTRL_HSP_DISABLE | \
 367                         COH901318_CX_CTRL_HSS_DISABLE | \
 368                         COH901318_CX_CTRL_DDMA_LEGACY | \
 369                         COH901318_CX_CTRL_PRDD_SOURCE)
 370 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
 371                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 372                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 373                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 374                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 375                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 376                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 377                         COH901318_CX_CTRL_TCP_DISABLE | \
 378                         COH901318_CX_CTRL_TC_IRQ_ENABLE | \
 379                         COH901318_CX_CTRL_HSP_DISABLE | \
 380                         COH901318_CX_CTRL_HSS_DISABLE | \
 381                         COH901318_CX_CTRL_DDMA_LEGACY | \
 382                         COH901318_CX_CTRL_PRDD_SOURCE)
 383
 384 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 385         {
 386                 .number = U300_DMA_MSL_TX_0,
 387                 .name = "MSL TX 0",
 388                 .priority_high = 0,
 389                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
 390         },
 391         {
 392                 .number = U300_DMA_MSL_TX_1,
 393                 .name = "MSL TX 1",
 394                 .priority_high = 0,
 395                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
 396                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 397                                 COH901318_CX_CFG_LCR_DISABLE |
 398                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 399                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 400                 .param.ctrl_lli_chained = 0 |
 401                                 COH901318_CX_CTRL_TC_ENABLE |
 402                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 403                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 404                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 405                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 406                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 407                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 408                                 COH901318_CX_CTRL_TCP_DISABLE |
 409                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 410                                 COH901318_CX_CTRL_HSP_ENABLE |
 411                                 COH901318_CX_CTRL_HSS_DISABLE |
 412                                 COH901318_CX_CTRL_DDMA_LEGACY |
 413                                 COH901318_CX_CTRL_PRDD_SOURCE,
 414                 .param.ctrl_lli = 0 |
 415                                 COH901318_CX_CTRL_TC_ENABLE |
 416                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 417                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 418                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 419                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 420                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 421                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 422                                 COH901318_CX_CTRL_TCP_ENABLE |
 423                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 424                                 COH901318_CX_CTRL_HSP_ENABLE |
 425                                 COH901318_CX_CTRL_HSS_DISABLE |
 426                                 COH901318_CX_CTRL_DDMA_LEGACY |
 427                                 COH901318_CX_CTRL_PRDD_SOURCE,
 428                 .param.ctrl_lli_last = 0 |
 429                                 COH901318_CX_CTRL_TC_ENABLE |
 430                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 431                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 432                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 433                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 434                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 435                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 436                                 COH901318_CX_CTRL_TCP_ENABLE |
 437                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 438                                 COH901318_CX_CTRL_HSP_ENABLE |
 439                                 COH901318_CX_CTRL_HSS_DISABLE |
 440                                 COH901318_CX_CTRL_DDMA_LEGACY |
 441                                 COH901318_CX_CTRL_PRDD_SOURCE,
 442         },
 443         {
 444                 .number = U300_DMA_MSL_TX_2,
 445                 .name = "MSL TX 2",
 446                 .priority_high = 0,
 447                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
 448                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 449                                 COH901318_CX_CFG_LCR_DISABLE |
 450                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 451                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 452                 .param.ctrl_lli_chained = 0 |
 453                                 COH901318_CX_CTRL_TC_ENABLE |
 454                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 455                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 456                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 457                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 458                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 459                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 460                                 COH901318_CX_CTRL_TCP_DISABLE |
 461                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 462                                 COH901318_CX_CTRL_HSP_ENABLE |
 463                                 COH901318_CX_CTRL_HSS_DISABLE |
 464                                 COH901318_CX_CTRL_DDMA_LEGACY |
 465                                 COH901318_CX_CTRL_PRDD_SOURCE,
 466                 .param.ctrl_lli = 0 |
 467                                 COH901318_CX_CTRL_TC_ENABLE |
 468                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 469                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 470                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 471                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 472                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 473                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 474                                 COH901318_CX_CTRL_TCP_ENABLE |
 475                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 476                                 COH901318_CX_CTRL_HSP_ENABLE |
 477                                 COH901318_CX_CTRL_HSS_DISABLE |
 478                                 COH901318_CX_CTRL_DDMA_LEGACY |
 479                                 COH901318_CX_CTRL_PRDD_SOURCE,
 480                 .param.ctrl_lli_last = 0 |
 481                                 COH901318_CX_CTRL_TC_ENABLE |
 482                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 483                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 484                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 485                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 486                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 487                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 488                                 COH901318_CX_CTRL_TCP_ENABLE |
 489                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 490                                 COH901318_CX_CTRL_HSP_ENABLE |
 491                                 COH901318_CX_CTRL_HSS_DISABLE |
 492                                 COH901318_CX_CTRL_DDMA_LEGACY |
 493                                 COH901318_CX_CTRL_PRDD_SOURCE,
 494                 .desc_nbr_max = 10,
 495         },
 496         {
 497                 .number = U300_DMA_MSL_TX_3,
 498                 .name = "MSL TX 3",
 499                 .priority_high = 0,
 500                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
 501                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 502                                 COH901318_CX_CFG_LCR_DISABLE |
 503                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 504                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 505                 .param.ctrl_lli_chained = 0 |
 506                                 COH901318_CX_CTRL_TC_ENABLE |
 507                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 508                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 509                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 510                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 511                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 512                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 513                                 COH901318_CX_CTRL_TCP_DISABLE |
 514                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 515                                 COH901318_CX_CTRL_HSP_ENABLE |
 516                                 COH901318_CX_CTRL_HSS_DISABLE |
 517                                 COH901318_CX_CTRL_DDMA_LEGACY |
 518                                 COH901318_CX_CTRL_PRDD_SOURCE,
 519                 .param.ctrl_lli = 0 |
 520                                 COH901318_CX_CTRL_TC_ENABLE |
 521                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 522                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 523                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 524                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 525                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 526                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 527                                 COH901318_CX_CTRL_TCP_ENABLE |
 528                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 529                                 COH901318_CX_CTRL_HSP_ENABLE |
 530                                 COH901318_CX_CTRL_HSS_DISABLE |
 531                                 COH901318_CX_CTRL_DDMA_LEGACY |
 532                                 COH901318_CX_CTRL_PRDD_SOURCE,
 533                 .param.ctrl_lli_last = 0 |
 534                                 COH901318_CX_CTRL_TC_ENABLE |
 535                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 536                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 537                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 538                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 539                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 540                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 541                                 COH901318_CX_CTRL_TCP_ENABLE |
 542                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 543                                 COH901318_CX_CTRL_HSP_ENABLE |
 544                                 COH901318_CX_CTRL_HSS_DISABLE |
 545                                 COH901318_CX_CTRL_DDMA_LEGACY |
 546                                 COH901318_CX_CTRL_PRDD_SOURCE,
 547         },
 548         {
 549                 .number = U300_DMA_MSL_TX_4,
 550                 .name = "MSL TX 4",
 551                 .priority_high = 0,
 552                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
 553                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 554                                 COH901318_CX_CFG_LCR_DISABLE |
 555                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 556                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 557                 .param.ctrl_lli_chained = 0 |
 558                                 COH901318_CX_CTRL_TC_ENABLE |
 559                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 560                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 561                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 562                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 563                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 564                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 565                                 COH901318_CX_CTRL_TCP_DISABLE |
 566                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 567                                 COH901318_CX_CTRL_HSP_ENABLE |
 568                                 COH901318_CX_CTRL_HSS_DISABLE |
 569                                 COH901318_CX_CTRL_DDMA_LEGACY |
 570                                 COH901318_CX_CTRL_PRDD_SOURCE,
 571                 .param.ctrl_lli = 0 |
 572                                 COH901318_CX_CTRL_TC_ENABLE |
 573                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 574                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 575                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 576                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 577                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 578                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 579                                 COH901318_CX_CTRL_TCP_ENABLE |
 580                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 581                                 COH901318_CX_CTRL_HSP_ENABLE |
 582                                 COH901318_CX_CTRL_HSS_DISABLE |
 583                                 COH901318_CX_CTRL_DDMA_LEGACY |
 584                                 COH901318_CX_CTRL_PRDD_SOURCE,
 585                 .param.ctrl_lli_last = 0 |
 586                                 COH901318_CX_CTRL_TC_ENABLE |
 587                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 588                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 589                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 590                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 591                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 592                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 593                                 COH901318_CX_CTRL_TCP_ENABLE |
 594                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 595                                 COH901318_CX_CTRL_HSP_ENABLE |
 596                                 COH901318_CX_CTRL_HSS_DISABLE |
 597                                 COH901318_CX_CTRL_DDMA_LEGACY |
 598                                 COH901318_CX_CTRL_PRDD_SOURCE,
 599         },
 600         {
 601                 .number = U300_DMA_MSL_TX_5,
 602                 .name = "MSL TX 5",
 603                 .priority_high = 0,
 604                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
 605         },
 606         {
 607                 .number = U300_DMA_MSL_TX_6,
 608                 .name = "MSL TX 6",
 609                 .priority_high = 0,
 610                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
 611         },
 612         {
 613                 .number = U300_DMA_MSL_RX_0,
 614                 .name = "MSL RX 0",
 615                 .priority_high = 0,
 616                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
 617         },
 618         {
 619                 .number = U300_DMA_MSL_RX_1,
 620                 .name = "MSL RX 1",
 621                 .priority_high = 0,
 622                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
 623                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 624                                 COH901318_CX_CFG_LCR_DISABLE |
 625                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 626                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 627                 .param.ctrl_lli_chained = 0 |
 628                                 COH901318_CX_CTRL_TC_ENABLE |
 629                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 630                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 631                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 632                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 633                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 634                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 635                                 COH901318_CX_CTRL_TCP_DISABLE |
 636                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 637                                 COH901318_CX_CTRL_HSP_ENABLE |
 638                                 COH901318_CX_CTRL_HSS_DISABLE |
 639                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 640                                 COH901318_CX_CTRL_PRDD_DEST,
 641                 .param.ctrl_lli = 0,
 642                 .param.ctrl_lli_last = 0 |
 643                                 COH901318_CX_CTRL_TC_ENABLE |
 644                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 645                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 646                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 647                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 648                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 649                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 650                                 COH901318_CX_CTRL_TCP_DISABLE |
 651                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 652                                 COH901318_CX_CTRL_HSP_ENABLE |
 653                                 COH901318_CX_CTRL_HSS_DISABLE |
 654                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 655                                 COH901318_CX_CTRL_PRDD_DEST,
 656         },
 657         {
 658                 .number = U300_DMA_MSL_RX_2,
 659                 .name = "MSL RX 2",
 660                 .priority_high = 0,
 661                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
 662                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 663                                 COH901318_CX_CFG_LCR_DISABLE |
 664                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 665                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 666                 .param.ctrl_lli_chained = 0 |
 667                                 COH901318_CX_CTRL_TC_ENABLE |
 668                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 669                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 670                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 671                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 672                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 673                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 674                                 COH901318_CX_CTRL_TCP_DISABLE |
 675                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 676                                 COH901318_CX_CTRL_HSP_ENABLE |
 677                                 COH901318_CX_CTRL_HSS_DISABLE |
 678                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 679                                 COH901318_CX_CTRL_PRDD_DEST,
 680                 .param.ctrl_lli = 0 |
 681                                 COH901318_CX_CTRL_TC_ENABLE |
 682                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 683                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 684                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 685                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 686                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 687                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 688                                 COH901318_CX_CTRL_TCP_DISABLE |
 689                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 690                                 COH901318_CX_CTRL_HSP_ENABLE |
 691                                 COH901318_CX_CTRL_HSS_DISABLE |
 692                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 693                                 COH901318_CX_CTRL_PRDD_DEST,
 694                 .param.ctrl_lli_last = 0 |
 695                                 COH901318_CX_CTRL_TC_ENABLE |
 696                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 697                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 698                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 699                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 700                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 701                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 702                                 COH901318_CX_CTRL_TCP_DISABLE |
 703                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 704                                 COH901318_CX_CTRL_HSP_ENABLE |
 705                                 COH901318_CX_CTRL_HSS_DISABLE |
 706                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 707                                 COH901318_CX_CTRL_PRDD_DEST,
 708         },
 709         {
 710                 .number = U300_DMA_MSL_RX_3,
 711                 .name = "MSL RX 3",
 712                 .priority_high = 0,
 713                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
 714                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 715                                 COH901318_CX_CFG_LCR_DISABLE |
 716                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 717                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 718                 .param.ctrl_lli_chained = 0 |
 719                                 COH901318_CX_CTRL_TC_ENABLE |
 720                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 721                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 722                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 723                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 724                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 725                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 726                                 COH901318_CX_CTRL_TCP_DISABLE |
 727                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 728                                 COH901318_CX_CTRL_HSP_ENABLE |
 729                                 COH901318_CX_CTRL_HSS_DISABLE |
 730                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 731                                 COH901318_CX_CTRL_PRDD_DEST,
 732                 .param.ctrl_lli = 0 |
 733                                 COH901318_CX_CTRL_TC_ENABLE |
 734                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 735                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 736                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 737                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 738                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 739                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 740                                 COH901318_CX_CTRL_TCP_DISABLE |
 741                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 742                                 COH901318_CX_CTRL_HSP_ENABLE |
 743                                 COH901318_CX_CTRL_HSS_DISABLE |
 744                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 745                                 COH901318_CX_CTRL_PRDD_DEST,
 746                 .param.ctrl_lli_last = 0 |
 747                                 COH901318_CX_CTRL_TC_ENABLE |
 748                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 749                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 750                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 751                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 752                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 753                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 754                                 COH901318_CX_CTRL_TCP_DISABLE |
 755                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 756                                 COH901318_CX_CTRL_HSP_ENABLE |
 757                                 COH901318_CX_CTRL_HSS_DISABLE |
 758                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 759                                 COH901318_CX_CTRL_PRDD_DEST,
 760         },
 761         {
 762                 .number = U300_DMA_MSL_RX_4,
 763                 .name = "MSL RX 4",
 764                 .priority_high = 0,
 765                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
 766                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 767                                 COH901318_CX_CFG_LCR_DISABLE |
 768                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 769                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 770                 .param.ctrl_lli_chained = 0 |
 771                                 COH901318_CX_CTRL_TC_ENABLE |
 772                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 773                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 774                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 775                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 776                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 777                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 778                                 COH901318_CX_CTRL_TCP_DISABLE |
 779                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 780                                 COH901318_CX_CTRL_HSP_ENABLE |
 781                                 COH901318_CX_CTRL_HSS_DISABLE |
 782                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 783                                 COH901318_CX_CTRL_PRDD_DEST,
 784                 .param.ctrl_lli = 0 |
 785                                 COH901318_CX_CTRL_TC_ENABLE |
 786                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 787                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 788                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 789                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 790                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 791                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 792                                 COH901318_CX_CTRL_TCP_DISABLE |
 793                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 794                                 COH901318_CX_CTRL_HSP_ENABLE |
 795                                 COH901318_CX_CTRL_HSS_DISABLE |
 796                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 797                                 COH901318_CX_CTRL_PRDD_DEST,
 798                 .param.ctrl_lli_last = 0 |
 799                                 COH901318_CX_CTRL_TC_ENABLE |
 800                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 801                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 802                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 803                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 804                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 805                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 806                                 COH901318_CX_CTRL_TCP_DISABLE |
 807                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 808                                 COH901318_CX_CTRL_HSP_ENABLE |
 809                                 COH901318_CX_CTRL_HSS_DISABLE |
 810                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 811                                 COH901318_CX_CTRL_PRDD_DEST,
 812         },
 813         {
 814                 .number = U300_DMA_MSL_RX_5,
 815                 .name = "MSL RX 5",
 816                 .priority_high = 0,
 817                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
 818                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 819                                 COH901318_CX_CFG_LCR_DISABLE |
 820                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 821                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 822                 .param.ctrl_lli_chained = 0 |
 823                                 COH901318_CX_CTRL_TC_ENABLE |
 824                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 825                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 826                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 827                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 828                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 829                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 830                                 COH901318_CX_CTRL_TCP_DISABLE |
 831                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 832                                 COH901318_CX_CTRL_HSP_ENABLE |
 833                                 COH901318_CX_CTRL_HSS_DISABLE |
 834                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 835                                 COH901318_CX_CTRL_PRDD_DEST,
 836                 .param.ctrl_lli = 0 |
 837                                 COH901318_CX_CTRL_TC_ENABLE |
 838                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 839                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 840                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 841                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 842                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 843                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 844                                 COH901318_CX_CTRL_TCP_DISABLE |
 845                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 846                                 COH901318_CX_CTRL_HSP_ENABLE |
 847                                 COH901318_CX_CTRL_HSS_DISABLE |
 848                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 849                                 COH901318_CX_CTRL_PRDD_DEST,
 850                 .param.ctrl_lli_last = 0 |
 851                                 COH901318_CX_CTRL_TC_ENABLE |
 852                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 853                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 854                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 855                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 856                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 857                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 858                                 COH901318_CX_CTRL_TCP_DISABLE |
 859                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 860                                 COH901318_CX_CTRL_HSP_ENABLE |
 861                                 COH901318_CX_CTRL_HSS_DISABLE |
 862                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 863                                 COH901318_CX_CTRL_PRDD_DEST,
 864         },
 865         {
 866                 .number = U300_DMA_MSL_RX_6,
 867                 .name = "MSL RX 6",
 868                 .priority_high = 0,
 869                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
 870         },
 871         /*
 872          * Don't set up device address, burst count or size of src
 873          * or dst bus for this peripheral - handled by PrimeCell
 874          * DMA extension.
 875          */
 876         {
 877                 .number = U300_DMA_MMCSD_RX_TX,
 878                 .name = "MMCSD RX TX",
 879                 .priority_high = 0,
 880                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 881                                 COH901318_CX_CFG_LCR_DISABLE |
 882                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 883                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 884                 .param.ctrl_lli_chained = 0 |
 885                                 COH901318_CX_CTRL_TC_ENABLE |
 886                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 887                                 COH901318_CX_CTRL_TCP_ENABLE |
 888                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 889                                 COH901318_CX_CTRL_HSP_ENABLE |
 890                                 COH901318_CX_CTRL_HSS_DISABLE |
 891                                 COH901318_CX_CTRL_DDMA_LEGACY,
 892                 .param.ctrl_lli = 0 |
 893                                 COH901318_CX_CTRL_TC_ENABLE |
 894                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 895                                 COH901318_CX_CTRL_TCP_ENABLE |
 896                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 897                                 COH901318_CX_CTRL_HSP_ENABLE |
 898                                 COH901318_CX_CTRL_HSS_DISABLE |
 899                                 COH901318_CX_CTRL_DDMA_LEGACY,
 900                 .param.ctrl_lli_last = 0 |
 901                                 COH901318_CX_CTRL_TC_ENABLE |
 902                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 903                                 COH901318_CX_CTRL_TCP_DISABLE |
 904                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 905                                 COH901318_CX_CTRL_HSP_ENABLE |
 906                                 COH901318_CX_CTRL_HSS_DISABLE |
 907                                 COH901318_CX_CTRL_DDMA_LEGACY,
 908
 909         },
 910         {
 911                 .number = U300_DMA_MSPRO_TX,
 912                 .name = "MSPRO TX",
 913                 .priority_high = 0,
 914         },
 915         {
 916                 .number = U300_DMA_MSPRO_RX,
 917                 .name = "MSPRO RX",
 918                 .priority_high = 0,
 919         },
 920         /*
 921          * Don't set up device address, burst count or size of src
 922          * or dst bus for this peripheral - handled by PrimeCell
 923          * DMA extension.
 924          */
 925         {
 926                 .number = U300_DMA_UART0_TX,
 927                 .name = "UART0 TX",
 928                 .priority_high = 0,
 929                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 930                                 COH901318_CX_CFG_LCR_DISABLE |
 931                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 932                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 933                 .param.ctrl_lli_chained = 0 |
 934                                 COH901318_CX_CTRL_TC_ENABLE |
 935                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 936                                 COH901318_CX_CTRL_TCP_ENABLE |
 937                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 938                                 COH901318_CX_CTRL_HSP_ENABLE |
 939                                 COH901318_CX_CTRL_HSS_DISABLE |
 940                                 COH901318_CX_CTRL_DDMA_LEGACY,
 941                 .param.ctrl_lli = 0 |
 942                                 COH901318_CX_CTRL_TC_ENABLE |
 943                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 944                                 COH901318_CX_CTRL_TCP_ENABLE |
 945                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 946                                 COH901318_CX_CTRL_HSP_ENABLE |
 947                                 COH901318_CX_CTRL_HSS_DISABLE |
 948                                 COH901318_CX_CTRL_DDMA_LEGACY,
 949                 .param.ctrl_lli_last = 0 |
 950                                 COH901318_CX_CTRL_TC_ENABLE |
 951                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 952                                 COH901318_CX_CTRL_TCP_ENABLE |
 953                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 954                                 COH901318_CX_CTRL_HSP_ENABLE |
 955                                 COH901318_CX_CTRL_HSS_DISABLE |
 956                                 COH901318_CX_CTRL_DDMA_LEGACY,
 957         },
 958         {
 959                 .number = U300_DMA_UART0_RX,
 960                 .name = "UART0 RX",
 961                 .priority_high = 0,
 962                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 963                                 COH901318_CX_CFG_LCR_DISABLE |
 964                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 965                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 966                 .param.ctrl_lli_chained = 0 |
 967                                 COH901318_CX_CTRL_TC_ENABLE |
 968                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 969                                 COH901318_CX_CTRL_TCP_ENABLE |
 970                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 971                                 COH901318_CX_CTRL_HSP_ENABLE |
 972                                 COH901318_CX_CTRL_HSS_DISABLE |
 973                                 COH901318_CX_CTRL_DDMA_LEGACY,
 974                 .param.ctrl_lli = 0 |
 975                                 COH901318_CX_CTRL_TC_ENABLE |
 976                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 977                                 COH901318_CX_CTRL_TCP_ENABLE |
 978                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 979                                 COH901318_CX_CTRL_HSP_ENABLE |
 980                                 COH901318_CX_CTRL_HSS_DISABLE |
 981                                 COH901318_CX_CTRL_DDMA_LEGACY,
 982                 .param.ctrl_lli_last = 0 |
 983                                 COH901318_CX_CTRL_TC_ENABLE |
 984                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 985                                 COH901318_CX_CTRL_TCP_ENABLE |
 986                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 987                                 COH901318_CX_CTRL_HSP_ENABLE |
 988                                 COH901318_CX_CTRL_HSS_DISABLE |
 989                                 COH901318_CX_CTRL_DDMA_LEGACY,
 990         },
 991         {
 992                 .number = U300_DMA_APEX_TX,
 993                 .name = "APEX TX",
 994                 .priority_high = 0,
 995         },
 996         {
 997                 .number = U300_DMA_APEX_RX,
 998                 .name = "APEX RX",
 999                 .priority_high = 0,
1000         },
1001         {
1002                 .number = U300_DMA_PCM_I2S0_TX,
1003                 .name = "PCM I2S0 TX",
1004                 .priority_high = 1,
1005                 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1006                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1007                                 COH901318_CX_CFG_LCR_DISABLE |
1008                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1009                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1010                 .param.ctrl_lli_chained = 0 |
1011                                 COH901318_CX_CTRL_TC_ENABLE |
1012                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1013                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1014                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1015                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1016                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1017                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1018                                 COH901318_CX_CTRL_TCP_DISABLE |
1019                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1020                                 COH901318_CX_CTRL_HSP_ENABLE |
1021                                 COH901318_CX_CTRL_HSS_DISABLE |
1022                                 COH901318_CX_CTRL_DDMA_LEGACY |
1023                                 COH901318_CX_CTRL_PRDD_SOURCE,
1024                 .param.ctrl_lli = 0 |
1025                                 COH901318_CX_CTRL_TC_ENABLE |
1026                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1027                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1028                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1029                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1030                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1031                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1032                                 COH901318_CX_CTRL_TCP_ENABLE |
1033                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1034                                 COH901318_CX_CTRL_HSP_ENABLE |
1035                                 COH901318_CX_CTRL_HSS_DISABLE |
1036                                 COH901318_CX_CTRL_DDMA_LEGACY |
1037                                 COH901318_CX_CTRL_PRDD_SOURCE,
1038                 .param.ctrl_lli_last = 0 |
1039                                 COH901318_CX_CTRL_TC_ENABLE |
1040                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1041                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1042                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1043                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1044                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1045                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1046                                 COH901318_CX_CTRL_TCP_ENABLE |
1047                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1048                                 COH901318_CX_CTRL_HSP_ENABLE |
1049                                 COH901318_CX_CTRL_HSS_DISABLE |
1050                                 COH901318_CX_CTRL_DDMA_LEGACY |
1051                                 COH901318_CX_CTRL_PRDD_SOURCE,
1052         },
1053         {
1054                 .number = U300_DMA_PCM_I2S0_RX,
1055                 .name = "PCM I2S0 RX",
1056                 .priority_high = 1,
1057                 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1058                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1059                                 COH901318_CX_CFG_LCR_DISABLE |
1060                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1061                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1062                 .param.ctrl_lli_chained = 0 |
1063                                 COH901318_CX_CTRL_TC_ENABLE |
1064                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1065                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1066                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1067                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1068                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1069                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1070                                 COH901318_CX_CTRL_TCP_DISABLE |
1071                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1072                                 COH901318_CX_CTRL_HSP_ENABLE |
1073                                 COH901318_CX_CTRL_HSS_DISABLE |
1074                                 COH901318_CX_CTRL_DDMA_LEGACY |
1075                                 COH901318_CX_CTRL_PRDD_DEST,
1076                 .param.ctrl_lli = 0 |
1077                                 COH901318_CX_CTRL_TC_ENABLE |
1078                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1079                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1080                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1081                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1082                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1083                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1084                                 COH901318_CX_CTRL_TCP_ENABLE |
1085                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1086                                 COH901318_CX_CTRL_HSP_ENABLE |
1087                                 COH901318_CX_CTRL_HSS_DISABLE |
1088                                 COH901318_CX_CTRL_DDMA_LEGACY |
1089                                 COH901318_CX_CTRL_PRDD_DEST,
1090                 .param.ctrl_lli_last = 0 |
1091                                 COH901318_CX_CTRL_TC_ENABLE |
1092                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1093                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1094                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1095                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1096                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1097                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1098                                 COH901318_CX_CTRL_TCP_ENABLE |
1099                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1100                                 COH901318_CX_CTRL_HSP_ENABLE |
1101                                 COH901318_CX_CTRL_HSS_DISABLE |
1102                                 COH901318_CX_CTRL_DDMA_LEGACY |
1103                                 COH901318_CX_CTRL_PRDD_DEST,
1104         },
1105         {
1106                 .number = U300_DMA_PCM_I2S1_TX,
1107                 .name = "PCM I2S1 TX",
1108                 .priority_high = 1,
1109                 .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
1110                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1111                                 COH901318_CX_CFG_LCR_DISABLE |
1112                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1113                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1114                 .param.ctrl_lli_chained = 0 |
1115                                 COH901318_CX_CTRL_TC_ENABLE |
1116                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1117                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1118                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1119                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1120                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1121                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1122                                 COH901318_CX_CTRL_TCP_DISABLE |
1123                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1124                                 COH901318_CX_CTRL_HSP_ENABLE |
1125                                 COH901318_CX_CTRL_HSS_DISABLE |
1126                                 COH901318_CX_CTRL_DDMA_LEGACY |
1127                                 COH901318_CX_CTRL_PRDD_SOURCE,
1128                 .param.ctrl_lli = 0 |
1129                                 COH901318_CX_CTRL_TC_ENABLE |
1130                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1131                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1132                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1133                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1134                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1135                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1136                                 COH901318_CX_CTRL_TCP_ENABLE |
1137                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1138                                 COH901318_CX_CTRL_HSP_ENABLE |
1139                                 COH901318_CX_CTRL_HSS_DISABLE |
1140                                 COH901318_CX_CTRL_DDMA_LEGACY |
1141                                 COH901318_CX_CTRL_PRDD_SOURCE,
1142                 .param.ctrl_lli_last = 0 |
1143                                 COH901318_CX_CTRL_TC_ENABLE |
1144                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1145                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1146                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1147                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1148                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1149                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1150                                 COH901318_CX_CTRL_TCP_ENABLE |
1151                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1152                                 COH901318_CX_CTRL_HSP_ENABLE |
1153                                 COH901318_CX_CTRL_HSS_DISABLE |
1154                                 COH901318_CX_CTRL_DDMA_LEGACY |
1155                                 COH901318_CX_CTRL_PRDD_SOURCE,
1156         },
1157         {
1158                 .number = U300_DMA_PCM_I2S1_RX,
1159                 .name = "PCM I2S1 RX",
1160                 .priority_high = 1,
1161                 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1162                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1163                                 COH901318_CX_CFG_LCR_DISABLE |
1164                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1165                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1166                 .param.ctrl_lli_chained = 0 |
1167                                 COH901318_CX_CTRL_TC_ENABLE |
1168                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1169                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1170                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1171                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1172                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1173                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1174                                 COH901318_CX_CTRL_TCP_DISABLE |
1175                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1176                                 COH901318_CX_CTRL_HSP_ENABLE |
1177                                 COH901318_CX_CTRL_HSS_DISABLE |
1178                                 COH901318_CX_CTRL_DDMA_LEGACY |
1179                                 COH901318_CX_CTRL_PRDD_DEST,
1180                 .param.ctrl_lli = 0 |
1181                                 COH901318_CX_CTRL_TC_ENABLE |
1182                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1183                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1184                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1185                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1186                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1187                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1188                                 COH901318_CX_CTRL_TCP_ENABLE |
1189                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1190                                 COH901318_CX_CTRL_HSP_ENABLE |
1191                                 COH901318_CX_CTRL_HSS_DISABLE |
1192                                 COH901318_CX_CTRL_DDMA_LEGACY |
1193                                 COH901318_CX_CTRL_PRDD_DEST,
1194                 .param.ctrl_lli_last = 0 |
1195                                 COH901318_CX_CTRL_TC_ENABLE |
1196                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1197                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1198                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1199                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1200                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1201                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1202                                 COH901318_CX_CTRL_TCP_ENABLE |
1203                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1204                                 COH901318_CX_CTRL_HSP_ENABLE |
1205                                 COH901318_CX_CTRL_HSS_DISABLE |
1206                                 COH901318_CX_CTRL_DDMA_LEGACY |
1207                                 COH901318_CX_CTRL_PRDD_DEST,
1208         },
1209         {
1210                 .number = U300_DMA_XGAM_CDI,
1211                 .name = "XGAM CDI",
1212                 .priority_high = 0,
1213         },
1214         {
1215                 .number = U300_DMA_XGAM_PDI,
1216                 .name = "XGAM PDI",
1217                 .priority_high = 0,
1218         },
1219         /*
1220          * Don't set up device address, burst count or size of src
1221          * or dst bus for this peripheral - handled by PrimeCell
1222          * DMA extension.
1223          */
1224         {
1225                 .number = U300_DMA_SPI_TX,
1226                 .name = "SPI TX",
1227                 .priority_high = 0,
1228                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1229                                 COH901318_CX_CFG_LCR_DISABLE |
1230                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1231                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1232                 .param.ctrl_lli_chained = 0 |
1233                                 COH901318_CX_CTRL_TC_ENABLE |
1234                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1235                                 COH901318_CX_CTRL_TCP_DISABLE |
1236                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1237                                 COH901318_CX_CTRL_HSP_ENABLE |
1238                                 COH901318_CX_CTRL_HSS_DISABLE |
1239                                 COH901318_CX_CTRL_DDMA_LEGACY,
1240                 .param.ctrl_lli = 0 |
1241                                 COH901318_CX_CTRL_TC_ENABLE |
1242                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1243                                 COH901318_CX_CTRL_TCP_DISABLE |
1244                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1245                                 COH901318_CX_CTRL_HSP_ENABLE |
1246                                 COH901318_CX_CTRL_HSS_DISABLE |
1247                                 COH901318_CX_CTRL_DDMA_LEGACY,
1248                 .param.ctrl_lli_last = 0 |
1249                                 COH901318_CX_CTRL_TC_ENABLE |
1250                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1251                                 COH901318_CX_CTRL_TCP_DISABLE |
1252                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1253                                 COH901318_CX_CTRL_HSP_ENABLE |
1254                                 COH901318_CX_CTRL_HSS_DISABLE |
1255                                 COH901318_CX_CTRL_DDMA_LEGACY,
1256         },
1257         {
1258                 .number = U300_DMA_SPI_RX,
1259                 .name = "SPI RX",
1260                 .priority_high = 0,
1261                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1262                                 COH901318_CX_CFG_LCR_DISABLE |
1263                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1264                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1265                 .param.ctrl_lli_chained = 0 |
1266                                 COH901318_CX_CTRL_TC_ENABLE |
1267                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1268                                 COH901318_CX_CTRL_TCP_DISABLE |
1269                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1270                                 COH901318_CX_CTRL_HSP_ENABLE |
1271                                 COH901318_CX_CTRL_HSS_DISABLE |
1272                                 COH901318_CX_CTRL_DDMA_LEGACY,
1273                 .param.ctrl_lli = 0 |
1274                                 COH901318_CX_CTRL_TC_ENABLE |
1275                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1276                                 COH901318_CX_CTRL_TCP_DISABLE |
1277                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1278                                 COH901318_CX_CTRL_HSP_ENABLE |
1279                                 COH901318_CX_CTRL_HSS_DISABLE |
1280                                 COH901318_CX_CTRL_DDMA_LEGACY,
1281                 .param.ctrl_lli_last = 0 |
1282                                 COH901318_CX_CTRL_TC_ENABLE |
1283                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1284                                 COH901318_CX_CTRL_TCP_DISABLE |
1285                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1286                                 COH901318_CX_CTRL_HSP_ENABLE |
1287                                 COH901318_CX_CTRL_HSS_DISABLE |
1288                                 COH901318_CX_CTRL_DDMA_LEGACY,
1289
1290         },
1291         {
1292                 .number = U300_DMA_GENERAL_PURPOSE_0,
1293                 .name = "GENERAL 00",
1294                 .priority_high = 0,
1295
1296                 .param.config = flags_memcpy_config,
1297                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1298                 .param.ctrl_lli = flags_memcpy_lli,
1299                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1300         },
1301         {
1302                 .number = U300_DMA_GENERAL_PURPOSE_1,
1303                 .name = "GENERAL 01",
1304                 .priority_high = 0,
1305
1306                 .param.config = flags_memcpy_config,
1307                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1308                 .param.ctrl_lli = flags_memcpy_lli,
1309                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1310         },
1311         {
1312                 .number = U300_DMA_GENERAL_PURPOSE_2,
1313                 .name = "GENERAL 02",
1314                 .priority_high = 0,
1315
1316                 .param.config = flags_memcpy_config,
1317                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1318                 .param.ctrl_lli = flags_memcpy_lli,
1319                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1320         },
1321         {
1322                 .number = U300_DMA_GENERAL_PURPOSE_3,
1323                 .name = "GENERAL 03",
1324                 .priority_high = 0,
1325
1326                 .param.config = flags_memcpy_config,
1327                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1328                 .param.ctrl_lli = flags_memcpy_lli,
1329                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1330         },
1331         {
1332                 .number = U300_DMA_GENERAL_PURPOSE_4,
1333                 .name = "GENERAL 04",
1334                 .priority_high = 0,
1335
1336                 .param.config = flags_memcpy_config,
1337                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1338                 .param.ctrl_lli = flags_memcpy_lli,
1339                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1340         },
1341         {
1342                 .number = U300_DMA_GENERAL_PURPOSE_5,
1343                 .name = "GENERAL 05",
1344                 .priority_high = 0,
1345
1346                 .param.config = flags_memcpy_config,
1347                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1348                 .param.ctrl_lli = flags_memcpy_lli,
1349                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1350         },
1351         {
1352                 .number = U300_DMA_GENERAL_PURPOSE_6,
1353                 .name = "GENERAL 06",
1354                 .priority_high = 0,
1355
1356                 .param.config = flags_memcpy_config,
1357                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1358                 .param.ctrl_lli = flags_memcpy_lli,
1359                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1360         },
1361         {
1362                 .number = U300_DMA_GENERAL_PURPOSE_7,
1363                 .name = "GENERAL 07",
1364                 .priority_high = 0,
1365
1366                 .param.config = flags_memcpy_config,
1367                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1368                 .param.ctrl_lli = flags_memcpy_lli,
1369                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1370         },
1371         {
1372                 .number = U300_DMA_GENERAL_PURPOSE_8,
1373                 .name = "GENERAL 08",
1374                 .priority_high = 0,
1375
1376                 .param.config = flags_memcpy_config,
1377                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1378                 .param.ctrl_lli = flags_memcpy_lli,
1379                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1380         },
1381         {
1382                 .number = U300_DMA_UART1_TX,
1383                 .name = "UART1 TX",
1384                 .priority_high = 0,
1385         },
1386         {
1387                 .number = U300_DMA_UART1_RX,
1388                 .name = "UART1 RX",
1389                 .priority_high = 0,
1390         }
1391 };
1392
1393
1394 static struct coh901318_platform coh901318_platform = {
1395         .chans_slave = dma_slave_channels,
1396         .chans_memcpy = dma_memcpy_channels,
1397         .access_memory_state = coh901318_access_memory_state,
1398         .chan_conf = chan_config,
1399         .max_channels = U300_DMA_CHANNELS,
1400 };
1401
1402 static struct resource pinctrl_resources[] = {
1403         {
1404                 .start = U300_SYSCON_BASE,
1405                 .end   = U300_SYSCON_BASE + SZ_4K - 1,
1406                 .flags = IORESOURCE_MEM,
1407         },
1408 };
1409
1410 static struct platform_device wdog_device = {
1411         .name = "coh901327_wdog",
1412         .id = -1,
1413         .num_resources = ARRAY_SIZE(wdog_resources),
1414         .resource = wdog_resources,
1415 };
1416
1417 static struct platform_device i2c0_device = {
1418         .name = "stu300",
1419         .id = 0,
1420         .num_resources = ARRAY_SIZE(i2c0_resources),
1421         .resource = i2c0_resources,
1422 };
1423
1424 static struct platform_device i2c1_device = {
1425         .name = "stu300",
1426         .id = 1,
1427         .num_resources = ARRAY_SIZE(i2c1_resources),
1428         .resource = i2c1_resources,
1429 };
1430
1431 static struct platform_device pinctrl_device = {
1432         .name = "pinctrl-u300",
1433         .id = -1,
1434         .num_resources = ARRAY_SIZE(pinctrl_resources),
1435         .resource = pinctrl_resources,
1436 };
1437
1438 /*
1439  * The different variants have a few different versions of the
1440  * GPIO block, with different number of ports.
1441  */
1442 static struct u300_gpio_platform u300_gpio_plat = {
1443         .ports = 7,
1444         .gpio_base = 0,
1445 };
1446
1447 static struct platform_device gpio_device = {
1448         .name = "u300-gpio",
1449         .id = -1,
1450         .num_resources = ARRAY_SIZE(gpio_resources),
1451         .resource = gpio_resources,
1452         .dev = {
1453                 .platform_data = &u300_gpio_plat,
1454         },
1455 };
1456
1457 static struct platform_device keypad_device = {
1458         .name = "keypad",
1459         .id = -1,
1460         .num_resources = ARRAY_SIZE(keypad_resources),
1461         .resource = keypad_resources,
1462 };
1463
1464 static struct platform_device rtc_device = {
1465         .name = "rtc-coh901331",
1466         .id = -1,
1467         .num_resources = ARRAY_SIZE(rtc_resources),
1468         .resource = rtc_resources,
1469 };
1470
1471 static struct mtd_partition u300_partitions[] = {
1472         {
1473                 .name = "bootrecords",
1474                 .offset = 0,
1475                 .size = SZ_128K,
1476         },
1477         {
1478                 .name = "free",
1479                 .offset = SZ_128K,
1480                 .size = 8064 * SZ_1K,
1481         },
1482         {
1483                 .name = "platform",
1484                 .offset = 8192 * SZ_1K,
1485                 .size = 253952 * SZ_1K,
1486         },
1487 };
1488
1489 static struct fsmc_nand_platform_data nand_platform_data = {
1490         .partitions = u300_partitions,
1491         .nr_partitions = ARRAY_SIZE(u300_partitions),
1492         .options = NAND_SKIP_BBTSCAN,
1493         .width = FSMC_NAND_BW8,
1494         .ale_off = PLAT_NAND_ALE,
1495         .cle_off = PLAT_NAND_CLE,
1496 };
1497
1498 static struct platform_device nand_device = {
1499         .name = "fsmc-nand",
1500         .id = -1,
1501         .resource = fsmc_resources,
1502         .num_resources = ARRAY_SIZE(fsmc_resources),
1503         .dev = {
1504                 .platform_data = &nand_platform_data,
1505         },
1506 };
1507
1508 static struct platform_device dma_device = {
1509         .name           = "coh901318",
1510         .id             = -1,
1511         .resource       = dma_resource,
1512         .num_resources  = ARRAY_SIZE(dma_resource),
1513         .dev = {
1514                 .platform_data = &coh901318_platform,
1515                 .coherent_dma_mask = ~0,
1516         },
1517 };
1518
1519 static unsigned long pin_pullup_conf[] = {
1520         PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
1521 };
1522
1523 static unsigned long pin_highz_conf[] = {
1524         PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
1525 };
1526
1527 /* Pin control settings */
1528 static struct pinctrl_map __initdata u300_pinmux_map[] = {
1529         /* anonymous maps for chip power and EMIFs */
1530         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
1531         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
1532         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
1533         /* per-device maps for MMC/SD, SPI and UART */
1534         PIN_MAP_MUX_GROUP_DEFAULT("mmci",  "pinctrl-u300", NULL, "mmc0"),
1535         PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
1536         PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
1537         /* This pin is used for clock return rather than GPIO */
1538         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
1539                                     pin_pullup_conf),
1540         /* This pin is used for card detect */
1541         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
1542                                     pin_highz_conf),
1543 };
1544
1545 /*
1546  * Notice that AMBA devices are initialized before platform devices.
1547  *
1548  */
1549 static struct platform_device *platform_devs[] __initdata = {
1550         &dma_device,
1551         &i2c0_device,
1552         &i2c1_device,
1553         &keypad_device,
1554         &rtc_device,
1555         &pinctrl_device,
1556         &gpio_device,
1557         &nand_device,
1558         &wdog_device,
1559 };
1560
1561 /*
1562  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1563  * together so some interrupts are connected to the first one and some
1564  * to the second one.
1565  */
1566 static void __init u300_init_irq(void)
1567 {
1568         u32 mask[2] = {0, 0};
1569         struct clk *clk;
1570         int i;
1571
1572         /* initialize clocking early, we want to clock the INTCON */
1573         u300_clk_init(U300_SYSCON_VBASE);
1574
1575         /* Bootstrap EMIF and SEMI clocks */
1576         clk = clk_get_sys("pl172", NULL);
1577         BUG_ON(IS_ERR(clk));
1578         clk_prepare_enable(clk);
1579         clk = clk_get_sys("semi", NULL);
1580         BUG_ON(IS_ERR(clk));
1581         clk_prepare_enable(clk);
1582
1583         /* Clock the interrupt controller */
1584         clk = clk_get_sys("intcon", NULL);
1585         BUG_ON(IS_ERR(clk));
1586         clk_prepare_enable(clk);
1587
1588         for (i = 0; i < U300_VIC_IRQS_END; i++)
1589                 set_bit(i, (unsigned long *) &mask[0]);
1590         vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
1591                  mask[0], mask[0]);
1592         vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
1593                  mask[1], mask[1]);
1594 }
1595
1596
1597 /*
1598  * U300 platforms peripheral handling
1599  */
1600 struct db_chip {
1601         u16 chipid;
1602         const char *name;
1603 };
1604
1605 /*
1606  * This is a list of the Digital Baseband chips used in the U300 platform.
1607  */
1608 static struct db_chip db_chips[] __initdata = {
1609         {
1610                 .chipid = 0xb800,
1611                 .name = "DB3000",
1612         },
1613         {
1614                 .chipid = 0xc000,
1615                 .name = "DB3100",
1616         },
1617         {
1618                 .chipid = 0xc800,
1619                 .name = "DB3150",
1620         },
1621         {
1622                 .chipid = 0xd800,
1623                 .name = "DB3200",
1624         },
1625         {
1626                 .chipid = 0xe000,
1627                 .name = "DB3250",
1628         },
1629         {
1630                 .chipid = 0xe800,
1631                 .name = "DB3210",
1632         },
1633         {
1634                 .chipid = 0xf000,
1635                 .name = "DB3350 P1x",
1636         },
1637         {
1638                 .chipid = 0xf100,
1639                 .name = "DB3350 P2x",
1640         },
1641         {
1642                 .chipid = 0x0000, /* List terminator */
1643                 .name = NULL,
1644         }
1645 };
1646
1647 static void __init u300_init_check_chip(void)
1648 {
1649
1650         u16 val;
1651         struct db_chip *chip;
1652         const char *chipname;
1653         const char unknown[] = "UNKNOWN";
1654
1655         /* Read out and print chip ID */
1656         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1657         /* This is in funky bigendian order... */
1658         val = (val & 0xFFU) << 8 | (val >> 8);
1659         chip = db_chips;
1660         chipname = unknown;
1661
1662         for ( ; chip->chipid; chip++) {
1663                 if (chip->chipid == (val & 0xFF00U)) {
1664                         chipname = chip->name;
1665                         break;
1666                 }
1667         }
1668         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1669                "(chip ID 0x%04x)\n", chipname, val);
1670
1671         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1672                 printk(KERN_ERR "Platform configured for BS335 " \
1673                        " with DB3350 but %s detected, expect problems!",
1674                        chipname);
1675         }
1676 }
1677
1678 /*
1679  * Some devices and their resources require reserved physical memory from
1680  * the end of the available RAM. This function traverses the list of devices
1681  * and assigns actual addresses to these.
1682  */
1683 static void __init u300_assign_physmem(void)
1684 {
1685         unsigned long curr_start = __pa(high_memory);
1686         int i, j;
1687
1688         for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1689                 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1690                         struct resource *const res =
1691                           &platform_devs[i]->resource[j];
1692
1693                         if (IORESOURCE_MEM == res->flags &&
1694                                      0 == res->start) {
1695                                 res->start  = curr_start;
1696                                 res->end   += curr_start;
1697                                 curr_start += resource_size(res);
1698
1699                                 printk(KERN_INFO "core.c: Mapping RAM " \
1700                                        "%#x-%#x to device %s:%s\n",
1701                                         res->start, res->end,
1702                                        platform_devs[i]->name, res->name);
1703                         }
1704                 }
1705         }
1706 }
1707
1708 static void __init u300_init_machine(void)
1709 {
1710         int i;
1711         u16 val;
1712
1713         /* Check what platform we run and print some status information */
1714         u300_init_check_chip();
1715
1716         /* Initialize SPI device with some board specifics */
1717         u300_spi_init(&pl022_device);
1718
1719         /* Register the AMBA devices in the AMBA bus abstraction layer */
1720         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1721                 struct amba_device *d = amba_devs[i];
1722                 amba_device_register(d, &iomem_resource);
1723         }
1724
1725         u300_assign_physmem();
1726
1727         /* Initialize pinmuxing */
1728         pinctrl_register_mappings(u300_pinmux_map,
1729                                   ARRAY_SIZE(u300_pinmux_map));
1730
1731         /* Register subdevices on the I2C buses */
1732         u300_i2c_register_board_devices();
1733
1734         /* Register the platform devices */
1735         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1736
1737         /* Register subdevices on the SPI bus */
1738         u300_spi_register_board_devices();
1739
1740         /* Enable SEMI self refresh */
1741         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1742                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1743         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1744 }
1745
1746 /* Forward declare this function from the watchdog */
1747 void coh901327_watchdog_reset(void);
1748
1749 static void u300_restart(char mode, const char *cmd)
1750 {
1751         switch (mode) {
1752         case 's':
1753         case 'h':
1754 #ifdef CONFIG_COH901327_WATCHDOG
1755                 coh901327_watchdog_reset();
1756 #endif
1757                 break;
1758         default:
1759                 /* Do nothing */
1760                 break;
1761         }
1762         /* Wait for system do die/reset. */
1763         while (1);
1764 }
1765
1766 MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
1767         /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
1768         .atag_offset    = 0x100,
1769         .map_io         = u300_map_io,
1770         .nr_irqs        = 0,
1771         .init_irq       = u300_init_irq,
1772         .handle_irq     = vic_handle_irq,
1773         .timer          = &u300_timer,
1774         .init_machine   = u300_init_machine,
1775         .restart        = u300_restart,
1776 MACHINE_END