2 * UniPhier SG (SoC Glue) block registers
4 * Copyright (C) 2011-2014 Panasonic Corporation
6 * SPDX-License-Identifier: GPL-2.0+
10 #define ARCH_SG_REGS_H
13 #define SG_CTRL_BASE 0x5f800000
14 #define SG_DBG_BASE 0x5f900000
17 #define SG_REVISION (SG_CTRL_BASE | 0x0000)
18 #define SG_REVISION_TYPE_SHIFT 16
19 #define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT)
20 #define SG_REVISION_MODEL_SHIFT 8
21 #define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT)
22 #define SG_REVISION_REV_SHIFT 0
23 #define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT)
25 /* Memory Configuration */
26 #define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
28 #define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
29 #define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
30 #define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
31 #define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
32 #define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
33 #define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
34 #define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
36 #define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
37 #define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
38 #define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
39 #define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
40 #define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
41 #define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
42 #define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
44 #define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
45 #define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
46 #define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
47 #define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
48 #define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
49 #define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
51 #define SG_MEMCONF_SPARSEMEM (0x1 << 4)
54 #define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
56 #if defined(CONFIG_MACH_PH1_PRO4)
57 # define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8)
58 #elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
59 # define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4)
62 #if defined(CONFIG_MACH_PH1_PRO4)
63 #define SG_PINSELBITS 4
64 #elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
65 #define SG_PINSELBITS 8
68 #define SG_PINSEL_ADDR(n) (SG_PINCTRL((n) * (SG_PINSELBITS) / 32))
69 #define SG_PINSEL_MASK(n) (~(((1 << (SG_PINSELBITS)) - 1) << \
70 ((n) * (SG_PINSELBITS) % 32)))
71 #define SG_PINSEL_MODE(n, mode) ((mode) << ((n) * (SG_PINSELBITS) % 32))
73 /* Only for PH1-Pro4 */
74 #define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
77 #define SG_IECTRL (SG_CTRL_BASE | 0x1d00)
80 #define SG_PINMON0 (SG_DBG_BASE | 0x0100)
82 #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
83 #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
84 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
85 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
87 #define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
88 #define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
89 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
90 #define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
91 #define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
93 #define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
94 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
95 #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
96 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
100 .macro set_pinsel, n, value, ra, rd
101 ldr \ra, =SG_PINSEL_ADDR(\n)
103 and \rd, \rd, #SG_PINSEL_MASK(\n)
104 orr \rd, \rd, #SG_PINSEL_MODE(\n, \value)
110 #include <linux/types.h>
111 #include <linux/sizes.h>
114 static inline void sg_set_pinsel(int n, int value)
116 writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n))
117 | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
120 static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
122 int size_mb = size / num;
127 ret = SG_MEMCONF_CH0_SZ_64M;
130 ret = SG_MEMCONF_CH0_SZ_128M;
133 ret = SG_MEMCONF_CH0_SZ_256M;
136 ret = SG_MEMCONF_CH0_SZ_512M;
139 ret = SG_MEMCONF_CH0_SZ_1G;
148 ret |= SG_MEMCONF_CH0_NUM_1;
151 ret |= SG_MEMCONF_CH0_NUM_2;
160 static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
162 int size_mb = size / num;
167 ret = SG_MEMCONF_CH1_SZ_64M;
170 ret = SG_MEMCONF_CH1_SZ_128M;
173 ret = SG_MEMCONF_CH1_SZ_256M;
176 ret = SG_MEMCONF_CH1_SZ_512M;
179 ret = SG_MEMCONF_CH1_SZ_1G;
188 ret |= SG_MEMCONF_CH1_NUM_1;
191 ret |= SG_MEMCONF_CH1_NUM_2;
200 static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
202 int size_mb = size / num;
207 ret = SG_MEMCONF_CH2_SZ_64M;
210 ret = SG_MEMCONF_CH2_SZ_128M;
213 ret = SG_MEMCONF_CH2_SZ_256M;
216 ret = SG_MEMCONF_CH2_SZ_512M;
225 ret |= SG_MEMCONF_CH2_NUM_1;
228 ret |= SG_MEMCONF_CH2_NUM_2;
236 #endif /* __ASSEMBLY__ */
238 #endif /* ARCH_SG_REGS_H */