2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <mach/sbc-regs.h>
10 #include <mach/sg-regs.h>
16 /* system bus output enable */
22 * SBCTRL0* does not need settings because PH1-sLD8 has no support for
23 * XECS0. The boot swap must be enabled to boot from the support card.
26 if (boot_is_swapped()) {
27 /* XECS1 : boot memory if boot swap is on */
28 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
29 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
30 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
31 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
34 /* XECS4 : sub memory */
35 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
36 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
37 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
38 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
40 /* XECS5 : peripherals */
41 writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
42 writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
43 writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
44 writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
46 /* base address regsiters */
47 writel(0x0000bc01, SBBASE0); /* boot memory */
48 writel(0x0900bfff, SBBASE1); /* dummy */
49 writel(0x0400bc01, SBBASE4); /* sub memory */
50 writel(0x0800bf01, SBBASE5); /* peripherals */
52 sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
53 sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
55 /* dummy read to assure write process */