arch/arm/mach-ux500/clock.c

   1 /*
   2  *  Copyright (C) 2009 ST-Ericsson
   3  *  Copyright (C) 2009 STMicroelectronics
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9 #include <linux/module.h>
  10 #include <linux/kernel.h>
  11 #include <linux/list.h>
  12 #include <linux/errno.h>
  13 #include <linux/err.h>
  14 #include <linux/clk.h>
  15 #include <linux/io.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/cpufreq.h>
  18
  19 #include <plat/mtu.h>
  20 #include <mach/hardware.h>
  21 #include "clock.h"
  22
  23 #ifdef CONFIG_DEBUG_FS
  24 #include <linux/debugfs.h>
  25 #include <linux/uaccess.h>      /* for copy_from_user */
  26 static LIST_HEAD(clk_list);
  27 #endif
  28
  29 #define PRCC_PCKEN              0x00
  30 #define PRCC_PCKDIS             0x04
  31 #define PRCC_KCKEN              0x08
  32 #define PRCC_KCKDIS             0x0C
  33
  34 #define PRCM_YYCLKEN0_MGT_SET   0x510
  35 #define PRCM_YYCLKEN1_MGT_SET   0x514
  36 #define PRCM_YYCLKEN0_MGT_CLR   0x518
  37 #define PRCM_YYCLKEN1_MGT_CLR   0x51C
  38 #define PRCM_YYCLKEN0_MGT_VAL   0x520
  39 #define PRCM_YYCLKEN1_MGT_VAL   0x524
  40
  41 #define PRCM_SVAMMDSPCLK_MGT    0x008
  42 #define PRCM_SIAMMDSPCLK_MGT    0x00C
  43 #define PRCM_SGACLK_MGT         0x014
  44 #define PRCM_UARTCLK_MGT        0x018
  45 #define PRCM_MSP02CLK_MGT       0x01C
  46 #define PRCM_MSP1CLK_MGT        0x288
  47 #define PRCM_I2CCLK_MGT         0x020
  48 #define PRCM_SDMMCCLK_MGT       0x024
  49 #define PRCM_SLIMCLK_MGT        0x028
  50 #define PRCM_PER1CLK_MGT        0x02C
  51 #define PRCM_PER2CLK_MGT        0x030
  52 #define PRCM_PER3CLK_MGT        0x034
  53 #define PRCM_PER5CLK_MGT        0x038
  54 #define PRCM_PER6CLK_MGT        0x03C
  55 #define PRCM_PER7CLK_MGT        0x040
  56 #define PRCM_LCDCLK_MGT         0x044
  57 #define PRCM_BMLCLK_MGT         0x04C
  58 #define PRCM_HSITXCLK_MGT       0x050
  59 #define PRCM_HSIRXCLK_MGT       0x054
  60 #define PRCM_HDMICLK_MGT        0x058
  61 #define PRCM_APEATCLK_MGT       0x05C
  62 #define PRCM_APETRACECLK_MGT    0x060
  63 #define PRCM_MCDECLK_MGT        0x064
  64 #define PRCM_IPI2CCLK_MGT       0x068
  65 #define PRCM_DSIALTCLK_MGT      0x06C
  66 #define PRCM_DMACLK_MGT         0x074
  67 #define PRCM_B2R2CLK_MGT        0x078
  68 #define PRCM_TVCLK_MGT          0x07C
  69 #define PRCM_TCR                0x1C8
  70 #define PRCM_TCR_STOPPED        (1 << 16)
  71 #define PRCM_TCR_DOZE_MODE      (1 << 17)
  72 #define PRCM_UNIPROCLK_MGT      0x278
  73 #define PRCM_SSPCLK_MGT         0x280
  74 #define PRCM_RNGCLK_MGT         0x284
  75 #define PRCM_UICCCLK_MGT        0x27C
  76
  77 #define PRCM_MGT_ENABLE         (1 << 8)
  78
  79 static DEFINE_SPINLOCK(clocks_lock);
  80
  81 static void __clk_enable(struct clk *clk)
  82 {
  83         if (clk->enabled++ == 0) {
  84                 if (clk->parent_cluster)
  85                         __clk_enable(clk->parent_cluster);
  86
  87                 if (clk->parent_periph)
  88                         __clk_enable(clk->parent_periph);
  89
  90                 if (clk->ops && clk->ops->enable)
  91                         clk->ops->enable(clk);
  92         }
  93 }
  94
  95 int clk_enable(struct clk *clk)
  96 {
  97         unsigned long flags;
  98
  99         spin_lock_irqsave(&clocks_lock, flags);
 100         __clk_enable(clk);
 101         spin_unlock_irqrestore(&clocks_lock, flags);
 102
 103         return 0;
 104 }
 105 EXPORT_SYMBOL(clk_enable);
 106
 107 static void __clk_disable(struct clk *clk)
 108 {
 109         if (--clk->enabled == 0) {
 110                 if (clk->ops && clk->ops->disable)
 111                         clk->ops->disable(clk);
 112
 113                 if (clk->parent_periph)
 114                         __clk_disable(clk->parent_periph);
 115
 116                 if (clk->parent_cluster)
 117                         __clk_disable(clk->parent_cluster);
 118         }
 119 }
 120
 121 void clk_disable(struct clk *clk)
 122 {
 123         unsigned long flags;
 124
 125         WARN_ON(!clk->enabled);
 126
 127         spin_lock_irqsave(&clocks_lock, flags);
 128         __clk_disable(clk);
 129         spin_unlock_irqrestore(&clocks_lock, flags);
 130 }
 131 EXPORT_SYMBOL(clk_disable);
 132
 133 /*
 134  * The MTU has a separate, rather complex muxing setup
 135  * with alternative parents (peripheral cluster or
 136  * ULP or fixed 32768 Hz) depending on settings
 137  */
 138 static unsigned long clk_mtu_get_rate(struct clk *clk)
 139 {
 140         void __iomem *addr;
 141         u32 tcr;
 142         int mtu = (int) clk->data;
 143         /*
 144          * One of these is selected eventually
 145          * TODO: Replace the constant with a reference
 146          * to the ULP source once this is modeled.
 147          */
 148         unsigned long clk32k = 32768;
 149         unsigned long mturate;
 150         unsigned long retclk;
 151
 152         if (cpu_is_u5500())
 153                 addr = __io_address(U5500_PRCMU_BASE);
 154         else if (cpu_is_u8500())
 155                 addr = __io_address(U8500_PRCMU_BASE);
 156         else
 157                 ux500_unknown_soc();
 158
 159         /*
 160          * On a startup, always conifgure the TCR to the doze mode;
 161          * bootloaders do it for us. Do this in the kernel too.
 162          */
 163         writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR);
 164
 165         tcr = readl(addr + PRCM_TCR);
 166
 167         /* Get the rate from the parent as a default */
 168         if (clk->parent_periph)
 169                 mturate = clk_get_rate(clk->parent_periph);
 170         else if (clk->parent_cluster)
 171                 mturate = clk_get_rate(clk->parent_cluster);
 172         else
 173                 /* We need to be connected SOMEWHERE */
 174                 BUG();
 175
 176         /* Return the clock selected for this MTU */
 177         if (tcr & (1 << mtu))
 178                 retclk = clk32k;
 179         else
 180                 retclk = mturate;
 181
 182         pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk);
 183         return retclk;
 184 }
 185
 186 unsigned long clk_get_rate(struct clk *clk)
 187 {
 188         unsigned long rate;
 189
 190         /*
 191          * If there is a custom getrate callback for this clock,
 192          * it will take precedence.
 193          */
 194         if (clk->get_rate)
 195                 return clk->get_rate(clk);
 196
 197         if (clk->ops && clk->ops->get_rate)
 198                 return clk->ops->get_rate(clk);
 199
 200         rate = clk->rate;
 201         if (!rate) {
 202                 if (clk->parent_periph)
 203                         rate = clk_get_rate(clk->parent_periph);
 204                 else if (clk->parent_cluster)
 205                         rate = clk_get_rate(clk->parent_cluster);
 206         }
 207
 208         return rate;
 209 }
 210 EXPORT_SYMBOL(clk_get_rate);
 211
 212 long clk_round_rate(struct clk *clk, unsigned long rate)
 213 {
 214         /*TODO*/
 215         return rate;
 216 }
 217 EXPORT_SYMBOL(clk_round_rate);
 218
 219 int clk_set_rate(struct clk *clk, unsigned long rate)
 220 {
 221         clk->rate = rate;
 222         return 0;
 223 }
 224 EXPORT_SYMBOL(clk_set_rate);
 225
 226 static void clk_prcmu_enable(struct clk *clk)
 227 {
 228         void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
 229                                    + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off;
 230
 231         writel(1 << clk->prcmu_cg_bit, cg_set_reg);
 232 }
 233
 234 static void clk_prcmu_disable(struct clk *clk)
 235 {
 236         void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE)
 237                                    + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off;
 238
 239         writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
 240 }
 241
 242 static struct clkops clk_prcmu_ops = {
 243         .enable = clk_prcmu_enable,
 244         .disable = clk_prcmu_disable,
 245 };
 246
 247 static unsigned int clkrst_base[] = {
 248         [1] = U8500_CLKRST1_BASE,
 249         [2] = U8500_CLKRST2_BASE,
 250         [3] = U8500_CLKRST3_BASE,
 251         [5] = U8500_CLKRST5_BASE,
 252         [6] = U8500_CLKRST6_BASE,
 253 };
 254
 255 static void clk_prcc_enable(struct clk *clk)
 256 {
 257         void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
 258
 259         if (clk->prcc_kernel != -1)
 260                 writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN);
 261
 262         if (clk->prcc_bus != -1)
 263                 writel(1 << clk->prcc_bus, addr + PRCC_PCKEN);
 264 }
 265
 266 static void clk_prcc_disable(struct clk *clk)
 267 {
 268         void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
 269
 270         if (clk->prcc_bus != -1)
 271                 writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS);
 272
 273         if (clk->prcc_kernel != -1)
 274                 writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS);
 275 }
 276
 277 static struct clkops clk_prcc_ops = {
 278         .enable = clk_prcc_enable,
 279         .disable = clk_prcc_disable,
 280 };
 281
 282 static struct clk clk_32khz = {
 283         .name =  "clk_32khz",
 284         .rate = 32000,
 285 };
 286
 287 /*
 288  * PRCMU level clock gating
 289  */
 290
 291 /* Bank 0 */
 292 static DEFINE_PRCMU_CLK(svaclk,         0x0, 2, SVAMMDSPCLK);
 293 static DEFINE_PRCMU_CLK(siaclk,         0x0, 3, SIAMMDSPCLK);
 294 static DEFINE_PRCMU_CLK(sgaclk,         0x0, 4, SGACLK);
 295 static DEFINE_PRCMU_CLK_RATE(uartclk,   0x0, 5, UARTCLK, 38400000);
 296 static DEFINE_PRCMU_CLK(msp02clk,       0x0, 6, MSP02CLK);
 297 static DEFINE_PRCMU_CLK(msp1clk,        0x0, 7, MSP1CLK); /* v1 */
 298 static DEFINE_PRCMU_CLK_RATE(i2cclk,    0x0, 8, I2CCLK, 48000000);
 299 static DEFINE_PRCMU_CLK_RATE(sdmmcclk,  0x0, 9, SDMMCCLK, 100000000);
 300 static DEFINE_PRCMU_CLK(slimclk,        0x0, 10, SLIMCLK);
 301 static DEFINE_PRCMU_CLK(per1clk,        0x0, 11, PER1CLK);
 302 static DEFINE_PRCMU_CLK(per2clk,        0x0, 12, PER2CLK);
 303 static DEFINE_PRCMU_CLK(per3clk,        0x0, 13, PER3CLK);
 304 static DEFINE_PRCMU_CLK(per5clk,        0x0, 14, PER5CLK);
 305 static DEFINE_PRCMU_CLK_RATE(per6clk,   0x0, 15, PER6CLK, 133330000);
 306 static DEFINE_PRCMU_CLK(lcdclk,         0x0, 17, LCDCLK);
 307 static DEFINE_PRCMU_CLK(bmlclk,         0x0, 18, BMLCLK);
 308 static DEFINE_PRCMU_CLK(hsitxclk,       0x0, 19, HSITXCLK);
 309 static DEFINE_PRCMU_CLK(hsirxclk,       0x0, 20, HSIRXCLK);
 310 static DEFINE_PRCMU_CLK(hdmiclk,        0x0, 21, HDMICLK);
 311 static DEFINE_PRCMU_CLK(apeatclk,       0x0, 22, APEATCLK);
 312 static DEFINE_PRCMU_CLK(apetraceclk,    0x0, 23, APETRACECLK);
 313 static DEFINE_PRCMU_CLK(mcdeclk,        0x0, 24, MCDECLK);
 314 static DEFINE_PRCMU_CLK(ipi2clk,        0x0, 25, IPI2CCLK);
 315 static DEFINE_PRCMU_CLK(dsialtclk,      0x0, 26, DSIALTCLK); /* v1 */
 316 static DEFINE_PRCMU_CLK(dmaclk,         0x0, 27, DMACLK);
 317 static DEFINE_PRCMU_CLK(b2r2clk,        0x0, 28, B2R2CLK);
 318 static DEFINE_PRCMU_CLK(tvclk,          0x0, 29, TVCLK);
 319 static DEFINE_PRCMU_CLK(uniproclk,      0x0, 30, UNIPROCLK); /* v1 */
 320 static DEFINE_PRCMU_CLK_RATE(sspclk,    0x0, 31, SSPCLK, 48000000); /* v1 */
 321
 322 /* Bank 1 */
 323 static DEFINE_PRCMU_CLK(rngclk,         0x4, 0, RNGCLK); /* v1 */
 324 static DEFINE_PRCMU_CLK(uiccclk,        0x4, 1, UICCCLK); /* v1 */
 325
 326 /*
 327  * PRCC level clock gating
 328  * Format: per#, clk, PCKEN bit, KCKEN bit, parent
 329  */
 330
 331 /* Peripheral Cluster #1 */
 332 static DEFINE_PRCC_CLK(1, i2c4,         10, 9, &clk_i2cclk);
 333 static DEFINE_PRCC_CLK(1, gpio0,        9, -1, NULL);
 334 static DEFINE_PRCC_CLK(1, slimbus0,     8,  8, &clk_slimclk);
 335 static DEFINE_PRCC_CLK(1, spi3,         7, -1, NULL);
 336 static DEFINE_PRCC_CLK(1, i2c2,         6,  6, &clk_i2cclk);
 337 static DEFINE_PRCC_CLK(1, sdi0,         5,  5, &clk_sdmmcclk);
 338 static DEFINE_PRCC_CLK(1, msp1,         4,  4, &clk_msp1clk);
 339 static DEFINE_PRCC_CLK(1, msp0,         3,  3, &clk_msp02clk);
 340 static DEFINE_PRCC_CLK(1, i2c1,         2,  2, &clk_i2cclk);
 341 static DEFINE_PRCC_CLK(1, uart1,        1,  1, &clk_uartclk);
 342 static DEFINE_PRCC_CLK(1, uart0,        0,  0, &clk_uartclk);
 343
 344 /* Peripheral Cluster #2 */
 345 static DEFINE_PRCC_CLK(2, gpio1,        11, -1, NULL);
 346 static DEFINE_PRCC_CLK(2, ssitx,        10,  7, NULL);
 347 static DEFINE_PRCC_CLK(2, ssirx,         9,  6, NULL);
 348 static DEFINE_PRCC_CLK(2, spi0,         8, -1, NULL);
 349 static DEFINE_PRCC_CLK(2, sdi3,         7,  5, &clk_sdmmcclk);
 350 static DEFINE_PRCC_CLK(2, sdi1,         6,  4, &clk_sdmmcclk);
 351 static DEFINE_PRCC_CLK(2, msp2,         5,  3, &clk_msp02clk);
 352 static DEFINE_PRCC_CLK(2, sdi4,         4,  2, &clk_sdmmcclk);
 353 static DEFINE_PRCC_CLK(2, pwl,          3,  1, NULL);
 354 static DEFINE_PRCC_CLK(2, spi1,         2, -1, NULL);
 355 static DEFINE_PRCC_CLK(2, spi2,         1, -1, NULL);
 356 static DEFINE_PRCC_CLK(2, i2c3,         0,  0, &clk_i2cclk);
 357
 358 /* Peripheral Cluster #3 */
 359 static DEFINE_PRCC_CLK(3, gpio2,        8, -1, NULL);
 360 static DEFINE_PRCC_CLK(3, sdi5,         7,  7, &clk_sdmmcclk);
 361 static DEFINE_PRCC_CLK(3, uart2,        6,  6, &clk_uartclk);
 362 static DEFINE_PRCC_CLK(3, ske,          5,  5, &clk_32khz);
 363 static DEFINE_PRCC_CLK(3, sdi2,         4,  4, &clk_sdmmcclk);
 364 static DEFINE_PRCC_CLK(3, i2c0,         3,  3, &clk_i2cclk);
 365 static DEFINE_PRCC_CLK(3, ssp1,         2,  2, &clk_sspclk);
 366 static DEFINE_PRCC_CLK(3, ssp0,         1,  1, &clk_sspclk);
 367 static DEFINE_PRCC_CLK(3, fsmc,         0, -1, NULL);
 368
 369 /* Peripheral Cluster #4 is in the always on domain */
 370
 371 /* Peripheral Cluster #5 */
 372 static DEFINE_PRCC_CLK(5, gpio3,        1, -1, NULL);
 373 static DEFINE_PRCC_CLK(5, usb,          0,  0, NULL);
 374
 375 /* Peripheral Cluster #6 */
 376
 377 /* MTU ID in data */
 378 static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 8, -1, NULL, clk_mtu_get_rate, 1);
 379 static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 7, -1, NULL, clk_mtu_get_rate, 0);
 380 static DEFINE_PRCC_CLK(6, cfgreg,       6,  6, NULL);
 381 static DEFINE_PRCC_CLK(6, hash1,        5, -1, NULL);
 382 static DEFINE_PRCC_CLK(6, unipro,       4,  1, &clk_uniproclk);
 383 static DEFINE_PRCC_CLK(6, pka,          3, -1, NULL);
 384 static DEFINE_PRCC_CLK(6, hash0,        2, -1, NULL);
 385 static DEFINE_PRCC_CLK(6, cryp0,        1, -1, NULL);
 386 static DEFINE_PRCC_CLK(6, rng,  0,  0, &clk_rngclk);
 387
 388 static struct clk clk_dummy_apb_pclk = {
 389         .name = "apb_pclk",
 390 };
 391
 392 static struct clk_lookup u8500_clks[] = {
 393         CLK(dummy_apb_pclk, NULL,       "apb_pclk"),
 394
 395         /* Peripheral Cluster #1 */
 396         CLK(gpio0,      "gpio.0",       NULL),
 397         CLK(gpio0,      "gpio.1",       NULL),
 398         CLK(slimbus0,   "slimbus0",     NULL),
 399         CLK(i2c2,       "nmk-i2c.2",    NULL),
 400         CLK(sdi0,       "sdi0",         NULL),
 401         CLK(msp0,       "msp0",         NULL),
 402         CLK(i2c1,       "nmk-i2c.1",    NULL),
 403         CLK(uart1,      "uart1",        NULL),
 404         CLK(uart0,      "uart0",        NULL),
 405
 406         /* Peripheral Cluster #3 */
 407         CLK(gpio2,      "gpio.2",       NULL),
 408         CLK(gpio2,      "gpio.3",       NULL),
 409         CLK(gpio2,      "gpio.4",       NULL),
 410         CLK(gpio2,      "gpio.5",       NULL),
 411         CLK(sdi5,       "sdi5",         NULL),
 412         CLK(uart2,      "uart2",        NULL),
 413         CLK(ske,        "ske",          NULL),
 414         CLK(ske,        "nmk-ske-keypad",       NULL),
 415         CLK(sdi2,       "sdi2",         NULL),
 416         CLK(i2c0,       "nmk-i2c.0",    NULL),
 417         CLK(fsmc,       "fsmc",         NULL),
 418
 419         /* Peripheral Cluster #5 */
 420         CLK(gpio3,      "gpio.8",       NULL),
 421
 422         /* Peripheral Cluster #6 */
 423         CLK(hash1,      "hash1",        NULL),
 424         CLK(pka,        "pka",          NULL),
 425         CLK(hash0,      "hash0",        NULL),
 426         CLK(cryp0,      "cryp0",        NULL),
 427
 428         /* PRCMU level clock gating */
 429
 430         /* Bank 0 */
 431         CLK(svaclk,     "sva",          NULL),
 432         CLK(siaclk,     "sia",          NULL),
 433         CLK(sgaclk,     "sga",          NULL),
 434         CLK(slimclk,    "slim",         NULL),
 435         CLK(lcdclk,     "lcd",          NULL),
 436         CLK(bmlclk,     "bml",          NULL),
 437         CLK(hsitxclk,   "stm-hsi.0",    NULL),
 438         CLK(hsirxclk,   "stm-hsi.1",    NULL),
 439         CLK(hdmiclk,    "hdmi",         NULL),
 440         CLK(apeatclk,   "apeat",        NULL),
 441         CLK(apetraceclk,        "apetrace",     NULL),
 442         CLK(mcdeclk,    "mcde",         NULL),
 443         CLK(ipi2clk,    "ipi2",         NULL),
 444         CLK(dmaclk,     "dma40.0",      NULL),
 445         CLK(b2r2clk,    "b2r2",         NULL),
 446         CLK(tvclk,      "tv",           NULL),
 447
 448         /* Peripheral Cluster #1 */
 449         CLK(i2c4,       "nmk-i2c.4",    NULL),
 450         CLK(spi3,       "spi3",         NULL),
 451         CLK(msp1,       "msp1",         NULL),
 452
 453         /* Peripheral Cluster #2 */
 454         CLK(gpio1,      "gpio.6",       NULL),
 455         CLK(gpio1,      "gpio.7",       NULL),
 456         CLK(ssitx,      "ssitx",        NULL),
 457         CLK(ssirx,      "ssirx",        NULL),
 458         CLK(spi0,       "spi0",         NULL),
 459         CLK(sdi3,       "sdi3",         NULL),
 460         CLK(sdi1,       "sdi1",         NULL),
 461         CLK(msp2,       "msp2",         NULL),
 462         CLK(sdi4,       "sdi4",         NULL),
 463         CLK(pwl,        "pwl",          NULL),
 464         CLK(spi1,       "spi1",         NULL),
 465         CLK(spi2,       "spi2",         NULL),
 466         CLK(i2c3,       "nmk-i2c.3",    NULL),
 467
 468         /* Peripheral Cluster #3 */
 469         CLK(ssp1,       "ssp1",         NULL),
 470         CLK(ssp0,       "ssp0",         NULL),
 471
 472         /* Peripheral Cluster #5 */
 473         CLK(usb,        "musb-ux500.0", "usb"),
 474
 475         /* Peripheral Cluster #6 */
 476         CLK(mtu1,       "mtu1",         NULL),
 477         CLK(mtu0,       "mtu0",         NULL),
 478         CLK(cfgreg,     "cfgreg",       NULL),
 479         CLK(hash1,      "hash1",        NULL),
 480         CLK(unipro,     "unipro",       NULL),
 481         CLK(rng,        "rng",          NULL),
 482
 483         /* PRCMU level clock gating */
 484
 485         /* Bank 0 */
 486         CLK(uniproclk,  "uniproclk",    NULL),
 487         CLK(dsialtclk,  "dsialt",       NULL),
 488
 489         /* Bank 1 */
 490         CLK(rngclk,     "rng",          NULL),
 491         CLK(uiccclk,    "uicc",         NULL),
 492 };
 493
 494 #ifdef CONFIG_DEBUG_FS
 495 /*
 496  *      debugfs support to trace clock tree hierarchy and attributes with
 497  *      powerdebug
 498  */
 499 static struct dentry *clk_debugfs_root;
 500
 501 void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num)
 502 {
 503         while (num--) {
 504                 /* Check that the clock has not been already registered */
 505                 if (!(cl->clk->list.prev != cl->clk->list.next))
 506                         list_add_tail(&cl->clk->list, &clk_list);
 507
 508                 cl++;
 509         }
 510 }
 511
 512 static ssize_t usecount_dbg_read(struct file *file, char __user *buf,
 513                                                   size_t size, loff_t *off)
 514 {
 515         struct clk *clk = file->f_dentry->d_inode->i_private;
 516         char cusecount[128];
 517         unsigned int len;
 518
 519         len = sprintf(cusecount, "%u\n", clk->enabled);
 520         return simple_read_from_buffer(buf, size, off, cusecount, len);
 521 }
 522
 523 static ssize_t rate_dbg_read(struct file *file, char __user *buf,
 524                                           size_t size, loff_t *off)
 525 {
 526         struct clk *clk = file->f_dentry->d_inode->i_private;
 527         char crate[128];
 528         unsigned int rate;
 529         unsigned int len;
 530
 531         rate = clk_get_rate(clk);
 532         len = sprintf(crate, "%u\n", rate);
 533         return simple_read_from_buffer(buf, size, off, crate, len);
 534 }
 535
 536 static const struct file_operations usecount_fops = {
 537         .read = usecount_dbg_read,
 538 };
 539
 540 static const struct file_operations set_rate_fops = {
 541         .read = rate_dbg_read,
 542 };
 543
 544 static struct dentry *clk_debugfs_register_dir(struct clk *c,
 545                                                 struct dentry *p_dentry)
 546 {
 547         struct dentry *d, *clk_d;
 548         const char *p = c->name;
 549
 550         if (!p)
 551                 p = "BUG";
 552
 553         clk_d = debugfs_create_dir(p, p_dentry);
 554         if (!clk_d)
 555                 return NULL;
 556
 557         d = debugfs_create_file("usecount", S_IRUGO,
 558                                 clk_d, c, &usecount_fops);
 559         if (!d)
 560                 goto err_out;
 561         d = debugfs_create_file("rate", S_IRUGO,
 562                                 clk_d, c, &set_rate_fops);
 563         if (!d)
 564                 goto err_out;
 565         /*
 566          * TODO : not currently available in ux500
 567          * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags);
 568          * if (!d)
 569          *      goto err_out;
 570          */
 571
 572         return clk_d;
 573
 574 err_out:
 575         debugfs_remove_recursive(clk_d);
 576         return NULL;
 577 }
 578
 579 static int clk_debugfs_register_one(struct clk *c)
 580 {
 581         struct clk *pa = c->parent_periph;
 582         struct clk *bpa = c->parent_cluster;
 583
 584         if (!(bpa && !pa)) {
 585                 c->dent = clk_debugfs_register_dir(c,
 586                                 pa ? pa->dent : clk_debugfs_root);
 587                 if (!c->dent)
 588                         return -ENOMEM;
 589         }
 590
 591         if (bpa) {
 592                 c->dent_bus = clk_debugfs_register_dir(c,
 593                                 bpa->dent_bus ? bpa->dent_bus : bpa->dent);
 594                 if ((!c->dent_bus) &&  (c->dent)) {
 595                         debugfs_remove_recursive(c->dent);
 596                         c->dent = NULL;
 597                         return -ENOMEM;
 598                 }
 599         }
 600         return 0;
 601 }
 602
 603 static int clk_debugfs_register(struct clk *c)
 604 {
 605         int err;
 606         struct clk *pa = c->parent_periph;
 607         struct clk *bpa = c->parent_cluster;
 608
 609         if (pa && (!pa->dent && !pa->dent_bus)) {
 610                 err = clk_debugfs_register(pa);
 611                 if (err)
 612                         return err;
 613         }
 614
 615         if (bpa && (!bpa->dent && !bpa->dent_bus)) {
 616                 err = clk_debugfs_register(bpa);
 617                 if (err)
 618                         return err;
 619         }
 620
 621         if ((!c->dent) && (!c->dent_bus)) {
 622                 err = clk_debugfs_register_one(c);
 623                 if (err)
 624                         return err;
 625         }
 626         return 0;
 627 }
 628
 629 static int __init clk_debugfs_init(void)
 630 {
 631         struct clk *c;
 632         struct dentry *d;
 633         int err;
 634
 635         d = debugfs_create_dir("clock", NULL);
 636         if (!d)
 637                 return -ENOMEM;
 638         clk_debugfs_root = d;
 639
 640         list_for_each_entry(c, &clk_list, list) {
 641                 err = clk_debugfs_register(c);
 642                 if (err)
 643                         goto err_out;
 644         }
 645         return 0;
 646 err_out:
 647         debugfs_remove_recursive(clk_debugfs_root);
 648         return err;
 649 }
 650
 651 late_initcall(clk_debugfs_init);
 652 #endif /* defined(CONFIG_DEBUG_FS) */
 653
 654 unsigned long clk_smp_twd_rate = 500000000;
 655
 656 unsigned long clk_smp_twd_get_rate(struct clk *clk)
 657 {
 658         return clk_smp_twd_rate;
 659 }
 660
 661 static struct clk clk_smp_twd = {
 662         .get_rate = clk_smp_twd_get_rate,
 663         .name =  "smp_twd",
 664 };
 665
 666 static struct clk_lookup clk_smp_twd_lookup = {
 667         .dev_id = "smp_twd",
 668         .clk = &clk_smp_twd,
 669 };
 670
 671 #ifdef CONFIG_CPU_FREQ
 672
 673 static int clk_twd_cpufreq_transition(struct notifier_block *nb,
 674                                       unsigned long state, void *data)
 675 {
 676         struct cpufreq_freqs *f = data;
 677
 678         if (state == CPUFREQ_PRECHANGE) {
 679                 /* Save frequency in simple Hz */
 680                 clk_smp_twd_rate = (f->new * 1000) / 2;
 681         }
 682
 683         return NOTIFY_OK;
 684 }
 685
 686 static struct notifier_block clk_twd_cpufreq_nb = {
 687         .notifier_call = clk_twd_cpufreq_transition,
 688 };
 689
 690 static int clk_init_smp_twd_cpufreq(void)
 691 {
 692         return cpufreq_register_notifier(&clk_twd_cpufreq_nb,
 693                                   CPUFREQ_TRANSITION_NOTIFIER);
 694 }
 695 late_initcall(clk_init_smp_twd_cpufreq);
 696
 697 #endif
 698
 699 int __init clk_init(void)
 700 {
 701         if (cpu_is_u5500()) {
 702                 /* Clock tree for U5500 not implemented yet */
 703                 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
 704                 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
 705                 clk_uartclk.rate = 36360000;
 706                 clk_sdmmcclk.rate = 99900000;
 707         }
 708
 709         clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
 710         clkdev_add(&clk_smp_twd_lookup);
 711
 712 #ifdef CONFIG_DEBUG_FS
 713         clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
 714 #endif
 715         return 0;
 716 }