arch/arm/mach-ux500/cpu-db8500.c

   1 /*
   2  * Copyright (C) 2008-2009 ST-Ericsson SA
   3  *
   4  * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2, as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11 #include <linux/types.h>
  12 #include <linux/init.h>
  13 #include <linux/device.h>
  14 #include <linux/amba/bus.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/io.h>
  19 #include <linux/mfd/abx500/ab8500.h>
  20 #include <linux/mfd/dbx500-prcmu.h>
  21 #include <linux/of.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/regulator/machine.h>
  24 #include <linux/platform_data/pinctrl-nomadik.h>
  25 #include <linux/random.h>
  26
  27 #include <asm/pmu.h>
  28 #include <asm/mach/map.h>
  29 #include <asm/mach/arch.h>
  30
  31 #include <mach/hardware.h>
  32 #include <mach/setup.h>
  33 #include <mach/devices.h>
  34 #include <mach/db8500-regs.h>
  35 #include <mach/irqs.h>
  36
  37 #include "devices-db8500.h"
  38 #include "ste-dma40-db8500.h"
  39
  40 #include "board-mop500.h"
  41 #include "id.h"
  42
  43 /* minimum static i/o mapping required to boot U8500 platforms */
  44 static struct map_desc u8500_uart_io_desc[] __initdata = {
  45         __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
  46         __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
  47 };
  48 /*  U8500 and U9540 common io_desc */
  49 static struct map_desc u8500_common_io_desc[] __initdata = {
  50         /* SCU base also covers GIC CPU BASE and TWD with its 4K page */
  51         __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
  52         __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
  53         __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K),
  54         __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
  55         __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
  56
  57         __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K),
  58         __IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K),
  59         __IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K),
  60         __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K),
  61         __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K),
  62
  63         __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
  64         __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
  65         __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
  66         __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
  67 };
  68
  69 /* U8500 IO map specific description */
  70 static struct map_desc u8500_io_desc[] __initdata = {
  71         __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
  72         __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
  73
  74 };
  75
  76 /* U9540 IO map specific description */
  77 static struct map_desc u9540_io_desc[] __initdata = {
  78         __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K + SZ_8K),
  79         __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K + SZ_8K),
  80 };
  81
  82 void __init u8500_map_io(void)
  83 {
  84         /*
  85          * Map the UARTs early so that the DEBUG_LL stuff continues to work.
  86          */
  87         iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));
  88
  89         ux500_map_io();
  90
  91         iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));
  92
  93         if (cpu_is_ux540_family())
  94                 iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
  95         else
  96                 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
  97
  98         _PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
  99 }
 100
 101 static struct resource db8500_pmu_resources[] = {
 102         [0] = {
 103                 .start          = IRQ_DB8500_PMU,
 104                 .end            = IRQ_DB8500_PMU,
 105                 .flags          = IORESOURCE_IRQ,
 106         },
 107 };
 108
 109 /*
 110  * The PMU IRQ lines of two cores are wired together into a single interrupt.
 111  * Bounce the interrupt to the other core if it's not ours.
 112  */
 113 static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler)
 114 {
 115         irqreturn_t ret = handler(irq, dev);
 116         int other = !smp_processor_id();
 117
 118         if (ret == IRQ_NONE && cpu_online(other))
 119                 irq_set_affinity(irq, cpumask_of(other));
 120
 121         /*
 122          * We should be able to get away with the amount of IRQ_NONEs we give,
 123          * while still having the spurious IRQ detection code kick in if the
 124          * interrupt really starts hitting spuriously.
 125          */
 126         return ret;
 127 }
 128
 129 struct arm_pmu_platdata db8500_pmu_platdata = {
 130         .handle_irq             = db8500_pmu_handler,
 131 };
 132
 133 static struct platform_device db8500_pmu_device = {
 134         .name                   = "arm-pmu",
 135         .id                     = -1,
 136         .num_resources          = ARRAY_SIZE(db8500_pmu_resources),
 137         .resource               = db8500_pmu_resources,
 138         .dev.platform_data      = &db8500_pmu_platdata,
 139 };
 140
 141 static struct platform_device *platform_devs[] __initdata = {
 142         &u8500_dma40_device,
 143         &db8500_pmu_device,
 144 };
 145
 146 static resource_size_t __initdata db8500_gpio_base[] = {
 147         U8500_GPIOBANK0_BASE,
 148         U8500_GPIOBANK1_BASE,
 149         U8500_GPIOBANK2_BASE,
 150         U8500_GPIOBANK3_BASE,
 151         U8500_GPIOBANK4_BASE,
 152         U8500_GPIOBANK5_BASE,
 153         U8500_GPIOBANK6_BASE,
 154         U8500_GPIOBANK7_BASE,
 155         U8500_GPIOBANK8_BASE,
 156 };
 157
 158 static void __init db8500_add_gpios(struct device *parent)
 159 {
 160         struct nmk_gpio_platform_data pdata = {
 161                 .supports_sleepmode = true,
 162         };
 163
 164         dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
 165                          IRQ_DB8500_GPIO0, &pdata);
 166         dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
 167 }
 168
 169 static int usb_db8500_rx_dma_cfg[] = {
 170         DB8500_DMA_DEV38_USB_OTG_IEP_1_9,
 171         DB8500_DMA_DEV37_USB_OTG_IEP_2_10,
 172         DB8500_DMA_DEV36_USB_OTG_IEP_3_11,
 173         DB8500_DMA_DEV19_USB_OTG_IEP_4_12,
 174         DB8500_DMA_DEV18_USB_OTG_IEP_5_13,
 175         DB8500_DMA_DEV17_USB_OTG_IEP_6_14,
 176         DB8500_DMA_DEV16_USB_OTG_IEP_7_15,
 177         DB8500_DMA_DEV39_USB_OTG_IEP_8
 178 };
 179
 180 static int usb_db8500_tx_dma_cfg[] = {
 181         DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
 182         DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
 183         DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
 184         DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
 185         DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
 186         DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
 187         DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
 188         DB8500_DMA_DEV39_USB_OTG_OEP_8
 189 };
 190
 191 static const char *db8500_read_soc_id(void)
 192 {
 193         void __iomem *uid = __io_address(U8500_BB_UID_BASE);
 194
 195         /* Throw these device-specific numbers into the entropy pool */
 196         add_device_randomness(uid, 0x14);
 197         return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
 198                          readl((u32 *)uid+1),
 199                          readl((u32 *)uid+1), readl((u32 *)uid+2),
 200                          readl((u32 *)uid+3), readl((u32 *)uid+4));
 201 }
 202
 203 static struct device * __init db8500_soc_device_init(void)
 204 {
 205         const char *soc_id = db8500_read_soc_id();
 206
 207         return ux500_soc_device_init(soc_id);
 208 }
 209
 210 /*
 211  * This function is called from the board init
 212  */
 213 struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500)
 214 {
 215         struct device *parent;
 216         int i;
 217
 218         parent = db8500_soc_device_init();
 219
 220         db8500_add_rtc(parent);
 221         db8500_add_gpios(parent);
 222         db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
 223
 224         for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
 225                 platform_devs[i]->dev.parent = parent;
 226
 227         db8500_prcmu_device.dev.platform_data = ab8500;
 228
 229         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
 230
 231         return parent;
 232 }
 233
 234 #ifdef CONFIG_MACH_UX500_DT
 235
 236 /* TODO: Once all pieces are DT:ed, remove completely. */
 237 static struct device * __init u8500_of_init_devices(void)
 238 {
 239         struct device *parent = db8500_soc_device_init();
 240
 241         db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
 242
 243         u8500_dma40_device.dev.parent = parent;
 244
 245         /*
 246          * Devices to be DT:ed:
 247          *   u8500_dma40_device  = todo
 248          *   db8500_pmu_device   = done
 249          *   db8500_prcmu_device = done
 250          */
 251         platform_device_register(&u8500_dma40_device);
 252
 253         return parent;
 254 }
 255
 256 static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 257         /* Requires call-back bindings. */
 258         OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
 259         /* Requires DMA bindings. */
 260         OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
 261         OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
 262         OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
 263         OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
 264         OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
 265         OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),
 266         OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  &mop500_sdi2_data),
 267         OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  &mop500_sdi4_data),
 268         /* Requires clock name bindings. */
 269         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
 270         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
 271         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
 272         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
 273         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
 274         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
 275         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
 276         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
 277         OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
 278         OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
 279         OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
 280         OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
 281         OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
 282         OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
 283         OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
 284                         &db8500_prcmu_pdata),
 285         /* Requires device name bindings. */
 286         OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
 287                 "pinctrl-db8500", NULL),
 288         /* Requires clock name and DMA bindings. */
 289         OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
 290                 "ux500-msp-i2s.0", &msp0_platform_data),
 291         OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
 292                 "ux500-msp-i2s.1", &msp1_platform_data),
 293         OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
 294                 "ux500-msp-i2s.2", &msp2_platform_data),
 295         OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
 296                 "ux500-msp-i2s.3", &msp3_platform_data),
 297         {},
 298 };
 299
 300 static const struct of_device_id u8500_local_bus_nodes[] = {
 301         /* only create devices below soc node */
 302         { .compatible = "stericsson,db8500", },
 303         { .compatible = "stericsson,db8500-prcmu", },
 304         { .compatible = "simple-bus"},
 305         { },
 306 };
 307
 308 static void __init u8500_init_machine(void)
 309 {
 310         struct device *parent = NULL;
 311
 312         /* Pinmaps must be in place before devices register */
 313         if (of_machine_is_compatible("st-ericsson,mop500"))
 314                 mop500_pinmaps_init();
 315         else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
 316                 snowball_pinmaps_init();
 317                 mop500_snowball_ethernet_clock_enable();
 318         } else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
 319                 hrefv60_pinmaps_init();
 320         else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
 321                 /* TODO: Add pinmaps for ccu9540 board. */
 322
 323         /* TODO: Export SoC, USB, cpu-freq and DMA40 */
 324         parent = u8500_of_init_devices();
 325
 326         /* automatically probe child nodes of db8500 device */
 327         of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
 328 }
 329
 330 static const char * stericsson_dt_platform_compat[] = {
 331         "st-ericsson,u8500",
 332         "st-ericsson,u8540",
 333         "st-ericsson,u9500",
 334         "st-ericsson,u9540",
 335         NULL,
 336 };
 337
 338 DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)")
 339         .smp            = smp_ops(ux500_smp_ops),
 340         .map_io         = u8500_map_io,
 341         .init_irq       = ux500_init_irq,
 342         /* we re-use nomadik timer here */
 343         .init_time      = ux500_timer_init,
 344         .init_machine   = u8500_init_machine,
 345         .init_late      = NULL,
 346         .dt_compat      = stericsson_dt_platform_compat,
 347 MACHINE_END
 348
 349 #endif