2 * Low-level IRQ helper macros for U8500 platforms
4 * Copyright (C) 2009 ST-Ericsson.
6 * This file is a copy of ARM Realview platform.
7 * -just satisfied checkpatch script.
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
13 #include <mach/hardware.h>
14 #include <asm/hardware/gic.h>
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =IO_ADDRESS(UX500_GIC_CPU_BASE)
23 .macro arch_ret_to_user, tmp1, tmp2
27 * The interrupt numbering scheme is defined in the
28 * interrupt controller spec. To wit:
30 * Interrupts 0-15 are IPI
32 * 29-31 are local. We allow 30 to be used for the watchdog.
34 * 1021-1022 are reserved
35 * 1023 is "spurious" (no interrupt)
37 * For now, we ignore all local interrupts so only return an
38 * interrupt if it's between 30 and 1020. The test_for_ipi
39 * routine below will pick up on IPIs.
41 * A simple read from the controller will tell us the number
42 * of the highest priority enabled interrupt. We then just
43 * need to check whether it is in the valid range for an
44 * IRQ (30-1020 inclusive).
47 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
49 /* bits 12-10 = src CPU, 9-0 = int # */
50 ldr \irqstat, [\base, #GIC_CPU_INTACK]
54 bic \irqnr, \irqstat, #0x1c00
63 /* We assume that irqstat (the raw value of the IRQ
64 * acknowledge register) is preserved from the macro above.
65 * If there is an IPI, we immediately signal end of
66 * interrupt on the controller, since this requires the
67 * original irqstat value which we won't easily be able
71 .macro test_for_ipi, irqnr, irqstat, base, tmp
72 bic \irqnr, \irqstat, #0x1c00
74 strcc \irqstat, [\base, #GIC_CPU_EOI]
78 /* As above, this assumes that irqstat and base
82 .macro test_for_ltirq, irqnr, irqstat, base, tmp
83 bic \irqnr, \irqstat, #0x1c00
87 streq \irqstat, [\base, #GIC_CPU_EOI]