2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
5 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
6 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
8 * License Terms: GNU General Public License v2
13 #ifndef __MACH_PRCMU_REGS_H
14 #define __MACH_PRCMU_REGS_H
16 #include <mach/hardware.h>
18 #define _PRCMU_BASE IO_ADDRESS(U8500_PRCMU_BASE)
20 #define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118)
21 #define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114)
22 #define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98)
23 #define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0)
24 #define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4)
25 #define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0)
26 #define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c)
27 #define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308)
29 /* ARM WFI Standby signal register */
30 #define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130)
31 #define PRCMU_IOCR (_PRCMU_BASE + 0x310)
33 /* CPU mailbox registers */
34 #define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc)
35 #define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100)
36 #define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104)
38 /* Dual A9 core interrupt management unit registers */
39 #define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328)
40 #define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c)
41 #define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c)
42 #define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120)
43 #define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124)
44 #define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128)
45 #define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C)
46 #define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260)
47 #define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264)
48 #define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268)
49 #define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C)
51 #define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334)
52 #define ARM_WAKEUP_MODEM 0x1
54 #define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C)
55 #define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494)
56 #define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174)
58 #define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148)
59 #define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150)
60 #define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158)
61 #define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160)
62 #define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168)
63 #define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484)
64 #define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488)
65 #define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018)
67 /* System reset register */
68 #define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228)
70 /* Level shifter and clamp control registers */
71 #define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420)
72 #define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424)
74 /* PRCMU clock/PLL/reset registers */
75 #define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500)
76 #define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504)
77 #define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044)
78 #define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064)
79 #define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058)
80 #define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07c)
81 #define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530)
82 #define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C)
83 #define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4)
84 #define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8)
86 /* ePOD and memory power signal control registers */
87 #define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410)
88 #define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304)
90 /* Debug power control unit registers */
91 #define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254)
93 /* Miscellaneous unit registers */
94 #define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324)
96 #endif /* __MACH_PRCMU_REGS_H */