2 * linux/arch/arm/mach-versatile/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
29 #include <linux/amba/pl061.h>
30 #include <linux/amba/mmci.h>
33 #include <asm/clkdev.h>
34 #include <asm/system.h>
37 #include <asm/hardware/arm_timer.h>
38 #include <asm/hardware/icst.h>
39 #include <asm/hardware/vic.h>
40 #include <asm/mach-types.h>
42 #include <asm/mach/arch.h>
43 #include <asm/mach/flash.h>
44 #include <asm/mach/irq.h>
45 #include <asm/mach/time.h>
46 #include <asm/mach/map.h>
47 #include <mach/clkdev.h>
48 #include <mach/hardware.h>
49 #include <mach/platform.h>
50 #include <plat/timer-sp.h>
55 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
58 * Setup a VA for the Versatile Vectored Interrupt Controller.
60 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
61 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
63 static void sic_mask_irq(unsigned int irq)
66 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
69 static void sic_unmask_irq(unsigned int irq)
72 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
75 static struct irq_chip sic_chip = {
79 .unmask = sic_unmask_irq,
83 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
85 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
88 do_bad_IRQ(irq, desc);
93 irq = ffs(status) - 1;
94 status &= ~(1 << irq);
98 generic_handle_irq(irq);
103 #define IRQ_MMCI0A IRQ_VICSOURCE22
104 #define IRQ_AACI IRQ_VICSOURCE24
105 #define IRQ_ETH IRQ_VICSOURCE25
106 #define PIC_MASK 0xFFD00000
108 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
109 #define IRQ_AACI IRQ_SIC_AACI
110 #define IRQ_ETH IRQ_SIC_ETH
114 void __init versatile_init_irq(void)
118 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
120 set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
122 /* Do second interrupt controller */
123 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
125 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
126 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
127 set_irq_chip(i, &sic_chip);
128 set_irq_handler(i, handle_level_irq);
129 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
134 * Interrupts on secondary controller from 0 to 8 are routed to
136 * Interrupts from 21 to 31 are routed directly to the VIC on
137 * the corresponding number on primary controller. This is controlled
138 * by setting PIC_ENABLEx.
140 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
143 static struct map_desc versatile_io_desc[] __initdata = {
145 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
146 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
150 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
151 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
155 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
156 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
160 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
161 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
165 #ifdef CONFIG_MACH_VERSATILE_AB
167 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
168 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
172 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
173 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
178 #ifdef CONFIG_DEBUG_LL
180 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
181 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
188 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
189 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
193 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
194 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
195 .length = VERSATILE_PCI_BASE_SIZE,
198 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
199 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
200 .length = VERSATILE_PCI_CFG_BASE_SIZE,
205 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
206 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
210 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
211 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
215 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
216 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
224 void __init versatile_map_io(void)
226 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
230 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
232 static int versatile_flash_init(void)
236 val = __raw_readl(VERSATILE_FLASHCTRL);
237 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
238 __raw_writel(val, VERSATILE_FLASHCTRL);
243 static void versatile_flash_exit(void)
247 val = __raw_readl(VERSATILE_FLASHCTRL);
248 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
249 __raw_writel(val, VERSATILE_FLASHCTRL);
252 static void versatile_flash_set_vpp(int on)
256 val = __raw_readl(VERSATILE_FLASHCTRL);
258 val |= VERSATILE_FLASHPROG_FLVPPEN;
260 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
261 __raw_writel(val, VERSATILE_FLASHCTRL);
264 static struct flash_platform_data versatile_flash_data = {
265 .map_name = "cfi_probe",
267 .init = versatile_flash_init,
268 .exit = versatile_flash_exit,
269 .set_vpp = versatile_flash_set_vpp,
272 static struct resource versatile_flash_resource = {
273 .start = VERSATILE_FLASH_BASE,
274 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
275 .flags = IORESOURCE_MEM,
278 static struct platform_device versatile_flash_device = {
282 .platform_data = &versatile_flash_data,
285 .resource = &versatile_flash_resource,
288 static struct resource smc91x_resources[] = {
290 .start = VERSATILE_ETH_BASE,
291 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
292 .flags = IORESOURCE_MEM,
297 .flags = IORESOURCE_IRQ,
301 static struct platform_device smc91x_device = {
304 .num_resources = ARRAY_SIZE(smc91x_resources),
305 .resource = smc91x_resources,
308 static struct resource versatile_i2c_resource = {
309 .start = VERSATILE_I2C_BASE,
310 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
311 .flags = IORESOURCE_MEM,
314 static struct platform_device versatile_i2c_device = {
315 .name = "versatile-i2c",
318 .resource = &versatile_i2c_resource,
321 static struct i2c_board_info versatile_i2c_board_info[] = {
323 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
327 static int __init versatile_i2c_init(void)
329 return i2c_register_board_info(0, versatile_i2c_board_info,
330 ARRAY_SIZE(versatile_i2c_board_info));
332 arch_initcall(versatile_i2c_init);
334 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
336 unsigned int mmc_status(struct device *dev)
338 struct amba_device *adev = container_of(dev, struct amba_device, dev);
341 if (adev->res.start == VERSATILE_MMCI0_BASE)
346 return readl(VERSATILE_SYSMCI) & mask;
349 static struct mmci_platform_data mmc0_plat_data = {
350 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
351 .status = mmc_status,
359 static const struct icst_params versatile_oscvco_params = {
361 .vco_max = ICST307_VCO_MAX,
362 .vco_min = ICST307_VCO_MIN,
367 .s2div = icst307_s2div,
368 .idx2s = icst307_idx2s,
371 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
373 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
374 void __iomem *sys_lock = sys + VERSATILE_SYS_LOCK_OFFSET;
377 val = readl(sys + clk->oscoff) & ~0x7ffff;
378 val |= vco.v | (vco.r << 9) | (vco.s << 16);
380 writel(0xa05f, sys_lock);
381 writel(val, sys + clk->oscoff);
385 static struct clk osc4_clk = {
386 .params = &versatile_oscvco_params,
387 .oscoff = VERSATILE_SYS_OSCCLCD_OFFSET,
388 .setvco = versatile_oscvco_set,
392 * These are fixed clocks.
394 static struct clk ref24_clk = {
398 static struct clk_lookup lookups[] = {
432 #define SYS_CLCD_MODE_MASK (3 << 0)
433 #define SYS_CLCD_MODE_888 (0 << 0)
434 #define SYS_CLCD_MODE_5551 (1 << 0)
435 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
436 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
437 #define SYS_CLCD_NLCDIOON (1 << 2)
438 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
439 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
440 #define SYS_CLCD_ID_MASK (0x1f << 8)
441 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
442 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
443 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
444 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
445 #define SYS_CLCD_ID_VGA (0x1f << 8)
447 static struct clcd_panel vga = {
461 .vmode = FB_VMODE_NONINTERLACED,
465 .tim2 = TIM2_BCD | TIM2_IPC,
466 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
470 static struct clcd_panel sanyo_3_8_in = {
472 .name = "Sanyo QVGA",
484 .vmode = FB_VMODE_NONINTERLACED,
489 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
493 static struct clcd_panel sanyo_2_5_in = {
495 .name = "Sanyo QVGA Portrait",
506 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
507 .vmode = FB_VMODE_NONINTERLACED,
511 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
512 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
516 static struct clcd_panel epson_2_2_in = {
518 .name = "Epson QCIF",
530 .vmode = FB_VMODE_NONINTERLACED,
534 .tim2 = TIM2_BCD | TIM2_IPC,
535 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
540 * Detect which LCD panel is connected, and return the appropriate
541 * clcd_panel structure. Note: we do not have any information on
542 * the required timings for the 8.4in panel, so we presently assume
545 static struct clcd_panel *versatile_clcd_panel(void)
547 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
548 struct clcd_panel *panel = &vga;
551 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
552 if (val == SYS_CLCD_ID_SANYO_3_8)
553 panel = &sanyo_3_8_in;
554 else if (val == SYS_CLCD_ID_SANYO_2_5)
555 panel = &sanyo_2_5_in;
556 else if (val == SYS_CLCD_ID_EPSON_2_2)
557 panel = &epson_2_2_in;
558 else if (val == SYS_CLCD_ID_VGA)
561 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
570 * Disable all display connectors on the interface module.
572 static void versatile_clcd_disable(struct clcd_fb *fb)
574 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
577 val = readl(sys_clcd);
578 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
579 writel(val, sys_clcd);
581 #ifdef CONFIG_MACH_VERSATILE_AB
583 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
585 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
586 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
589 ctrl = readl(versatile_ib2_ctrl);
591 writel(ctrl, versatile_ib2_ctrl);
597 * Enable the relevant connector on the interface module.
599 static void versatile_clcd_enable(struct clcd_fb *fb)
601 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
604 val = readl(sys_clcd);
605 val &= ~SYS_CLCD_MODE_MASK;
607 switch (fb->fb.var.green.length) {
609 val |= SYS_CLCD_MODE_5551;
612 val |= SYS_CLCD_MODE_565_RLSB;
615 val |= SYS_CLCD_MODE_888;
622 writel(val, sys_clcd);
625 * And now enable the PSUs
627 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
628 writel(val, sys_clcd);
630 #ifdef CONFIG_MACH_VERSATILE_AB
632 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
634 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
635 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
638 ctrl = readl(versatile_ib2_ctrl);
640 writel(ctrl, versatile_ib2_ctrl);
645 static unsigned long framesize = SZ_1M;
647 static int versatile_clcd_setup(struct clcd_fb *fb)
651 fb->panel = versatile_clcd_panel();
653 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
655 if (!fb->fb.screen_base) {
656 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
660 fb->fb.fix.smem_start = dma;
661 fb->fb.fix.smem_len = framesize;
666 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
668 return dma_mmap_writecombine(&fb->dev->dev, vma,
670 fb->fb.fix.smem_start,
671 fb->fb.fix.smem_len);
674 static void versatile_clcd_remove(struct clcd_fb *fb)
676 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
677 fb->fb.screen_base, fb->fb.fix.smem_start);
680 static struct clcd_board clcd_plat_data = {
682 .check = clcdfb_check,
683 .decode = clcdfb_decode,
684 .disable = versatile_clcd_disable,
685 .enable = versatile_clcd_enable,
686 .setup = versatile_clcd_setup,
687 .mmap = versatile_clcd_mmap,
688 .remove = versatile_clcd_remove,
691 static struct pl061_platform_data gpio0_plat_data = {
693 .irq_base = IRQ_GPIO0_START,
696 static struct pl061_platform_data gpio1_plat_data = {
698 .irq_base = IRQ_GPIO1_START,
701 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
702 #define AACI_DMA { 0x80, 0x81 }
703 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
704 #define MMCI0_DMA { 0x84, 0 }
705 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
706 #define KMI0_DMA { 0, 0 }
707 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
708 #define KMI1_DMA { 0, 0 }
711 * These devices are connected directly to the multi-layer AHB switch
713 #define SMC_IRQ { NO_IRQ, NO_IRQ }
714 #define SMC_DMA { 0, 0 }
715 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
716 #define MPMC_DMA { 0, 0 }
717 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
718 #define CLCD_DMA { 0, 0 }
719 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
720 #define DMAC_DMA { 0, 0 }
723 * These devices are connected via the core APB bridge
725 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
726 #define SCTL_DMA { 0, 0 }
727 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
728 #define WATCHDOG_DMA { 0, 0 }
729 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
730 #define GPIO0_DMA { 0, 0 }
731 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
732 #define GPIO1_DMA { 0, 0 }
733 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
734 #define RTC_DMA { 0, 0 }
737 * These devices are connected via the DMA APB bridge
739 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
740 #define SCI_DMA { 7, 6 }
741 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
742 #define UART0_DMA { 15, 14 }
743 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
744 #define UART1_DMA { 13, 12 }
745 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
746 #define UART2_DMA { 11, 10 }
747 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
748 #define SSP_DMA { 9, 8 }
750 /* FPGA Primecells */
751 AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
752 AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
753 AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
754 AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
756 /* DevChip Primecells */
757 AMBA_DEVICE(smc, "dev:00", SMC, NULL);
758 AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
759 AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
760 AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
761 AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
762 AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
763 AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
764 AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
765 AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
766 AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
767 AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
768 AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
769 AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
770 AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
772 static struct amba_device *amba_devs[] __initdata = {
794 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
796 static void versatile_leds_event(led_event_t ledevt)
801 local_irq_save(flags);
802 val = readl(VA_LEDS_BASE);
806 val = val & ~VERSATILE_SYS_LED0;
810 val = val | VERSATILE_SYS_LED0;
814 val = val ^ VERSATILE_SYS_LED1;
825 writel(val, VA_LEDS_BASE);
826 local_irq_restore(flags);
828 #endif /* CONFIG_LEDS */
830 void __init versatile_init(void)
834 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
836 platform_device_register(&versatile_flash_device);
837 platform_device_register(&versatile_i2c_device);
838 platform_device_register(&smc91x_device);
840 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
841 struct amba_device *d = amba_devs[i];
842 amba_device_register(d, &iomem_resource);
846 leds_event = versatile_leds_event;
851 * Where is the timer (VA)?
853 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
854 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
855 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
856 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
859 * Set up timer interrupt, and return the current time in seconds.
861 static void __init versatile_timer_init(void)
866 * set clock frequency:
867 * VERSATILE_REFCLK is 32KHz
868 * VERSATILE_TIMCLK is 1MHz
870 val = readl(__io_address(VERSATILE_SCTL_BASE));
871 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
872 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
873 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
874 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
875 __io_address(VERSATILE_SCTL_BASE));
878 * Initialise to a known state (all timers off)
880 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
881 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
882 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
883 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
885 sp804_clocksource_init(TIMER3_VA_BASE);
886 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1);
889 struct sys_timer versatile_timer = {
890 .init = versatile_timer_init,