arch/arm/mach-vexpress/ct-ca9x4.c

   1 /*
   2  * Versatile Express Core Tile Cortex A9x4 Support
   3  */
   4 #include <linux/init.h>
   5 #include <linux/gfp.h>
   6 #include <linux/device.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/amba/bus.h>
  10 #include <linux/amba/clcd.h>
  11 #include <linux/clkdev.h>
  12
  13 #include <asm/hardware/arm_timer.h>
  14 #include <asm/hardware/cache-l2x0.h>
  15 #include <asm/hardware/gic.h>
  16 #include <asm/smp_scu.h>
  17 #include <asm/smp_twd.h>
  18
  19 #include <mach/ct-ca9x4.h>
  20
  21 #include <asm/hardware/timer-sp.h>
  22
  23 #include <asm/mach/map.h>
  24 #include <asm/mach/time.h>
  25
  26 #include "core.h"
  27
  28 #include <mach/motherboard.h>
  29
  30 #include <plat/clcd.h>
  31
  32 static struct map_desc ct_ca9x4_io_desc[] __initdata = {
  33         {
  34                 .virtual        = V2T_PERIPH,
  35                 .pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
  36                 .length         = SZ_8K,
  37                 .type           = MT_DEVICE,
  38         },
  39 };
  40
  41 static void __init ct_ca9x4_map_io(void)
  42 {
  43         iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
  44 }
  45
  46 #ifdef CONFIG_HAVE_ARM_TWD
  47 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
  48
  49 static void __init ca9x4_twd_init(void)
  50 {
  51         int err = twd_local_timer_register(&twd_local_timer);
  52         if (err)
  53                 pr_err("twd_local_timer_register failed %d\n", err);
  54 }
  55 #else
  56 #define ca9x4_twd_init()        do {} while(0)
  57 #endif
  58
  59 static void __init ct_ca9x4_init_irq(void)
  60 {
  61         gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
  62                  ioremap(A9_MPCORE_GIC_CPU, SZ_256));
  63         ca9x4_twd_init();
  64 }
  65
  66 static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
  67 {
  68         u32 site = v2m_get_master_site();
  69
  70         /*
  71          * Old firmware was using the "site" component of the command
  72          * to control the DVI muxer (while it should be always 0 ie. MB).
  73          * Newer firmware uses the data register. Keep both for compatibility.
  74          */
  75         v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE(site), site);
  76         v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE(SYS_CFG_SITE_MB), 2);
  77 }
  78
  79 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
  80 {
  81         unsigned long framesize = 1024 * 768 * 2;
  82
  83         fb->panel = versatile_clcd_get_panel("XVGA");
  84         if (!fb->panel)
  85                 return -EINVAL;
  86
  87         return versatile_clcd_setup_dma(fb, framesize);
  88 }
  89
  90 static struct clcd_board ct_ca9x4_clcd_data = {
  91         .name           = "CT-CA9X4",
  92         .caps           = CLCD_CAP_5551 | CLCD_CAP_565,
  93         .check          = clcdfb_check,
  94         .decode         = clcdfb_decode,
  95         .enable         = ct_ca9x4_clcd_enable,
  96         .setup          = ct_ca9x4_clcd_setup,
  97         .mmap           = versatile_clcd_mmap_dma,
  98         .remove         = versatile_clcd_remove_dma,
  99 };
 100
 101 static AMBA_AHB_DEVICE(clcd, "ct:clcd", 0, CT_CA9X4_CLCDC, IRQ_CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
 102 static AMBA_APB_DEVICE(dmc, "ct:dmc", 0, CT_CA9X4_DMC, IRQ_CT_CA9X4_DMC, NULL);
 103 static AMBA_APB_DEVICE(smc, "ct:smc", 0, CT_CA9X4_SMC, IRQ_CT_CA9X4_SMC, NULL);
 104 static AMBA_APB_DEVICE(gpio, "ct:gpio", 0, CT_CA9X4_GPIO, IRQ_CT_CA9X4_GPIO, NULL);
 105
 106 static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
 107         &clcd_device,
 108         &dmc_device,
 109         &smc_device,
 110         &gpio_device,
 111 };
 112
 113
 114 static struct v2m_osc ct_osc1 = {
 115         .osc = 1,
 116         .rate_min = 10000000,
 117         .rate_max = 80000000,
 118         .rate_default = 23750000,
 119 };
 120
 121 static struct resource pmu_resources[] = {
 122         [0] = {
 123                 .start  = IRQ_CT_CA9X4_PMU_CPU0,
 124                 .end    = IRQ_CT_CA9X4_PMU_CPU0,
 125                 .flags  = IORESOURCE_IRQ,
 126         },
 127         [1] = {
 128                 .start  = IRQ_CT_CA9X4_PMU_CPU1,
 129                 .end    = IRQ_CT_CA9X4_PMU_CPU1,
 130                 .flags  = IORESOURCE_IRQ,
 131         },
 132         [2] = {
 133                 .start  = IRQ_CT_CA9X4_PMU_CPU2,
 134                 .end    = IRQ_CT_CA9X4_PMU_CPU2,
 135                 .flags  = IORESOURCE_IRQ,
 136         },
 137         [3] = {
 138                 .start  = IRQ_CT_CA9X4_PMU_CPU3,
 139                 .end    = IRQ_CT_CA9X4_PMU_CPU3,
 140                 .flags  = IORESOURCE_IRQ,
 141         },
 142 };
 143
 144 static struct platform_device pmu_device = {
 145         .name           = "arm-pmu",
 146         .id             = -1,
 147         .num_resources  = ARRAY_SIZE(pmu_resources),
 148         .resource       = pmu_resources,
 149 };
 150
 151 static void __init ct_ca9x4_init(void)
 152 {
 153         int i;
 154         struct clk *clk;
 155
 156 #ifdef CONFIG_CACHE_L2X0
 157         void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
 158
 159         /* set RAM latencies to 1 cycle for this core tile. */
 160         writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
 161         writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
 162
 163         l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
 164 #endif
 165
 166         ct_osc1.site = v2m_get_master_site();
 167         clk = v2m_osc_register("ct:osc1", &ct_osc1);
 168         clk_register_clkdev(clk, NULL, "ct:clcd");
 169
 170         for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
 171                 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
 172
 173         platform_device_register(&pmu_device);
 174 }
 175
 176 #ifdef CONFIG_SMP
 177 static void *ct_ca9x4_scu_base __initdata;
 178
 179 static void __init ct_ca9x4_init_cpu_map(void)
 180 {
 181         int i, ncores;
 182
 183         ct_ca9x4_scu_base = ioremap(A9_MPCORE_SCU, SZ_128);
 184         if (WARN_ON(!ct_ca9x4_scu_base))
 185                 return;
 186
 187         ncores = scu_get_core_count(ct_ca9x4_scu_base);
 188
 189         if (ncores > nr_cpu_ids) {
 190                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
 191                         ncores, nr_cpu_ids);
 192                 ncores = nr_cpu_ids;
 193         }
 194
 195         for (i = 0; i < ncores; ++i)
 196                 set_cpu_possible(i, true);
 197
 198         set_smp_cross_call(gic_raise_softirq);
 199 }
 200
 201 static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
 202 {
 203         scu_enable(ct_ca9x4_scu_base);
 204 }
 205 #endif
 206
 207 struct ct_desc ct_ca9x4_desc __initdata = {
 208         .id             = V2M_CT_ID_CA9,
 209         .name           = "CA9x4",
 210         .map_io         = ct_ca9x4_map_io,
 211         .init_irq       = ct_ca9x4_init_irq,
 212         .init_tile      = ct_ca9x4_init,
 213 #ifdef CONFIG_SMP
 214         .init_cpu_map   = ct_ca9x4_init_cpu_map,
 215         .smp_enable     = ct_ca9x4_smp_enable,
 216 #endif
 217 };