2 * Versatile Express Core Tile Cortex A9x4 Support
4 #include <linux/init.h>
6 #include <linux/device.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/platform_device.h>
9 #include <linux/amba/bus.h>
10 #include <linux/amba/clcd.h>
11 #include <linux/clkdev.h>
13 #include <asm/hardware/arm_timer.h>
14 #include <asm/hardware/cache-l2x0.h>
15 #include <asm/hardware/gic.h>
16 #include <asm/smp_scu.h>
17 #include <asm/smp_twd.h>
19 #include <mach/ct-ca9x4.h>
21 #include <asm/hardware/timer-sp.h>
23 #include <asm/mach/map.h>
24 #include <asm/mach/time.h>
28 #include <mach/motherboard.h>
30 #include <plat/clcd.h>
32 static struct map_desc ct_ca9x4_io_desc[] __initdata = {
34 .virtual = V2T_PERIPH,
35 .pfn = __phys_to_pfn(CT_CA9X4_MPIC),
41 static void __init ct_ca9x4_map_io(void)
43 iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
46 #ifdef CONFIG_HAVE_ARM_TWD
47 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
49 static void __init ca9x4_twd_init(void)
51 int err = twd_local_timer_register(&twd_local_timer);
53 pr_err("twd_local_timer_register failed %d\n", err);
56 #define ca9x4_twd_init() do {} while(0)
59 static void __init ct_ca9x4_init_irq(void)
61 gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
62 ioremap(A9_MPCORE_GIC_CPU, SZ_256));
66 static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
68 u32 site = v2m_get_master_site();
71 * Old firmware was using the "site" component of the command
72 * to control the DVI muxer (while it should be always 0 ie. MB).
73 * Newer firmware uses the data register. Keep both for compatibility.
75 v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE(site), site);
76 v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE(SYS_CFG_SITE_MB), 2);
79 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
81 unsigned long framesize = 1024 * 768 * 2;
83 fb->panel = versatile_clcd_get_panel("XVGA");
87 return versatile_clcd_setup_dma(fb, framesize);
90 static struct clcd_board ct_ca9x4_clcd_data = {
92 .caps = CLCD_CAP_5551 | CLCD_CAP_565,
93 .check = clcdfb_check,
94 .decode = clcdfb_decode,
95 .enable = ct_ca9x4_clcd_enable,
96 .setup = ct_ca9x4_clcd_setup,
97 .mmap = versatile_clcd_mmap_dma,
98 .remove = versatile_clcd_remove_dma,
101 static AMBA_AHB_DEVICE(clcd, "ct:clcd", 0, CT_CA9X4_CLCDC, IRQ_CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
102 static AMBA_APB_DEVICE(dmc, "ct:dmc", 0, CT_CA9X4_DMC, IRQ_CT_CA9X4_DMC, NULL);
103 static AMBA_APB_DEVICE(smc, "ct:smc", 0, CT_CA9X4_SMC, IRQ_CT_CA9X4_SMC, NULL);
104 static AMBA_APB_DEVICE(gpio, "ct:gpio", 0, CT_CA9X4_GPIO, IRQ_CT_CA9X4_GPIO, NULL);
106 static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
114 static struct v2m_osc ct_osc1 = {
116 .rate_min = 10000000,
117 .rate_max = 80000000,
118 .rate_default = 23750000,
121 static struct resource pmu_resources[] = {
123 .start = IRQ_CT_CA9X4_PMU_CPU0,
124 .end = IRQ_CT_CA9X4_PMU_CPU0,
125 .flags = IORESOURCE_IRQ,
128 .start = IRQ_CT_CA9X4_PMU_CPU1,
129 .end = IRQ_CT_CA9X4_PMU_CPU1,
130 .flags = IORESOURCE_IRQ,
133 .start = IRQ_CT_CA9X4_PMU_CPU2,
134 .end = IRQ_CT_CA9X4_PMU_CPU2,
135 .flags = IORESOURCE_IRQ,
138 .start = IRQ_CT_CA9X4_PMU_CPU3,
139 .end = IRQ_CT_CA9X4_PMU_CPU3,
140 .flags = IORESOURCE_IRQ,
144 static struct platform_device pmu_device = {
147 .num_resources = ARRAY_SIZE(pmu_resources),
148 .resource = pmu_resources,
151 static void __init ct_ca9x4_init(void)
156 #ifdef CONFIG_CACHE_L2X0
157 void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
159 /* set RAM latencies to 1 cycle for this core tile. */
160 writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
161 writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
163 l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
166 ct_osc1.site = v2m_get_master_site();
167 clk = v2m_osc_register("ct:osc1", &ct_osc1);
168 clk_register_clkdev(clk, NULL, "ct:clcd");
170 for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
171 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
173 platform_device_register(&pmu_device);
177 static void *ct_ca9x4_scu_base __initdata;
179 static void __init ct_ca9x4_init_cpu_map(void)
183 ct_ca9x4_scu_base = ioremap(A9_MPCORE_SCU, SZ_128);
184 if (WARN_ON(!ct_ca9x4_scu_base))
187 ncores = scu_get_core_count(ct_ca9x4_scu_base);
189 if (ncores > nr_cpu_ids) {
190 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
195 for (i = 0; i < ncores; ++i)
196 set_cpu_possible(i, true);
198 set_smp_cross_call(gic_raise_softirq);
201 static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
203 scu_enable(ct_ca9x4_scu_base);
207 struct ct_desc ct_ca9x4_desc __initdata = {
210 .map_io = ct_ca9x4_map_io,
211 .init_irq = ct_ca9x4_init_irq,
212 .init_tile = ct_ca9x4_init,
214 .init_cpu_map = ct_ca9x4_init_cpu_map,
215 .smp_enable = ct_ca9x4_smp_enable,