2 * arch/arm/mach-vt8500/irq.c
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * This file is copied and modified from the original irq.c provided by
24 * Alexey Charkov. Minor changes have been made for Device Tree Support.
27 #include <linux/slab.h>
29 #include <linux/irq.h>
30 #include <linux/irqdomain.h>
31 #include <linux/interrupt.h>
32 #include <linux/bitops.h>
35 #include <linux/of_irq.h>
36 #include <linux/of_address.h>
41 #define VT8500_ICPC_IRQ 0x20
42 #define VT8500_ICPC_FIQ 0x24
43 #define VT8500_ICDC 0x40 /* Destination Control 64*u32 */
44 #define VT8500_ICIS 0x80 /* Interrupt status, 16*u32 */
47 #define ICPC_MASK 0x3F
48 #define ICPC_ROTATE BIT(6)
53 #define ICDC_DSS0 0x02
54 #define ICDC_DSS1 0x03
55 #define ICDC_DSS2 0x04
56 #define ICDC_DSS3 0x05
57 #define ICDC_DSS4 0x06
58 #define ICDC_DSS5 0x07
60 #define VT8500_INT_DISABLE 0
61 #define VT8500_INT_ENABLE BIT(3)
63 #define VT8500_TRIGGER_HIGH 0
64 #define VT8500_TRIGGER_RISING BIT(5)
65 #define VT8500_TRIGGER_FALLING BIT(6)
66 #define VT8500_EDGE ( VT8500_TRIGGER_RISING \
67 | VT8500_TRIGGER_FALLING)
71 struct vt8500_irq_priv {
75 static void vt8500_irq_mask(struct irq_data *d)
77 struct vt8500_irq_priv *priv =
78 (struct vt8500_irq_priv *)(d->domain->host_data);
79 void __iomem *base = priv->base;
82 edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
84 void __iomem *stat_reg = base + VT8500_ICIS
85 + (d->hwirq < 32 ? 0 : 4);
86 unsigned status = readl(stat_reg);
88 status |= (1 << (d->hwirq & 0x1f));
89 writel(status, stat_reg);
91 u8 dctr = readb(base + VT8500_ICDC + d->hwirq);
93 dctr &= ~VT8500_INT_ENABLE;
94 writeb(dctr, base + VT8500_ICDC + d->hwirq);
98 static void vt8500_irq_unmask(struct irq_data *d)
100 struct vt8500_irq_priv *priv =
101 (struct vt8500_irq_priv *)(d->domain->host_data);
102 void __iomem *base = priv->base;
105 dctr = readb(base + VT8500_ICDC + d->hwirq);
106 dctr |= VT8500_INT_ENABLE;
107 writeb(dctr, base + VT8500_ICDC + d->hwirq);
110 static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
112 struct vt8500_irq_priv *priv =
113 (struct vt8500_irq_priv *)(d->domain->host_data);
114 void __iomem *base = priv->base;
117 dctr = readb(base + VT8500_ICDC + d->hwirq);
118 dctr &= ~VT8500_EDGE;
121 case IRQF_TRIGGER_LOW:
123 case IRQF_TRIGGER_HIGH:
124 dctr |= VT8500_TRIGGER_HIGH;
125 __irq_set_handler_locked(d->irq, handle_level_irq);
127 case IRQF_TRIGGER_FALLING:
128 dctr |= VT8500_TRIGGER_FALLING;
129 __irq_set_handler_locked(d->irq, handle_edge_irq);
131 case IRQF_TRIGGER_RISING:
132 dctr |= VT8500_TRIGGER_RISING;
133 __irq_set_handler_locked(d->irq, handle_edge_irq);
136 writeb(dctr, base + VT8500_ICDC + d->hwirq);
141 static struct irq_chip vt8500_irq_chip = {
143 .irq_ack = vt8500_irq_mask,
144 .irq_mask = vt8500_irq_mask,
145 .irq_unmask = vt8500_irq_unmask,
146 .irq_set_type = vt8500_irq_set_type,
149 static void __init vt8500_init_irq_hw(void __iomem *base)
153 /* Enable rotating priority for IRQ */
154 writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
155 writel(0x00, base + VT8500_ICPC_FIQ);
157 for (i = 0; i < 64; i++) {
158 /* Disable all interrupts and route them to IRQ */
159 writeb(VT8500_INT_DISABLE | ICDC_IRQ,
160 base + VT8500_ICDC + i);
164 static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
167 irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
168 set_irq_flags(virq, IRQF_VALID);
173 static struct irq_domain_ops vt8500_irq_domain_ops = {
174 .map = vt8500_irq_map,
175 .xlate = irq_domain_xlate_onecell,
178 int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
180 struct irq_domain *vt8500_irq_domain;
181 struct vt8500_irq_priv *priv;
183 struct device_node *np = node;
185 priv = kzalloc(sizeof(struct vt8500_irq_priv), GFP_KERNEL);
186 priv->base = of_iomap(np, 0);
188 vt8500_irq_domain = irq_domain_add_legacy(node, 64, irq_cnt, 0,
189 &vt8500_irq_domain_ops, priv);
190 if (!vt8500_irq_domain)
191 pr_err("%s: Unable to add wmt irq domain!\n", __func__);
193 irq_set_default_host(vt8500_irq_domain);
195 vt8500_init_irq_hw(priv->base);
197 pr_info("Added IRQ Controller @ %x [virq_base = %d]\n",
198 (u32)(priv->base), irq_cnt);
200 /* check if this is a slaved controller */
201 if (of_irq_count(np) != 0) {
202 /* check that we have the correct number of interrupts */
203 if (of_irq_count(np) != 8) {
204 pr_err("%s: Incorrect IRQ map for slave controller\n",
209 for (i = 0; i < 8; i++) {
210 irq = irq_of_parse_and_map(np, i);
214 pr_info("vt8500-irq: Enabled slave->parent interrupts\n");