2 * arch/arm/mm/cache-feroceon-l2.c - Feroceon L2 cache controller support
4 * Copyright (C) 2008 Marvell Semiconductor
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 * - Unified Layer 2 Cache for Feroceon CPU Cores,
12 * Document ID MV-S104858-00, Rev. A, October 23 2007.
15 #include <linux/init.h>
16 #include <linux/highmem.h>
17 #include <asm/cacheflush.h>
19 #include <plat/cache-feroceon-l2.h>
22 * Low-level cache maintenance operations.
24 * As well as the regular 'clean/invalidate/flush L2 cache line by
25 * MVA' instructions, the Feroceon L2 cache controller also features
26 * 'clean/invalidate L2 range by MVA' operations.
28 * Cache range operations are initiated by writing the start and
29 * end addresses to successive cp15 registers, and process every
30 * cache line whose first byte address lies in the inclusive range
33 * The cache range operations stall the CPU pipeline until completion.
35 * The range operations require two successive cp15 writes, in
36 * between which we don't want to be preempted.
39 static inline unsigned long l2_get_va(unsigned long paddr)
43 * Because range ops can't be done on physical addresses,
44 * we simply install a virtual mapping for it only for the
45 * TLB lookup to occur, hence no need to flush the untouched
46 * memory mapping afterwards (note: a cache flush may happen
47 * in some circumstances depending on the path taken in kunmap_atomic).
49 void *vaddr = kmap_atomic_pfn(paddr >> PAGE_SHIFT);
50 return (unsigned long)vaddr + (paddr & ~PAGE_MASK);
52 return __phys_to_virt(paddr);
56 static inline void l2_put_va(unsigned long vaddr)
59 kunmap_atomic((void *)vaddr);
63 static inline void l2_clean_pa(unsigned long addr)
65 __asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr));
68 static inline void l2_clean_pa_range(unsigned long start, unsigned long end)
70 unsigned long va_start, va_end, flags;
73 * Make sure 'start' and 'end' reference the same page, as
74 * L2 is PIPT and range operations only do a TLB lookup on
77 BUG_ON((start ^ end) >> PAGE_SHIFT);
79 va_start = l2_get_va(start);
80 va_end = va_start + (end - start);
81 raw_local_irq_save(flags);
82 __asm__("mcr p15, 1, %0, c15, c9, 4\n\t"
83 "mcr p15, 1, %1, c15, c9, 5"
84 : : "r" (va_start), "r" (va_end));
85 raw_local_irq_restore(flags);
89 static inline void l2_clean_inv_pa(unsigned long addr)
91 __asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr));
94 static inline void l2_inv_pa(unsigned long addr)
96 __asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr));
99 static inline void l2_inv_pa_range(unsigned long start, unsigned long end)
101 unsigned long va_start, va_end, flags;
104 * Make sure 'start' and 'end' reference the same page, as
105 * L2 is PIPT and range operations only do a TLB lookup on
108 BUG_ON((start ^ end) >> PAGE_SHIFT);
110 va_start = l2_get_va(start);
111 va_end = va_start + (end - start);
112 raw_local_irq_save(flags);
113 __asm__("mcr p15, 1, %0, c15, c11, 4\n\t"
114 "mcr p15, 1, %1, c15, c11, 5"
115 : : "r" (va_start), "r" (va_end));
116 raw_local_irq_restore(flags);
120 static inline void l2_inv_all(void)
122 __asm__("mcr p15, 1, %0, c15, c11, 0" : : "r" (0));
128 * Note that the end addresses passed to Linux primitives are
129 * noninclusive, while the hardware cache range operations use
130 * inclusive start and end addresses.
132 #define CACHE_LINE_SIZE 32
133 #define MAX_RANGE_SIZE 1024
135 static int l2_wt_override;
137 static unsigned long calc_range_end(unsigned long start, unsigned long end)
139 unsigned long range_end;
141 BUG_ON(start & (CACHE_LINE_SIZE - 1));
142 BUG_ON(end & (CACHE_LINE_SIZE - 1));
145 * Try to process all cache lines between 'start' and 'end'.
150 * Limit the number of cache lines processed at once,
151 * since cache range operations stall the CPU pipeline
154 if (range_end > start + MAX_RANGE_SIZE)
155 range_end = start + MAX_RANGE_SIZE;
158 * Cache range operations can't straddle a page boundary.
160 if (range_end > (start | (PAGE_SIZE - 1)) + 1)
161 range_end = (start | (PAGE_SIZE - 1)) + 1;
166 static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
169 * Clean and invalidate partial first cache line.
171 if (start & (CACHE_LINE_SIZE - 1)) {
172 l2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
173 start = (start | (CACHE_LINE_SIZE - 1)) + 1;
177 * Clean and invalidate partial last cache line.
179 if (start < end && end & (CACHE_LINE_SIZE - 1)) {
180 l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
181 end &= ~(CACHE_LINE_SIZE - 1);
185 * Invalidate all full cache lines between 'start' and 'end'.
187 while (start < end) {
188 unsigned long range_end = calc_range_end(start, end);
189 l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
196 static void feroceon_l2_clean_range(unsigned long start, unsigned long end)
199 * If L2 is forced to WT, the L2 will always be clean and we
200 * don't need to do anything here.
202 if (!l2_wt_override) {
203 start &= ~(CACHE_LINE_SIZE - 1);
204 end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
205 while (start != end) {
206 unsigned long range_end = calc_range_end(start, end);
207 l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE);
215 static void feroceon_l2_flush_range(unsigned long start, unsigned long end)
217 start &= ~(CACHE_LINE_SIZE - 1);
218 end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
219 while (start != end) {
220 unsigned long range_end = calc_range_end(start, end);
222 l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE);
223 l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
232 * Routines to disable and re-enable the D-cache and I-cache at run
233 * time. These are necessary because the L2 cache can only be enabled
234 * or disabled while the L1 Dcache and Icache are both disabled.
236 static int __init flush_and_disable_dcache(void)
244 raw_local_irq_save(flags);
247 raw_local_irq_restore(flags);
253 static void __init enable_dcache(void)
261 static void __init __invalidate_icache(void)
263 __asm__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
266 static int __init invalidate_and_disable_icache(void)
273 __invalidate_icache();
279 static void __init enable_icache(void)
287 static inline u32 read_extra_features(void)
291 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));
296 static inline void write_extra_features(u32 u)
298 __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
301 static void __init disable_l2_prefetch(void)
306 * Read the CPU Extra Features register and verify that the
307 * Disable L2 Prefetch bit is set.
309 u = read_extra_features();
310 if (!(u & 0x01000000)) {
311 printk(KERN_INFO "Feroceon L2: Disabling L2 prefetch.\n");
312 write_extra_features(u | 0x01000000);
316 static void __init enable_l2(void)
320 u = read_extra_features();
321 if (!(u & 0x00400000)) {
324 printk(KERN_INFO "Feroceon L2: Enabling L2\n");
326 d = flush_and_disable_dcache();
327 i = invalidate_and_disable_icache();
329 write_extra_features(u | 0x00400000);
337 void __init feroceon_l2_init(int __l2_wt_override)
339 l2_wt_override = __l2_wt_override;
341 disable_l2_prefetch();
343 outer_cache.inv_range = feroceon_l2_inv_range;
344 outer_cache.clean_range = feroceon_l2_clean_range;
345 outer_cache.flush_range = feroceon_l2_flush_range;
349 printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n",
350 l2_wt_override ? ", in WT override mode" : "");