2 * linux/arch/arm/mm/cache-v4.S
4 * Copyright (C) 1997-2002 Russell king
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/linkage.h>
11 #include <linux/init.h>
13 #include "proc-macros.S"
16 * flush_user_cache_all()
18 * Invalidate all cache entries in a particular address
21 * - mm - mm_struct describing address space
23 ENTRY(v4_flush_user_cache_all)
26 * flush_kern_cache_all()
28 * Clean and invalidate the entire cache.
30 ENTRY(v4_flush_kern_cache_all)
31 #ifdef CONFIG_CPU_CP15
33 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
40 * flush_user_cache_range(start, end, flags)
42 * Invalidate a range of cache entries in the specified
45 * - start - start address (may not be aligned)
46 * - end - end address (exclusive, may not be aligned)
47 * - flags - vma_area_struct flags describing address space
49 ENTRY(v4_flush_user_cache_range)
50 #ifdef CONFIG_CPU_CP15
52 mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache
59 * coherent_kern_range(start, end)
61 * Ensure coherency between the Icache and the Dcache in the
62 * region described by start. If you have non-snooping
63 * Harvard caches, you need to implement this function.
65 * - start - virtual start address
66 * - end - virtual end address
68 ENTRY(v4_coherent_kern_range)
72 * coherent_user_range(start, end)
74 * Ensure coherency between the Icache and the Dcache in the
75 * region described by start. If you have non-snooping
76 * Harvard caches, you need to implement this function.
78 * - start - virtual start address
79 * - end - virtual end address
81 ENTRY(v4_coherent_user_range)
85 * flush_kern_dcache_area(void *addr, size_t size)
87 * Ensure no D cache aliasing occurs, either with itself or
90 * - addr - kernel address
91 * - size - region size
93 ENTRY(v4_flush_kern_dcache_area)
97 * dma_flush_range(start, end)
99 * Clean and invalidate the specified virtual address range.
101 * - start - virtual start address
102 * - end - virtual end address
104 ENTRY(v4_dma_flush_range)
105 #ifdef CONFIG_CPU_CP15
107 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
112 * dma_unmap_area(start, size, dir)
113 * - start - kernel virtual start address
114 * - size - size of region
115 * - dir - DMA direction
117 ENTRY(v4_dma_unmap_area)
118 teq r2, #DMA_TO_DEVICE
119 bne v4_dma_flush_range
123 * dma_map_area(start, size, dir)
124 * - start - kernel virtual start address
125 * - size - size of region
126 * - dir - DMA direction
128 ENTRY(v4_dma_map_area)
130 ENDPROC(v4_dma_unmap_area)
131 ENDPROC(v4_dma_map_area)
135 .type v4_cache_fns, #object
137 .long v4_flush_kern_cache_all
138 .long v4_flush_user_cache_all
139 .long v4_flush_user_cache_range
140 .long v4_coherent_kern_range
141 .long v4_coherent_user_range
142 .long v4_flush_kern_dcache_area
143 .long v4_dma_map_area
144 .long v4_dma_unmap_area
145 .long v4_dma_flush_range
146 .size v4_cache_fns, . - v4_cache_fns