2 * linux/arch/arm/mm/cache-v4wt.S
4 * Copyright (C) 1997-2002 Russell king
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * ARMv4 write through cache operations support.
12 * We assume that the write buffer is not enabled.
14 #include <linux/linkage.h>
15 #include <linux/init.h>
17 #include "proc-macros.S"
20 * The size of one data cache line.
22 #define CACHE_DLINESIZE 32
25 * The number of data cache segments.
27 #define CACHE_DSEGMENTS 8
30 * The number of lines in a cache segment.
32 #define CACHE_DENTRIES 64
35 * This is the size at which it becomes more efficient to
36 * clean the whole cache, rather than using the individual
37 * cache line maintainence instructions.
39 * *** This needs benchmarking
41 #define CACHE_DLIMIT 16384
44 * flush_user_cache_all()
46 * Invalidate all cache entries in a particular address
49 ENTRY(v4wt_flush_user_cache_all)
52 * flush_kern_cache_all()
54 * Clean and invalidate the entire cache.
56 ENTRY(v4wt_flush_kern_cache_all)
61 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
62 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
66 * flush_user_cache_range(start, end, flags)
68 * Clean and invalidate a range of cache entries in the specified
71 * - start - start address (inclusive, page aligned)
72 * - end - end address (exclusive, page aligned)
73 * - flags - vma_area_struct flags describing address space
75 ENTRY(v4wt_flush_user_cache_range)
76 sub r3, r1, r0 @ calculate total size
78 bhs __flush_whole_cache
80 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
82 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
83 add r0, r0, #CACHE_DLINESIZE
89 * coherent_kern_range(start, end)
91 * Ensure coherency between the Icache and the Dcache in the
92 * region described by start. If you have non-snooping
93 * Harvard caches, you need to implement this function.
95 * - start - virtual start address
96 * - end - virtual end address
98 ENTRY(v4wt_coherent_kern_range)
102 * coherent_user_range(start, end)
104 * Ensure coherency between the Icache and the Dcache in the
105 * region described by start. If you have non-snooping
106 * Harvard caches, you need to implement this function.
108 * - start - virtual start address
109 * - end - virtual end address
111 ENTRY(v4wt_coherent_user_range)
112 bic r0, r0, #CACHE_DLINESIZE - 1
113 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
114 add r0, r0, #CACHE_DLINESIZE
120 * flush_kern_dcache_area(void *addr, size_t size)
122 * Ensure no D cache aliasing occurs, either with itself or
125 * - addr - kernel address
126 * - size - region size
128 ENTRY(v4wt_flush_kern_dcache_area)
130 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
135 * dma_inv_range(start, end)
137 * Invalidate (discard) the specified virtual address range.
138 * May not write back any entries. If 'start' or 'end'
139 * are not cache line aligned, those lines must be written
142 * - start - virtual start address
143 * - end - virtual end address
146 bic r0, r0, #CACHE_DLINESIZE - 1
147 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
148 add r0, r0, #CACHE_DLINESIZE
154 * dma_flush_range(start, end)
156 * Clean and invalidate the specified virtual address range.
158 * - start - virtual start address
159 * - end - virtual end address
161 .globl v4wt_dma_flush_range
162 .equ v4wt_dma_flush_range, v4wt_dma_inv_range
165 * dma_unmap_area(start, size, dir)
166 * - start - kernel virtual start address
167 * - size - size of region
168 * - dir - DMA direction
170 ENTRY(v4wt_dma_unmap_area)
172 teq r2, #DMA_TO_DEVICE
173 bne v4wt_dma_inv_range
177 * dma_map_area(start, size, dir)
178 * - start - kernel virtual start address
179 * - size - size of region
180 * - dir - DMA direction
182 ENTRY(v4wt_dma_map_area)
184 ENDPROC(v4wt_dma_unmap_area)
185 ENDPROC(v4wt_dma_map_area)
189 .type v4wt_cache_fns, #object
190 ENTRY(v4wt_cache_fns)
191 .long v4wt_flush_kern_cache_all
192 .long v4wt_flush_user_cache_all
193 .long v4wt_flush_user_cache_range
194 .long v4wt_coherent_kern_range
195 .long v4wt_coherent_user_range
196 .long v4wt_flush_kern_dcache_area
197 .long v4wt_dma_map_area
198 .long v4wt_dma_unmap_area
199 .long v4wt_dma_flush_range
200 .size v4wt_cache_fns, . - v4wt_cache_fns