2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/bootmem.h>
13 #include <linux/module.h>
15 #include <linux/gfp.h>
16 #include <linux/errno.h>
17 #include <linux/list.h>
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/dma-contiguous.h>
22 #include <linux/highmem.h>
23 #include <linux/memblock.h>
24 #include <linux/slab.h>
25 #include <linux/iommu.h>
27 #include <linux/vmalloc.h>
28 #include <linux/sizes.h>
30 #include <asm/memory.h>
31 #include <asm/highmem.h>
32 #include <asm/cacheflush.h>
33 #include <asm/tlbflush.h>
34 #include <asm/mach/arch.h>
35 #include <asm/dma-iommu.h>
36 #include <asm/mach/map.h>
37 #include <asm/system_info.h>
38 #include <asm/dma-contiguous.h>
43 * The DMA API is built upon the notion of "buffer ownership". A buffer
44 * is either exclusively owned by the CPU (and therefore may be accessed
45 * by it) or exclusively owned by the DMA device. These helper functions
46 * represent the transitions between these two ownership states.
48 * Note, however, that on later ARMs, this notion does not work due to
49 * speculative prefetches. We model our approach on the assumption that
50 * the CPU does do speculative prefetches, which means we clean caches
51 * before transfers and delay cache invalidation until transfer completion.
54 static void __dma_page_cpu_to_dev(struct page *, unsigned long,
55 size_t, enum dma_data_direction);
56 static void __dma_page_dev_to_cpu(struct page *, unsigned long,
57 size_t, enum dma_data_direction);
60 * arm_dma_map_page - map a portion of a page for streaming DMA
61 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
62 * @page: page that buffer resides in
63 * @offset: offset into page for start of buffer
64 * @size: size of buffer to map
65 * @dir: DMA transfer direction
67 * Ensure that any data held in the cache is appropriately discarded
70 * The device owns this memory once this call has completed. The CPU
71 * can regain ownership by calling dma_unmap_page().
73 static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
74 unsigned long offset, size_t size, enum dma_data_direction dir,
75 struct dma_attrs *attrs)
77 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
78 __dma_page_cpu_to_dev(page, offset, size, dir);
79 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
82 static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
83 unsigned long offset, size_t size, enum dma_data_direction dir,
84 struct dma_attrs *attrs)
86 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
90 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
91 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
92 * @handle: DMA address of buffer
93 * @size: size of buffer (same as passed to dma_map_page)
94 * @dir: DMA transfer direction (same as passed to dma_map_page)
96 * Unmap a page streaming mode DMA translation. The handle and size
97 * must match what was provided in the previous dma_map_page() call.
98 * All other usages are undefined.
100 * After this call, reads by the CPU to the buffer are guaranteed to see
101 * whatever the device wrote there.
103 static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
104 size_t size, enum dma_data_direction dir,
105 struct dma_attrs *attrs)
107 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
108 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
109 handle & ~PAGE_MASK, size, dir);
112 static void arm_dma_sync_single_for_cpu(struct device *dev,
113 dma_addr_t handle, size_t size, enum dma_data_direction dir)
115 unsigned int offset = handle & (PAGE_SIZE - 1);
116 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
117 __dma_page_dev_to_cpu(page, offset, size, dir);
120 static void arm_dma_sync_single_for_device(struct device *dev,
121 dma_addr_t handle, size_t size, enum dma_data_direction dir)
123 unsigned int offset = handle & (PAGE_SIZE - 1);
124 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
125 __dma_page_cpu_to_dev(page, offset, size, dir);
128 struct dma_map_ops arm_dma_ops = {
129 .alloc = arm_dma_alloc,
130 .free = arm_dma_free,
131 .mmap = arm_dma_mmap,
132 .get_sgtable = arm_dma_get_sgtable,
133 .map_page = arm_dma_map_page,
134 .unmap_page = arm_dma_unmap_page,
135 .map_sg = arm_dma_map_sg,
136 .unmap_sg = arm_dma_unmap_sg,
137 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
138 .sync_single_for_device = arm_dma_sync_single_for_device,
139 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
140 .sync_sg_for_device = arm_dma_sync_sg_for_device,
141 .set_dma_mask = arm_dma_set_mask,
143 EXPORT_SYMBOL(arm_dma_ops);
145 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
146 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
147 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
148 dma_addr_t handle, struct dma_attrs *attrs);
150 struct dma_map_ops arm_coherent_dma_ops = {
151 .alloc = arm_coherent_dma_alloc,
152 .free = arm_coherent_dma_free,
153 .mmap = arm_dma_mmap,
154 .get_sgtable = arm_dma_get_sgtable,
155 .map_page = arm_coherent_dma_map_page,
156 .map_sg = arm_dma_map_sg,
157 .set_dma_mask = arm_dma_set_mask,
159 EXPORT_SYMBOL(arm_coherent_dma_ops);
161 static int __dma_supported(struct device *dev, u64 mask, bool warn)
163 unsigned long max_dma_pfn;
166 * If the mask allows for more memory than we can address,
167 * and we actually have that much memory, then we must
168 * indicate that DMA to this device is not supported.
170 if (sizeof(mask) != sizeof(dma_addr_t) &&
171 mask > (dma_addr_t)~0 &&
172 dma_to_pfn(dev, ~0) < max_pfn) {
174 dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n",
176 dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n");
181 max_dma_pfn = min(max_pfn, arm_dma_pfn_limit);
184 * Translate the device's DMA mask to a PFN limit. This
185 * PFN number includes the page which we can DMA to.
187 if (dma_to_pfn(dev, mask) < max_dma_pfn) {
189 dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n",
191 dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1,
199 static u64 get_coherent_dma_mask(struct device *dev)
201 u64 mask = (u64)DMA_BIT_MASK(32);
204 mask = dev->coherent_dma_mask;
207 * Sanity check the DMA mask - it must be non-zero, and
208 * must be able to be satisfied by a DMA allocation.
211 dev_warn(dev, "coherent DMA mask is unset\n");
215 if (!__dma_supported(dev, mask, true))
222 static void __dma_clear_buffer(struct page *page, size_t size)
225 * Ensure that the allocated pages are zeroed, and that any data
226 * lurking in the kernel direct-mapped region is invalidated.
228 if (PageHighMem(page)) {
229 phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
230 phys_addr_t end = base + size;
232 void *ptr = kmap_atomic(page);
233 memset(ptr, 0, PAGE_SIZE);
234 dmac_flush_range(ptr, ptr + PAGE_SIZE);
239 outer_flush_range(base, end);
241 void *ptr = page_address(page);
242 memset(ptr, 0, size);
243 dmac_flush_range(ptr, ptr + size);
244 outer_flush_range(__pa(ptr), __pa(ptr) + size);
249 * Allocate a DMA buffer for 'dev' of size 'size' using the
250 * specified gfp mask. Note that 'size' must be page aligned.
252 static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
254 unsigned long order = get_order(size);
255 struct page *page, *p, *e;
257 page = alloc_pages(gfp, order);
262 * Now split the huge page and free the excess pages
264 split_page(page, order);
265 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
268 __dma_clear_buffer(page, size);
274 * Free a DMA buffer. 'size' must be page aligned.
276 static void __dma_free_buffer(struct page *page, size_t size)
278 struct page *e = page + (size >> PAGE_SHIFT);
288 static void *__alloc_from_contiguous(struct device *dev, size_t size,
289 pgprot_t prot, struct page **ret_page,
292 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
293 pgprot_t prot, struct page **ret_page,
297 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
300 struct vm_struct *area;
304 * DMA allocation can be mapped to user space, so lets
305 * set VM_USERMAP flags too.
307 area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
311 addr = (unsigned long)area->addr;
312 area->phys_addr = __pfn_to_phys(page_to_pfn(page));
314 if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) {
315 vunmap((void *)addr);
321 static void __dma_free_remap(void *cpu_addr, size_t size)
323 unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP;
324 struct vm_struct *area = find_vm_area(cpu_addr);
325 if (!area || (area->flags & flags) != flags) {
326 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
329 unmap_kernel_range((unsigned long)cpu_addr, size);
333 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
338 unsigned long *bitmap;
339 unsigned long nr_pages;
344 static struct dma_pool atomic_pool = {
345 .size = DEFAULT_DMA_COHERENT_POOL_SIZE,
348 static int __init early_coherent_pool(char *p)
350 atomic_pool.size = memparse(p, &p);
353 early_param("coherent_pool", early_coherent_pool);
355 void __init init_dma_coherent_pool_size(unsigned long size)
358 * Catch any attempt to set the pool size too late.
360 BUG_ON(atomic_pool.vaddr);
363 * Set architecture specific coherent pool size only if
364 * it has not been changed by kernel command line parameter.
366 if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE)
367 atomic_pool.size = size;
371 * Initialise the coherent pool for atomic allocations.
373 static int __init atomic_pool_init(void)
375 struct dma_pool *pool = &atomic_pool;
376 pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL);
377 gfp_t gfp = GFP_KERNEL | GFP_DMA;
378 unsigned long nr_pages = pool->size >> PAGE_SHIFT;
379 unsigned long *bitmap;
383 int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
385 bitmap = kzalloc(bitmap_size, GFP_KERNEL);
389 pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
393 if (dev_get_cma_area(NULL))
394 ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
397 ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page,
402 for (i = 0; i < nr_pages; i++)
405 spin_lock_init(&pool->lock);
408 pool->bitmap = bitmap;
409 pool->nr_pages = nr_pages;
410 pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
411 (unsigned)pool->size / 1024);
419 pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
420 (unsigned)pool->size / 1024);
424 * CMA is activated by core_initcall, so we must be called after it.
426 postcore_initcall(atomic_pool_init);
428 struct dma_contig_early_reserve {
433 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
435 static int dma_mmu_remap_num __initdata;
437 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
439 dma_mmu_remap[dma_mmu_remap_num].base = base;
440 dma_mmu_remap[dma_mmu_remap_num].size = size;
444 void __init dma_contiguous_remap(void)
447 for (i = 0; i < dma_mmu_remap_num; i++) {
448 phys_addr_t start = dma_mmu_remap[i].base;
449 phys_addr_t end = start + dma_mmu_remap[i].size;
453 if (end > arm_lowmem_limit)
454 end = arm_lowmem_limit;
458 map.pfn = __phys_to_pfn(start);
459 map.virtual = __phys_to_virt(start);
460 map.length = end - start;
461 map.type = MT_MEMORY_DMA_READY;
464 * Clear previous low-memory mapping to ensure that the
465 * TLB does not see any conflicting entries, then flush
466 * the TLB of the old entries before creating new mappings.
468 * This ensures that any speculatively loaded TLB entries
469 * (even though they may be rare) can not cause any problems,
470 * and ensures that this code is architecturally compliant.
472 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
474 pmd_clear(pmd_off_k(addr));
476 flush_tlb_kernel_range(__phys_to_virt(start),
477 __phys_to_virt(end));
479 iotable_init(&map, 1);
483 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
486 struct page *page = virt_to_page(addr);
487 pgprot_t prot = *(pgprot_t *)data;
489 set_pte_ext(pte, mk_pte(page, prot), 0);
493 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
495 unsigned long start = (unsigned long) page_address(page);
496 unsigned end = start + size;
498 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
499 flush_tlb_kernel_range(start, end);
502 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
503 pgprot_t prot, struct page **ret_page,
508 page = __dma_alloc_buffer(dev, size, gfp);
512 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
514 __dma_free_buffer(page, size);
522 static void *__alloc_from_pool(size_t size, struct page **ret_page)
524 struct dma_pool *pool = &atomic_pool;
525 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
529 unsigned long align_mask;
532 WARN(1, "coherent pool not initialised!\n");
537 * Align the region allocation - allocations from pool are rather
538 * small, so align them to their order in pages, minimum is a page
539 * size. This helps reduce fragmentation of the DMA space.
541 align_mask = (1 << get_order(size)) - 1;
543 spin_lock_irqsave(&pool->lock, flags);
544 pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages,
545 0, count, align_mask);
546 if (pageno < pool->nr_pages) {
547 bitmap_set(pool->bitmap, pageno, count);
548 ptr = pool->vaddr + PAGE_SIZE * pageno;
549 *ret_page = pool->pages[pageno];
551 pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
552 "Please increase it with coherent_pool= kernel parameter!\n",
553 (unsigned)pool->size / 1024);
555 spin_unlock_irqrestore(&pool->lock, flags);
560 static bool __in_atomic_pool(void *start, size_t size)
562 struct dma_pool *pool = &atomic_pool;
563 void *end = start + size;
564 void *pool_start = pool->vaddr;
565 void *pool_end = pool->vaddr + pool->size;
567 if (start < pool_start || start >= pool_end)
573 WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
574 start, end - 1, pool_start, pool_end - 1);
579 static int __free_from_pool(void *start, size_t size)
581 struct dma_pool *pool = &atomic_pool;
582 unsigned long pageno, count;
585 if (!__in_atomic_pool(start, size))
588 pageno = (start - pool->vaddr) >> PAGE_SHIFT;
589 count = size >> PAGE_SHIFT;
591 spin_lock_irqsave(&pool->lock, flags);
592 bitmap_clear(pool->bitmap, pageno, count);
593 spin_unlock_irqrestore(&pool->lock, flags);
598 static void *__alloc_from_contiguous(struct device *dev, size_t size,
599 pgprot_t prot, struct page **ret_page,
602 unsigned long order = get_order(size);
603 size_t count = size >> PAGE_SHIFT;
607 page = dma_alloc_from_contiguous(dev, count, order);
611 __dma_clear_buffer(page, size);
613 if (PageHighMem(page)) {
614 ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
616 dma_release_from_contiguous(dev, page, count);
620 __dma_remap(page, size, prot);
621 ptr = page_address(page);
627 static void __free_from_contiguous(struct device *dev, struct page *page,
628 void *cpu_addr, size_t size)
630 if (PageHighMem(page))
631 __dma_free_remap(cpu_addr, size);
633 __dma_remap(page, size, PAGE_KERNEL);
634 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
637 static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
639 prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
640 pgprot_writecombine(prot) :
641 pgprot_dmacoherent(prot);
647 #else /* !CONFIG_MMU */
651 #define __get_dma_pgprot(attrs, prot) __pgprot(0)
652 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL
653 #define __alloc_from_pool(size, ret_page) NULL
654 #define __alloc_from_contiguous(dev, size, prot, ret, c) NULL
655 #define __free_from_pool(cpu_addr, size) 0
656 #define __free_from_contiguous(dev, page, cpu_addr, size) do { } while (0)
657 #define __dma_free_remap(cpu_addr, size) do { } while (0)
659 #endif /* CONFIG_MMU */
661 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
662 struct page **ret_page)
665 page = __dma_alloc_buffer(dev, size, gfp);
670 return page_address(page);
675 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
676 gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller)
678 u64 mask = get_coherent_dma_mask(dev);
679 struct page *page = NULL;
682 #ifdef CONFIG_DMA_API_DEBUG
683 u64 limit = (mask + 1) & ~mask;
684 if (limit && size >= limit) {
685 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
694 if (mask < 0xffffffffULL)
698 * Following is a work-around (a.k.a. hack) to prevent pages
699 * with __GFP_COMP being passed to split_page() which cannot
700 * handle them. The real problem is that this flag probably
701 * should be 0 on ARM as it is not supported on this
702 * platform; see CONFIG_HUGETLBFS.
704 gfp &= ~(__GFP_COMP);
706 *handle = DMA_ERROR_CODE;
707 size = PAGE_ALIGN(size);
709 if (is_coherent || nommu())
710 addr = __alloc_simple_buffer(dev, size, gfp, &page);
711 else if (!(gfp & __GFP_WAIT))
712 addr = __alloc_from_pool(size, &page);
713 else if (!dev_get_cma_area(dev))
714 addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
716 addr = __alloc_from_contiguous(dev, size, prot, &page, caller);
719 *handle = pfn_to_dma(dev, page_to_pfn(page));
725 * Allocate DMA-coherent memory space and return both the kernel remapped
726 * virtual and bus address for that space.
728 void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
729 gfp_t gfp, struct dma_attrs *attrs)
731 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
734 if (dma_alloc_from_coherent(dev, size, handle, &memory))
737 return __dma_alloc(dev, size, handle, gfp, prot, false,
738 __builtin_return_address(0));
741 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
742 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
744 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
747 if (dma_alloc_from_coherent(dev, size, handle, &memory))
750 return __dma_alloc(dev, size, handle, gfp, prot, true,
751 __builtin_return_address(0));
755 * Create userspace mapping for the DMA-coherent memory.
757 int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
758 void *cpu_addr, dma_addr_t dma_addr, size_t size,
759 struct dma_attrs *attrs)
763 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
764 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
765 unsigned long pfn = dma_to_pfn(dev, dma_addr);
766 unsigned long off = vma->vm_pgoff;
768 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
770 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
773 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
774 ret = remap_pfn_range(vma, vma->vm_start,
776 vma->vm_end - vma->vm_start,
779 #endif /* CONFIG_MMU */
785 * Free a buffer as defined by the above mapping.
787 static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
788 dma_addr_t handle, struct dma_attrs *attrs,
791 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
793 if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
796 size = PAGE_ALIGN(size);
798 if (is_coherent || nommu()) {
799 __dma_free_buffer(page, size);
800 } else if (__free_from_pool(cpu_addr, size)) {
802 } else if (!dev_get_cma_area(dev)) {
803 __dma_free_remap(cpu_addr, size);
804 __dma_free_buffer(page, size);
807 * Non-atomic allocations cannot be freed with IRQs disabled
809 WARN_ON(irqs_disabled());
810 __free_from_contiguous(dev, page, cpu_addr, size);
814 void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
815 dma_addr_t handle, struct dma_attrs *attrs)
817 __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
820 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
821 dma_addr_t handle, struct dma_attrs *attrs)
823 __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
826 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
827 void *cpu_addr, dma_addr_t handle, size_t size,
828 struct dma_attrs *attrs)
830 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
833 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
837 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
841 static void dma_cache_maint_page(struct page *page, unsigned long offset,
842 size_t size, enum dma_data_direction dir,
843 void (*op)(const void *, size_t, int))
848 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
852 * A single sg entry may refer to multiple physically contiguous
853 * pages. But we still need to process highmem pages individually.
854 * If highmem is not configured then the bulk of this loop gets
861 page = pfn_to_page(pfn);
863 if (PageHighMem(page)) {
864 if (len + offset > PAGE_SIZE)
865 len = PAGE_SIZE - offset;
867 if (cache_is_vipt_nonaliasing()) {
868 vaddr = kmap_atomic(page);
869 op(vaddr + offset, len, dir);
870 kunmap_atomic(vaddr);
872 vaddr = kmap_high_get(page);
874 op(vaddr + offset, len, dir);
879 vaddr = page_address(page) + offset;
889 * Make an area consistent for devices.
890 * Note: Drivers should NOT use this function directly, as it will break
891 * platforms with CONFIG_DMABOUNCE.
892 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
894 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
895 size_t size, enum dma_data_direction dir)
899 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
901 paddr = page_to_phys(page) + off;
902 if (dir == DMA_FROM_DEVICE) {
903 outer_inv_range(paddr, paddr + size);
905 outer_clean_range(paddr, paddr + size);
907 /* FIXME: non-speculating: flush on bidirectional mappings? */
910 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
911 size_t size, enum dma_data_direction dir)
913 phys_addr_t paddr = page_to_phys(page) + off;
915 /* FIXME: non-speculating: not required */
916 /* in any case, don't bother invalidating if DMA to device */
917 if (dir != DMA_TO_DEVICE) {
918 outer_inv_range(paddr, paddr + size);
920 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
924 * Mark the D-cache clean for these pages to avoid extra flushing.
926 if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
930 pfn = page_to_pfn(page) + off / PAGE_SIZE;
934 left -= PAGE_SIZE - off;
936 while (left >= PAGE_SIZE) {
937 page = pfn_to_page(pfn++);
938 set_bit(PG_dcache_clean, &page->flags);
945 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
946 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
947 * @sg: list of buffers
948 * @nents: number of buffers to map
949 * @dir: DMA transfer direction
951 * Map a set of buffers described by scatterlist in streaming mode for DMA.
952 * This is the scatter-gather version of the dma_map_single interface.
953 * Here the scatter gather list elements are each tagged with the
954 * appropriate dma address and length. They are obtained via
955 * sg_dma_{address,length}.
957 * Device ownership issues as mentioned for dma_map_single are the same
960 int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
961 enum dma_data_direction dir, struct dma_attrs *attrs)
963 struct dma_map_ops *ops = get_dma_ops(dev);
964 struct scatterlist *s;
967 for_each_sg(sg, s, nents, i) {
968 #ifdef CONFIG_NEED_SG_DMA_LENGTH
969 s->dma_length = s->length;
971 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
972 s->length, dir, attrs);
973 if (dma_mapping_error(dev, s->dma_address))
979 for_each_sg(sg, s, i, j)
980 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
985 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
986 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
987 * @sg: list of buffers
988 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
989 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
991 * Unmap a set of streaming mode DMA translations. Again, CPU access
992 * rules concerning calls here are the same as for dma_unmap_single().
994 void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
995 enum dma_data_direction dir, struct dma_attrs *attrs)
997 struct dma_map_ops *ops = get_dma_ops(dev);
998 struct scatterlist *s;
1002 for_each_sg(sg, s, nents, i)
1003 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
1007 * arm_dma_sync_sg_for_cpu
1008 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1009 * @sg: list of buffers
1010 * @nents: number of buffers to map (returned from dma_map_sg)
1011 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1013 void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1014 int nents, enum dma_data_direction dir)
1016 struct dma_map_ops *ops = get_dma_ops(dev);
1017 struct scatterlist *s;
1020 for_each_sg(sg, s, nents, i)
1021 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
1026 * arm_dma_sync_sg_for_device
1027 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1028 * @sg: list of buffers
1029 * @nents: number of buffers to map (returned from dma_map_sg)
1030 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1032 void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1033 int nents, enum dma_data_direction dir)
1035 struct dma_map_ops *ops = get_dma_ops(dev);
1036 struct scatterlist *s;
1039 for_each_sg(sg, s, nents, i)
1040 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
1045 * Return whether the given device DMA address mask can be supported
1046 * properly. For example, if your device can only drive the low 24-bits
1047 * during bus mastering, then you would pass 0x00ffffff as the mask
1050 int dma_supported(struct device *dev, u64 mask)
1052 return __dma_supported(dev, mask, false);
1054 EXPORT_SYMBOL(dma_supported);
1056 int arm_dma_set_mask(struct device *dev, u64 dma_mask)
1058 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
1061 *dev->dma_mask = dma_mask;
1066 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
1068 static int __init dma_debug_do_init(void)
1070 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1073 fs_initcall(dma_debug_do_init);
1075 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1079 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping);
1081 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1084 unsigned int order = get_order(size);
1085 unsigned int align = 0;
1086 unsigned int count, start;
1087 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1088 unsigned long flags;
1092 if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
1093 order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
1095 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1096 align = (1 << order) - 1;
1098 spin_lock_irqsave(&mapping->lock, flags);
1099 for (i = 0; i < mapping->nr_bitmaps; i++) {
1100 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1101 mapping->bits, 0, count, align);
1103 if (start > mapping->bits)
1106 bitmap_set(mapping->bitmaps[i], start, count);
1111 * No unused range found. Try to extend the existing mapping
1112 * and perform a second attempt to reserve an IO virtual
1113 * address range of size bytes.
1115 if (i == mapping->nr_bitmaps) {
1116 if (extend_iommu_mapping(mapping)) {
1117 spin_unlock_irqrestore(&mapping->lock, flags);
1118 return DMA_ERROR_CODE;
1121 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1122 mapping->bits, 0, count, align);
1124 if (start > mapping->bits) {
1125 spin_unlock_irqrestore(&mapping->lock, flags);
1126 return DMA_ERROR_CODE;
1129 bitmap_set(mapping->bitmaps[i], start, count);
1131 spin_unlock_irqrestore(&mapping->lock, flags);
1133 iova = mapping->base + (mapping_size * i);
1134 iova += start << PAGE_SHIFT;
1139 static inline void __free_iova(struct dma_iommu_mapping *mapping,
1140 dma_addr_t addr, size_t size)
1142 unsigned int start, count;
1143 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1144 unsigned long flags;
1145 dma_addr_t bitmap_base;
1151 bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size;
1152 BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions);
1154 bitmap_base = mapping->base + mapping_size * bitmap_index;
1156 start = (addr - bitmap_base) >> PAGE_SHIFT;
1158 if (addr + size > bitmap_base + mapping_size) {
1160 * The address range to be freed reaches into the iova
1161 * range of the next bitmap. This should not happen as
1162 * we don't allow this in __alloc_iova (at the
1167 count = size >> PAGE_SHIFT;
1169 spin_lock_irqsave(&mapping->lock, flags);
1170 bitmap_clear(mapping->bitmaps[bitmap_index], start, count);
1171 spin_unlock_irqrestore(&mapping->lock, flags);
1174 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
1175 gfp_t gfp, struct dma_attrs *attrs)
1177 struct page **pages;
1178 int count = size >> PAGE_SHIFT;
1179 int array_size = count * sizeof(struct page *);
1182 if (array_size <= PAGE_SIZE)
1183 pages = kzalloc(array_size, gfp);
1185 pages = vzalloc(array_size);
1189 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs))
1191 unsigned long order = get_order(size);
1194 page = dma_alloc_from_contiguous(dev, count, order);
1198 __dma_clear_buffer(page, size);
1200 for (i = 0; i < count; i++)
1201 pages[i] = page + i;
1207 * IOMMU can map any pages, so himem can also be used here
1209 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
1212 int j, order = __fls(count);
1214 pages[i] = alloc_pages(gfp, order);
1215 while (!pages[i] && order)
1216 pages[i] = alloc_pages(gfp, --order);
1221 split_page(pages[i], order);
1224 pages[i + j] = pages[i] + j;
1227 __dma_clear_buffer(pages[i], PAGE_SIZE << order);
1229 count -= 1 << order;
1236 __free_pages(pages[i], 0);
1237 if (array_size <= PAGE_SIZE)
1244 static int __iommu_free_buffer(struct device *dev, struct page **pages,
1245 size_t size, struct dma_attrs *attrs)
1247 int count = size >> PAGE_SHIFT;
1248 int array_size = count * sizeof(struct page *);
1251 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) {
1252 dma_release_from_contiguous(dev, pages[0], count);
1254 for (i = 0; i < count; i++)
1256 __free_pages(pages[i], 0);
1259 if (array_size <= PAGE_SIZE)
1267 * Create a CPU mapping for a specified pages
1270 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1273 unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1274 struct vm_struct *area;
1277 area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
1282 area->pages = pages;
1283 area->nr_pages = nr_pages;
1284 p = (unsigned long)area->addr;
1286 for (i = 0; i < nr_pages; i++) {
1287 phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i]));
1288 if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot))
1294 unmap_kernel_range((unsigned long)area->addr, size);
1300 * Create a mapping in device IO address space for specified pages
1303 __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
1305 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1306 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1307 dma_addr_t dma_addr, iova;
1308 int i, ret = DMA_ERROR_CODE;
1310 dma_addr = __alloc_iova(mapping, size);
1311 if (dma_addr == DMA_ERROR_CODE)
1315 for (i = 0; i < count; ) {
1316 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1317 phys_addr_t phys = page_to_phys(pages[i]);
1318 unsigned int len, j;
1320 for (j = i + 1; j < count; j++, next_pfn++)
1321 if (page_to_pfn(pages[j]) != next_pfn)
1324 len = (j - i) << PAGE_SHIFT;
1325 ret = iommu_map(mapping->domain, iova, phys, len,
1326 IOMMU_READ|IOMMU_WRITE);
1334 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1335 __free_iova(mapping, dma_addr, size);
1336 return DMA_ERROR_CODE;
1339 static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1341 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1344 * add optional in-page offset from iova to size and align
1345 * result to page size
1347 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1350 iommu_unmap(mapping->domain, iova, size);
1351 __free_iova(mapping, iova, size);
1355 static struct page **__atomic_get_pages(void *addr)
1357 struct dma_pool *pool = &atomic_pool;
1358 struct page **pages = pool->pages;
1359 int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
1361 return pages + offs;
1364 static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
1366 struct vm_struct *area;
1368 if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
1369 return __atomic_get_pages(cpu_addr);
1371 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1374 area = find_vm_area(cpu_addr);
1375 if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
1380 static void *__iommu_alloc_atomic(struct device *dev, size_t size,
1386 addr = __alloc_from_pool(size, &page);
1390 *handle = __iommu_create_mapping(dev, &page, size);
1391 if (*handle == DMA_ERROR_CODE)
1397 __free_from_pool(addr, size);
1401 static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
1402 dma_addr_t handle, size_t size)
1404 __iommu_remove_mapping(dev, handle, size);
1405 __free_from_pool(cpu_addr, size);
1408 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1409 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
1411 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
1412 struct page **pages;
1415 *handle = DMA_ERROR_CODE;
1416 size = PAGE_ALIGN(size);
1418 if (!(gfp & __GFP_WAIT))
1419 return __iommu_alloc_atomic(dev, size, handle);
1422 * Following is a work-around (a.k.a. hack) to prevent pages
1423 * with __GFP_COMP being passed to split_page() which cannot
1424 * handle them. The real problem is that this flag probably
1425 * should be 0 on ARM as it is not supported on this
1426 * platform; see CONFIG_HUGETLBFS.
1428 gfp &= ~(__GFP_COMP);
1430 pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
1434 *handle = __iommu_create_mapping(dev, pages, size);
1435 if (*handle == DMA_ERROR_CODE)
1438 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1441 addr = __iommu_alloc_remap(pages, size, gfp, prot,
1442 __builtin_return_address(0));
1449 __iommu_remove_mapping(dev, *handle, size);
1451 __iommu_free_buffer(dev, pages, size, attrs);
1455 static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1456 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1457 struct dma_attrs *attrs)
1459 unsigned long uaddr = vma->vm_start;
1460 unsigned long usize = vma->vm_end - vma->vm_start;
1461 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1463 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1469 int ret = vm_insert_page(vma, uaddr, *pages++);
1471 pr_err("Remapping memory failed: %d\n", ret);
1476 } while (usize > 0);
1482 * free a page as defined by the above mapping.
1483 * Must not be called with IRQs disabled.
1485 void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1486 dma_addr_t handle, struct dma_attrs *attrs)
1488 struct page **pages;
1489 size = PAGE_ALIGN(size);
1491 if (__in_atomic_pool(cpu_addr, size)) {
1492 __iommu_free_atomic(dev, cpu_addr, handle, size);
1496 pages = __iommu_get_pages(cpu_addr, attrs);
1498 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
1502 if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
1503 unmap_kernel_range((unsigned long)cpu_addr, size);
1507 __iommu_remove_mapping(dev, handle, size);
1508 __iommu_free_buffer(dev, pages, size, attrs);
1511 static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
1512 void *cpu_addr, dma_addr_t dma_addr,
1513 size_t size, struct dma_attrs *attrs)
1515 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1516 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1521 return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
1525 static int __dma_direction_to_prot(enum dma_data_direction dir)
1530 case DMA_BIDIRECTIONAL:
1531 prot = IOMMU_READ | IOMMU_WRITE;
1536 case DMA_FROM_DEVICE:
1547 * Map a part of the scatter-gather list into contiguous io address space
1549 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1550 size_t size, dma_addr_t *handle,
1551 enum dma_data_direction dir, struct dma_attrs *attrs,
1554 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1555 dma_addr_t iova, iova_base;
1558 struct scatterlist *s;
1561 size = PAGE_ALIGN(size);
1562 *handle = DMA_ERROR_CODE;
1564 iova_base = iova = __alloc_iova(mapping, size);
1565 if (iova == DMA_ERROR_CODE)
1568 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1569 phys_addr_t phys = page_to_phys(sg_page(s));
1570 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1573 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1574 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1576 prot = __dma_direction_to_prot(dir);
1578 ret = iommu_map(mapping->domain, iova, phys, len, prot);
1581 count += len >> PAGE_SHIFT;
1584 *handle = iova_base;
1588 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1589 __free_iova(mapping, iova_base, size);
1593 static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1594 enum dma_data_direction dir, struct dma_attrs *attrs,
1597 struct scatterlist *s = sg, *dma = sg, *start = sg;
1599 unsigned int offset = s->offset;
1600 unsigned int size = s->offset + s->length;
1601 unsigned int max = dma_get_max_seg_size(dev);
1603 for (i = 1; i < nents; i++) {
1606 s->dma_address = DMA_ERROR_CODE;
1609 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1610 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1611 dir, attrs, is_coherent) < 0)
1614 dma->dma_address += offset;
1615 dma->dma_length = size - offset;
1617 size = offset = s->offset;
1624 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
1628 dma->dma_address += offset;
1629 dma->dma_length = size - offset;
1634 for_each_sg(sg, s, count, i)
1635 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1640 * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1641 * @dev: valid struct device pointer
1642 * @sg: list of buffers
1643 * @nents: number of buffers to map
1644 * @dir: DMA transfer direction
1646 * Map a set of i/o coherent buffers described by scatterlist in streaming
1647 * mode for DMA. The scatter gather list elements are merged together (if
1648 * possible) and tagged with the appropriate dma address and length. They are
1649 * obtained via sg_dma_{address,length}.
1651 int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1652 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1654 return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
1658 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1659 * @dev: valid struct device pointer
1660 * @sg: list of buffers
1661 * @nents: number of buffers to map
1662 * @dir: DMA transfer direction
1664 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1665 * The scatter gather list elements are merged together (if possible) and
1666 * tagged with the appropriate dma address and length. They are obtained via
1667 * sg_dma_{address,length}.
1669 int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1670 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1672 return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
1675 static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1676 int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
1679 struct scatterlist *s;
1682 for_each_sg(sg, s, nents, i) {
1684 __iommu_remove_mapping(dev, sg_dma_address(s),
1687 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1688 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1694 * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1695 * @dev: valid struct device pointer
1696 * @sg: list of buffers
1697 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1698 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1700 * Unmap a set of streaming mode DMA translations. Again, CPU access
1701 * rules concerning calls here are the same as for dma_unmap_single().
1703 void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1704 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1706 __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
1710 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1711 * @dev: valid struct device pointer
1712 * @sg: list of buffers
1713 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1714 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1716 * Unmap a set of streaming mode DMA translations. Again, CPU access
1717 * rules concerning calls here are the same as for dma_unmap_single().
1719 void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1720 enum dma_data_direction dir, struct dma_attrs *attrs)
1722 __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
1726 * arm_iommu_sync_sg_for_cpu
1727 * @dev: valid struct device pointer
1728 * @sg: list of buffers
1729 * @nents: number of buffers to map (returned from dma_map_sg)
1730 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1732 void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1733 int nents, enum dma_data_direction dir)
1735 struct scatterlist *s;
1738 for_each_sg(sg, s, nents, i)
1739 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1744 * arm_iommu_sync_sg_for_device
1745 * @dev: valid struct device pointer
1746 * @sg: list of buffers
1747 * @nents: number of buffers to map (returned from dma_map_sg)
1748 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1750 void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1751 int nents, enum dma_data_direction dir)
1753 struct scatterlist *s;
1756 for_each_sg(sg, s, nents, i)
1757 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1762 * arm_coherent_iommu_map_page
1763 * @dev: valid struct device pointer
1764 * @page: page that buffer resides in
1765 * @offset: offset into page for start of buffer
1766 * @size: size of buffer to map
1767 * @dir: DMA transfer direction
1769 * Coherent IOMMU aware version of arm_dma_map_page()
1771 static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
1772 unsigned long offset, size_t size, enum dma_data_direction dir,
1773 struct dma_attrs *attrs)
1775 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1776 dma_addr_t dma_addr;
1777 int ret, prot, len = PAGE_ALIGN(size + offset);
1779 dma_addr = __alloc_iova(mapping, len);
1780 if (dma_addr == DMA_ERROR_CODE)
1783 prot = __dma_direction_to_prot(dir);
1785 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
1789 return dma_addr + offset;
1791 __free_iova(mapping, dma_addr, len);
1792 return DMA_ERROR_CODE;
1796 * arm_iommu_map_page
1797 * @dev: valid struct device pointer
1798 * @page: page that buffer resides in
1799 * @offset: offset into page for start of buffer
1800 * @size: size of buffer to map
1801 * @dir: DMA transfer direction
1803 * IOMMU aware version of arm_dma_map_page()
1805 static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1806 unsigned long offset, size_t size, enum dma_data_direction dir,
1807 struct dma_attrs *attrs)
1809 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1810 __dma_page_cpu_to_dev(page, offset, size, dir);
1812 return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
1816 * arm_coherent_iommu_unmap_page
1817 * @dev: valid struct device pointer
1818 * @handle: DMA address of buffer
1819 * @size: size of buffer (same as passed to dma_map_page)
1820 * @dir: DMA transfer direction (same as passed to dma_map_page)
1822 * Coherent IOMMU aware version of arm_dma_unmap_page()
1824 static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1825 size_t size, enum dma_data_direction dir,
1826 struct dma_attrs *attrs)
1828 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1829 dma_addr_t iova = handle & PAGE_MASK;
1830 int offset = handle & ~PAGE_MASK;
1831 int len = PAGE_ALIGN(size + offset);
1836 iommu_unmap(mapping->domain, iova, len);
1837 __free_iova(mapping, iova, len);
1841 * arm_iommu_unmap_page
1842 * @dev: valid struct device pointer
1843 * @handle: DMA address of buffer
1844 * @size: size of buffer (same as passed to dma_map_page)
1845 * @dir: DMA transfer direction (same as passed to dma_map_page)
1847 * IOMMU aware version of arm_dma_unmap_page()
1849 static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1850 size_t size, enum dma_data_direction dir,
1851 struct dma_attrs *attrs)
1853 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1854 dma_addr_t iova = handle & PAGE_MASK;
1855 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1856 int offset = handle & ~PAGE_MASK;
1857 int len = PAGE_ALIGN(size + offset);
1862 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1863 __dma_page_dev_to_cpu(page, offset, size, dir);
1865 iommu_unmap(mapping->domain, iova, len);
1866 __free_iova(mapping, iova, len);
1869 static void arm_iommu_sync_single_for_cpu(struct device *dev,
1870 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1872 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1873 dma_addr_t iova = handle & PAGE_MASK;
1874 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1875 unsigned int offset = handle & ~PAGE_MASK;
1880 __dma_page_dev_to_cpu(page, offset, size, dir);
1883 static void arm_iommu_sync_single_for_device(struct device *dev,
1884 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1886 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1887 dma_addr_t iova = handle & PAGE_MASK;
1888 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1889 unsigned int offset = handle & ~PAGE_MASK;
1894 __dma_page_cpu_to_dev(page, offset, size, dir);
1897 struct dma_map_ops iommu_ops = {
1898 .alloc = arm_iommu_alloc_attrs,
1899 .free = arm_iommu_free_attrs,
1900 .mmap = arm_iommu_mmap_attrs,
1901 .get_sgtable = arm_iommu_get_sgtable,
1903 .map_page = arm_iommu_map_page,
1904 .unmap_page = arm_iommu_unmap_page,
1905 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
1906 .sync_single_for_device = arm_iommu_sync_single_for_device,
1908 .map_sg = arm_iommu_map_sg,
1909 .unmap_sg = arm_iommu_unmap_sg,
1910 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
1911 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
1913 .set_dma_mask = arm_dma_set_mask,
1916 struct dma_map_ops iommu_coherent_ops = {
1917 .alloc = arm_iommu_alloc_attrs,
1918 .free = arm_iommu_free_attrs,
1919 .mmap = arm_iommu_mmap_attrs,
1920 .get_sgtable = arm_iommu_get_sgtable,
1922 .map_page = arm_coherent_iommu_map_page,
1923 .unmap_page = arm_coherent_iommu_unmap_page,
1925 .map_sg = arm_coherent_iommu_map_sg,
1926 .unmap_sg = arm_coherent_iommu_unmap_sg,
1928 .set_dma_mask = arm_dma_set_mask,
1932 * arm_iommu_create_mapping
1933 * @bus: pointer to the bus holding the client device (for IOMMU calls)
1934 * @base: start address of the valid IO address space
1935 * @size: maximum size of the valid IO address space
1937 * Creates a mapping structure which holds information about used/unused
1938 * IO address ranges, which is required to perform memory allocation and
1939 * mapping with IOMMU aware functions.
1941 * The client device need to be attached to the mapping with
1942 * arm_iommu_attach_device function.
1944 struct dma_iommu_mapping *
1945 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size)
1947 unsigned int bits = size >> PAGE_SHIFT;
1948 unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long);
1949 struct dma_iommu_mapping *mapping;
1954 return ERR_PTR(-EINVAL);
1956 if (bitmap_size > PAGE_SIZE) {
1957 extensions = bitmap_size / PAGE_SIZE;
1958 bitmap_size = PAGE_SIZE;
1961 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
1965 mapping->bitmap_size = bitmap_size;
1966 mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *),
1968 if (!mapping->bitmaps)
1971 mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL);
1972 if (!mapping->bitmaps[0])
1975 mapping->nr_bitmaps = 1;
1976 mapping->extensions = extensions;
1977 mapping->base = base;
1978 mapping->bits = BITS_PER_BYTE * bitmap_size;
1980 spin_lock_init(&mapping->lock);
1982 mapping->domain = iommu_domain_alloc(bus);
1983 if (!mapping->domain)
1986 kref_init(&mapping->kref);
1989 kfree(mapping->bitmaps[0]);
1991 kfree(mapping->bitmaps);
1995 return ERR_PTR(err);
1997 EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
1999 static void release_iommu_mapping(struct kref *kref)
2002 struct dma_iommu_mapping *mapping =
2003 container_of(kref, struct dma_iommu_mapping, kref);
2005 iommu_domain_free(mapping->domain);
2006 for (i = 0; i < mapping->nr_bitmaps; i++)
2007 kfree(mapping->bitmaps[i]);
2008 kfree(mapping->bitmaps);
2012 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping)
2016 if (mapping->nr_bitmaps > mapping->extensions)
2019 next_bitmap = mapping->nr_bitmaps;
2020 mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size,
2022 if (!mapping->bitmaps[next_bitmap])
2025 mapping->nr_bitmaps++;
2030 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
2033 kref_put(&mapping->kref, release_iommu_mapping);
2035 EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
2038 * arm_iommu_attach_device
2039 * @dev: valid struct device pointer
2040 * @mapping: io address space mapping structure (returned from
2041 * arm_iommu_create_mapping)
2043 * Attaches specified io address space mapping to the provided device,
2044 * this replaces the dma operations (dma_map_ops pointer) with the
2045 * IOMMU aware version. More than one client might be attached to
2046 * the same io address space mapping.
2048 int arm_iommu_attach_device(struct device *dev,
2049 struct dma_iommu_mapping *mapping)
2053 err = iommu_attach_device(mapping->domain, dev);
2057 kref_get(&mapping->kref);
2058 dev->archdata.mapping = mapping;
2059 set_dma_ops(dev, &iommu_ops);
2061 pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
2064 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
2067 * arm_iommu_detach_device
2068 * @dev: valid struct device pointer
2070 * Detaches the provided device from a previously attached map.
2071 * This voids the dma operations (dma_map_ops pointer)
2073 void arm_iommu_detach_device(struct device *dev)
2075 struct dma_iommu_mapping *mapping;
2077 mapping = to_dma_iommu_mapping(dev);
2079 dev_warn(dev, "Not attached\n");
2083 iommu_detach_device(mapping->domain, dev);
2084 kref_put(&mapping->kref, release_iommu_mapping);
2085 dev->archdata.mapping = NULL;
2086 set_dma_ops(dev, NULL);
2088 pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
2090 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);