2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/bootmem.h>
13 #include <linux/module.h>
15 #include <linux/gfp.h>
16 #include <linux/errno.h>
17 #include <linux/list.h>
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/dma-contiguous.h>
22 #include <linux/highmem.h>
23 #include <linux/memblock.h>
24 #include <linux/slab.h>
25 #include <linux/iommu.h>
27 #include <linux/vmalloc.h>
28 #include <linux/sizes.h>
30 #include <asm/memory.h>
31 #include <asm/highmem.h>
32 #include <asm/cacheflush.h>
33 #include <asm/tlbflush.h>
34 #include <asm/mach/arch.h>
35 #include <asm/dma-iommu.h>
36 #include <asm/mach/map.h>
37 #include <asm/system_info.h>
38 #include <asm/dma-contiguous.h>
43 * The DMA API is built upon the notion of "buffer ownership". A buffer
44 * is either exclusively owned by the CPU (and therefore may be accessed
45 * by it) or exclusively owned by the DMA device. These helper functions
46 * represent the transitions between these two ownership states.
48 * Note, however, that on later ARMs, this notion does not work due to
49 * speculative prefetches. We model our approach on the assumption that
50 * the CPU does do speculative prefetches, which means we clean caches
51 * before transfers and delay cache invalidation until transfer completion.
54 static void __dma_page_cpu_to_dev(struct page *, unsigned long,
55 size_t, enum dma_data_direction);
56 static void __dma_page_dev_to_cpu(struct page *, unsigned long,
57 size_t, enum dma_data_direction);
60 * arm_dma_map_page - map a portion of a page for streaming DMA
61 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
62 * @page: page that buffer resides in
63 * @offset: offset into page for start of buffer
64 * @size: size of buffer to map
65 * @dir: DMA transfer direction
67 * Ensure that any data held in the cache is appropriately discarded
70 * The device owns this memory once this call has completed. The CPU
71 * can regain ownership by calling dma_unmap_page().
73 static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
74 unsigned long offset, size_t size, enum dma_data_direction dir,
75 struct dma_attrs *attrs)
77 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
78 __dma_page_cpu_to_dev(page, offset, size, dir);
79 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
82 static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
83 unsigned long offset, size_t size, enum dma_data_direction dir,
84 struct dma_attrs *attrs)
86 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
90 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
91 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
92 * @handle: DMA address of buffer
93 * @size: size of buffer (same as passed to dma_map_page)
94 * @dir: DMA transfer direction (same as passed to dma_map_page)
96 * Unmap a page streaming mode DMA translation. The handle and size
97 * must match what was provided in the previous dma_map_page() call.
98 * All other usages are undefined.
100 * After this call, reads by the CPU to the buffer are guaranteed to see
101 * whatever the device wrote there.
103 static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
104 size_t size, enum dma_data_direction dir,
105 struct dma_attrs *attrs)
107 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
108 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
109 handle & ~PAGE_MASK, size, dir);
112 static void arm_dma_sync_single_for_cpu(struct device *dev,
113 dma_addr_t handle, size_t size, enum dma_data_direction dir)
115 unsigned int offset = handle & (PAGE_SIZE - 1);
116 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
117 __dma_page_dev_to_cpu(page, offset, size, dir);
120 static void arm_dma_sync_single_for_device(struct device *dev,
121 dma_addr_t handle, size_t size, enum dma_data_direction dir)
123 unsigned int offset = handle & (PAGE_SIZE - 1);
124 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
125 __dma_page_cpu_to_dev(page, offset, size, dir);
128 struct dma_map_ops arm_dma_ops = {
129 .alloc = arm_dma_alloc,
130 .free = arm_dma_free,
131 .mmap = arm_dma_mmap,
132 .get_sgtable = arm_dma_get_sgtable,
133 .map_page = arm_dma_map_page,
134 .unmap_page = arm_dma_unmap_page,
135 .map_sg = arm_dma_map_sg,
136 .unmap_sg = arm_dma_unmap_sg,
137 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
138 .sync_single_for_device = arm_dma_sync_single_for_device,
139 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
140 .sync_sg_for_device = arm_dma_sync_sg_for_device,
141 .set_dma_mask = arm_dma_set_mask,
143 EXPORT_SYMBOL(arm_dma_ops);
145 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
146 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
147 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
148 dma_addr_t handle, struct dma_attrs *attrs);
150 struct dma_map_ops arm_coherent_dma_ops = {
151 .alloc = arm_coherent_dma_alloc,
152 .free = arm_coherent_dma_free,
153 .mmap = arm_dma_mmap,
154 .get_sgtable = arm_dma_get_sgtable,
155 .map_page = arm_coherent_dma_map_page,
156 .map_sg = arm_dma_map_sg,
157 .set_dma_mask = arm_dma_set_mask,
159 EXPORT_SYMBOL(arm_coherent_dma_ops);
161 static int __dma_supported(struct device *dev, u64 mask, bool warn)
163 unsigned long max_dma_pfn;
166 * If the mask allows for more memory than we can address,
167 * and we actually have that much memory, then we must
168 * indicate that DMA to this device is not supported.
170 if (sizeof(mask) != sizeof(dma_addr_t) &&
171 mask > (dma_addr_t)~0 &&
172 dma_to_pfn(dev, ~0) < max_pfn) {
174 dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n",
176 dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n");
181 max_dma_pfn = min(max_pfn, arm_dma_pfn_limit);
184 * Translate the device's DMA mask to a PFN limit. This
185 * PFN number includes the page which we can DMA to.
187 if (dma_to_pfn(dev, mask) < max_dma_pfn) {
189 dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n",
191 dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1,
199 static u64 get_coherent_dma_mask(struct device *dev)
201 u64 mask = (u64)DMA_BIT_MASK(32);
204 mask = dev->coherent_dma_mask;
207 * Sanity check the DMA mask - it must be non-zero, and
208 * must be able to be satisfied by a DMA allocation.
211 dev_warn(dev, "coherent DMA mask is unset\n");
215 if (!__dma_supported(dev, mask, true))
222 static void __dma_clear_buffer(struct page *page, size_t size)
225 * Ensure that the allocated pages are zeroed, and that any data
226 * lurking in the kernel direct-mapped region is invalidated.
228 if (PageHighMem(page)) {
229 phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
230 phys_addr_t end = base + size;
232 void *ptr = kmap_atomic(page);
233 memset(ptr, 0, PAGE_SIZE);
234 dmac_flush_range(ptr, ptr + PAGE_SIZE);
239 outer_flush_range(base, end);
241 void *ptr = page_address(page);
242 memset(ptr, 0, size);
243 dmac_flush_range(ptr, ptr + size);
244 outer_flush_range(__pa(ptr), __pa(ptr) + size);
249 * Allocate a DMA buffer for 'dev' of size 'size' using the
250 * specified gfp mask. Note that 'size' must be page aligned.
252 static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
254 unsigned long order = get_order(size);
255 struct page *page, *p, *e;
257 page = alloc_pages(gfp, order);
262 * Now split the huge page and free the excess pages
264 split_page(page, order);
265 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
268 __dma_clear_buffer(page, size);
274 * Free a DMA buffer. 'size' must be page aligned.
276 static void __dma_free_buffer(struct page *page, size_t size)
278 struct page *e = page + (size >> PAGE_SHIFT);
288 static void *__alloc_from_contiguous(struct device *dev, size_t size,
289 pgprot_t prot, struct page **ret_page,
292 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
293 pgprot_t prot, struct page **ret_page,
297 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
300 struct vm_struct *area;
304 * DMA allocation can be mapped to user space, so lets
305 * set VM_USERMAP flags too.
307 area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
311 addr = (unsigned long)area->addr;
312 area->phys_addr = __pfn_to_phys(page_to_pfn(page));
314 if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) {
315 vunmap((void *)addr);
321 static void __dma_free_remap(void *cpu_addr, size_t size)
323 unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP;
324 struct vm_struct *area = find_vm_area(cpu_addr);
325 if (!area || (area->flags & flags) != flags) {
326 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
329 unmap_kernel_range((unsigned long)cpu_addr, size);
333 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
338 unsigned long *bitmap;
339 unsigned long nr_pages;
344 static struct dma_pool atomic_pool = {
345 .size = DEFAULT_DMA_COHERENT_POOL_SIZE,
348 static int __init early_coherent_pool(char *p)
350 atomic_pool.size = memparse(p, &p);
353 early_param("coherent_pool", early_coherent_pool);
355 void __init init_dma_coherent_pool_size(unsigned long size)
358 * Catch any attempt to set the pool size too late.
360 BUG_ON(atomic_pool.vaddr);
363 * Set architecture specific coherent pool size only if
364 * it has not been changed by kernel command line parameter.
366 if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE)
367 atomic_pool.size = size;
371 * Initialise the coherent pool for atomic allocations.
373 static int __init atomic_pool_init(void)
375 struct dma_pool *pool = &atomic_pool;
376 pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL);
377 gfp_t gfp = GFP_KERNEL | GFP_DMA;
378 unsigned long nr_pages = pool->size >> PAGE_SHIFT;
379 unsigned long *bitmap;
383 int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
385 bitmap = kzalloc(bitmap_size, GFP_KERNEL);
389 pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
393 if (dev_get_cma_area(NULL))
394 ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
397 ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page,
402 for (i = 0; i < nr_pages; i++)
405 spin_lock_init(&pool->lock);
408 pool->bitmap = bitmap;
409 pool->nr_pages = nr_pages;
410 pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
411 (unsigned)pool->size / 1024);
419 pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
420 (unsigned)pool->size / 1024);
424 * CMA is activated by core_initcall, so we must be called after it.
426 postcore_initcall(atomic_pool_init);
428 struct dma_contig_early_reserve {
433 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
435 static int dma_mmu_remap_num __initdata;
437 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
439 dma_mmu_remap[dma_mmu_remap_num].base = base;
440 dma_mmu_remap[dma_mmu_remap_num].size = size;
444 void __init dma_contiguous_remap(void)
447 for (i = 0; i < dma_mmu_remap_num; i++) {
448 phys_addr_t start = dma_mmu_remap[i].base;
449 phys_addr_t end = start + dma_mmu_remap[i].size;
453 if (end > arm_lowmem_limit)
454 end = arm_lowmem_limit;
458 map.pfn = __phys_to_pfn(start);
459 map.virtual = __phys_to_virt(start);
460 map.length = end - start;
461 map.type = MT_MEMORY_DMA_READY;
464 * Clear previous low-memory mapping
466 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
468 pmd_clear(pmd_off_k(addr));
470 iotable_init(&map, 1);
474 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
477 struct page *page = virt_to_page(addr);
478 pgprot_t prot = *(pgprot_t *)data;
480 set_pte_ext(pte, mk_pte(page, prot), 0);
484 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
486 unsigned long start = (unsigned long) page_address(page);
487 unsigned end = start + size;
489 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
490 flush_tlb_kernel_range(start, end);
493 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
494 pgprot_t prot, struct page **ret_page,
499 page = __dma_alloc_buffer(dev, size, gfp);
503 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
505 __dma_free_buffer(page, size);
513 static void *__alloc_from_pool(size_t size, struct page **ret_page)
515 struct dma_pool *pool = &atomic_pool;
516 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
520 unsigned long align_mask;
523 WARN(1, "coherent pool not initialised!\n");
528 * Align the region allocation - allocations from pool are rather
529 * small, so align them to their order in pages, minimum is a page
530 * size. This helps reduce fragmentation of the DMA space.
532 align_mask = (1 << get_order(size)) - 1;
534 spin_lock_irqsave(&pool->lock, flags);
535 pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages,
536 0, count, align_mask);
537 if (pageno < pool->nr_pages) {
538 bitmap_set(pool->bitmap, pageno, count);
539 ptr = pool->vaddr + PAGE_SIZE * pageno;
540 *ret_page = pool->pages[pageno];
542 pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
543 "Please increase it with coherent_pool= kernel parameter!\n",
544 (unsigned)pool->size / 1024);
546 spin_unlock_irqrestore(&pool->lock, flags);
551 static bool __in_atomic_pool(void *start, size_t size)
553 struct dma_pool *pool = &atomic_pool;
554 void *end = start + size;
555 void *pool_start = pool->vaddr;
556 void *pool_end = pool->vaddr + pool->size;
558 if (start < pool_start || start >= pool_end)
564 WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
565 start, end - 1, pool_start, pool_end - 1);
570 static int __free_from_pool(void *start, size_t size)
572 struct dma_pool *pool = &atomic_pool;
573 unsigned long pageno, count;
576 if (!__in_atomic_pool(start, size))
579 pageno = (start - pool->vaddr) >> PAGE_SHIFT;
580 count = size >> PAGE_SHIFT;
582 spin_lock_irqsave(&pool->lock, flags);
583 bitmap_clear(pool->bitmap, pageno, count);
584 spin_unlock_irqrestore(&pool->lock, flags);
589 static void *__alloc_from_contiguous(struct device *dev, size_t size,
590 pgprot_t prot, struct page **ret_page,
593 unsigned long order = get_order(size);
594 size_t count = size >> PAGE_SHIFT;
598 page = dma_alloc_from_contiguous(dev, count, order);
602 __dma_clear_buffer(page, size);
604 if (PageHighMem(page)) {
605 ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
607 dma_release_from_contiguous(dev, page, count);
611 __dma_remap(page, size, prot);
612 ptr = page_address(page);
618 static void __free_from_contiguous(struct device *dev, struct page *page,
619 void *cpu_addr, size_t size)
621 if (PageHighMem(page))
622 __dma_free_remap(cpu_addr, size);
624 __dma_remap(page, size, PAGE_KERNEL);
625 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
628 static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
630 prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
631 pgprot_writecombine(prot) :
632 pgprot_dmacoherent(prot);
638 #else /* !CONFIG_MMU */
642 #define __get_dma_pgprot(attrs, prot) __pgprot(0)
643 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL
644 #define __alloc_from_pool(size, ret_page) NULL
645 #define __alloc_from_contiguous(dev, size, prot, ret, c) NULL
646 #define __free_from_pool(cpu_addr, size) 0
647 #define __free_from_contiguous(dev, page, cpu_addr, size) do { } while (0)
648 #define __dma_free_remap(cpu_addr, size) do { } while (0)
650 #endif /* CONFIG_MMU */
652 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
653 struct page **ret_page)
656 page = __dma_alloc_buffer(dev, size, gfp);
661 return page_address(page);
666 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
667 gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller)
669 u64 mask = get_coherent_dma_mask(dev);
670 struct page *page = NULL;
673 #ifdef CONFIG_DMA_API_DEBUG
674 u64 limit = (mask + 1) & ~mask;
675 if (limit && size >= limit) {
676 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
685 if (mask < 0xffffffffULL)
689 * Following is a work-around (a.k.a. hack) to prevent pages
690 * with __GFP_COMP being passed to split_page() which cannot
691 * handle them. The real problem is that this flag probably
692 * should be 0 on ARM as it is not supported on this
693 * platform; see CONFIG_HUGETLBFS.
695 gfp &= ~(__GFP_COMP);
697 *handle = DMA_ERROR_CODE;
698 size = PAGE_ALIGN(size);
700 if (is_coherent || nommu())
701 addr = __alloc_simple_buffer(dev, size, gfp, &page);
702 else if (!(gfp & __GFP_WAIT))
703 addr = __alloc_from_pool(size, &page);
704 else if (!dev_get_cma_area(dev))
705 addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
707 addr = __alloc_from_contiguous(dev, size, prot, &page, caller);
710 *handle = pfn_to_dma(dev, page_to_pfn(page));
716 * Allocate DMA-coherent memory space and return both the kernel remapped
717 * virtual and bus address for that space.
719 void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
720 gfp_t gfp, struct dma_attrs *attrs)
722 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
725 if (dma_alloc_from_coherent(dev, size, handle, &memory))
728 return __dma_alloc(dev, size, handle, gfp, prot, false,
729 __builtin_return_address(0));
732 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
733 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
735 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
738 if (dma_alloc_from_coherent(dev, size, handle, &memory))
741 return __dma_alloc(dev, size, handle, gfp, prot, true,
742 __builtin_return_address(0));
746 * Create userspace mapping for the DMA-coherent memory.
748 int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
749 void *cpu_addr, dma_addr_t dma_addr, size_t size,
750 struct dma_attrs *attrs)
754 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
755 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
756 unsigned long pfn = dma_to_pfn(dev, dma_addr);
757 unsigned long off = vma->vm_pgoff;
759 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
761 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
764 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
765 ret = remap_pfn_range(vma, vma->vm_start,
767 vma->vm_end - vma->vm_start,
770 #endif /* CONFIG_MMU */
776 * Free a buffer as defined by the above mapping.
778 static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
779 dma_addr_t handle, struct dma_attrs *attrs,
782 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
784 if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
787 size = PAGE_ALIGN(size);
789 if (is_coherent || nommu()) {
790 __dma_free_buffer(page, size);
791 } else if (__free_from_pool(cpu_addr, size)) {
793 } else if (!dev_get_cma_area(dev)) {
794 __dma_free_remap(cpu_addr, size);
795 __dma_free_buffer(page, size);
798 * Non-atomic allocations cannot be freed with IRQs disabled
800 WARN_ON(irqs_disabled());
801 __free_from_contiguous(dev, page, cpu_addr, size);
805 void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
806 dma_addr_t handle, struct dma_attrs *attrs)
808 __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
811 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
812 dma_addr_t handle, struct dma_attrs *attrs)
814 __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
817 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
818 void *cpu_addr, dma_addr_t handle, size_t size,
819 struct dma_attrs *attrs)
821 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
824 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
828 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
832 static void dma_cache_maint_page(struct page *page, unsigned long offset,
833 size_t size, enum dma_data_direction dir,
834 void (*op)(const void *, size_t, int))
839 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
843 * A single sg entry may refer to multiple physically contiguous
844 * pages. But we still need to process highmem pages individually.
845 * If highmem is not configured then the bulk of this loop gets
852 page = pfn_to_page(pfn);
854 if (PageHighMem(page)) {
855 if (len + offset > PAGE_SIZE)
856 len = PAGE_SIZE - offset;
858 if (cache_is_vipt_nonaliasing()) {
859 vaddr = kmap_atomic(page);
860 op(vaddr + offset, len, dir);
861 kunmap_atomic(vaddr);
863 vaddr = kmap_high_get(page);
865 op(vaddr + offset, len, dir);
870 vaddr = page_address(page) + offset;
880 * Make an area consistent for devices.
881 * Note: Drivers should NOT use this function directly, as it will break
882 * platforms with CONFIG_DMABOUNCE.
883 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
885 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
886 size_t size, enum dma_data_direction dir)
890 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
892 paddr = page_to_phys(page) + off;
893 if (dir == DMA_FROM_DEVICE) {
894 outer_inv_range(paddr, paddr + size);
896 outer_clean_range(paddr, paddr + size);
898 /* FIXME: non-speculating: flush on bidirectional mappings? */
901 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
902 size_t size, enum dma_data_direction dir)
904 phys_addr_t paddr = page_to_phys(page) + off;
906 /* FIXME: non-speculating: not required */
907 /* in any case, don't bother invalidating if DMA to device */
908 if (dir != DMA_TO_DEVICE) {
909 outer_inv_range(paddr, paddr + size);
911 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
915 * Mark the D-cache clean for these pages to avoid extra flushing.
917 if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
921 pfn = page_to_pfn(page) + off / PAGE_SIZE;
925 left -= PAGE_SIZE - off;
927 while (left >= PAGE_SIZE) {
928 page = pfn_to_page(pfn++);
929 set_bit(PG_dcache_clean, &page->flags);
936 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
937 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
938 * @sg: list of buffers
939 * @nents: number of buffers to map
940 * @dir: DMA transfer direction
942 * Map a set of buffers described by scatterlist in streaming mode for DMA.
943 * This is the scatter-gather version of the dma_map_single interface.
944 * Here the scatter gather list elements are each tagged with the
945 * appropriate dma address and length. They are obtained via
946 * sg_dma_{address,length}.
948 * Device ownership issues as mentioned for dma_map_single are the same
951 int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
952 enum dma_data_direction dir, struct dma_attrs *attrs)
954 struct dma_map_ops *ops = get_dma_ops(dev);
955 struct scatterlist *s;
958 for_each_sg(sg, s, nents, i) {
959 #ifdef CONFIG_NEED_SG_DMA_LENGTH
960 s->dma_length = s->length;
962 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
963 s->length, dir, attrs);
964 if (dma_mapping_error(dev, s->dma_address))
970 for_each_sg(sg, s, i, j)
971 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
976 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
977 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
978 * @sg: list of buffers
979 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
980 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
982 * Unmap a set of streaming mode DMA translations. Again, CPU access
983 * rules concerning calls here are the same as for dma_unmap_single().
985 void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
986 enum dma_data_direction dir, struct dma_attrs *attrs)
988 struct dma_map_ops *ops = get_dma_ops(dev);
989 struct scatterlist *s;
993 for_each_sg(sg, s, nents, i)
994 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
998 * arm_dma_sync_sg_for_cpu
999 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1000 * @sg: list of buffers
1001 * @nents: number of buffers to map (returned from dma_map_sg)
1002 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1004 void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1005 int nents, enum dma_data_direction dir)
1007 struct dma_map_ops *ops = get_dma_ops(dev);
1008 struct scatterlist *s;
1011 for_each_sg(sg, s, nents, i)
1012 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
1017 * arm_dma_sync_sg_for_device
1018 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1019 * @sg: list of buffers
1020 * @nents: number of buffers to map (returned from dma_map_sg)
1021 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1023 void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1024 int nents, enum dma_data_direction dir)
1026 struct dma_map_ops *ops = get_dma_ops(dev);
1027 struct scatterlist *s;
1030 for_each_sg(sg, s, nents, i)
1031 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
1036 * Return whether the given device DMA address mask can be supported
1037 * properly. For example, if your device can only drive the low 24-bits
1038 * during bus mastering, then you would pass 0x00ffffff as the mask
1041 int dma_supported(struct device *dev, u64 mask)
1043 return __dma_supported(dev, mask, false);
1045 EXPORT_SYMBOL(dma_supported);
1047 int arm_dma_set_mask(struct device *dev, u64 dma_mask)
1049 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
1052 *dev->dma_mask = dma_mask;
1057 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
1059 static int __init dma_debug_do_init(void)
1061 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1064 fs_initcall(dma_debug_do_init);
1066 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1070 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping);
1072 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1075 unsigned int order = get_order(size);
1076 unsigned int align = 0;
1077 unsigned int count, start;
1078 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1079 unsigned long flags;
1083 if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
1084 order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
1086 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1087 align = (1 << order) - 1;
1089 spin_lock_irqsave(&mapping->lock, flags);
1090 for (i = 0; i < mapping->nr_bitmaps; i++) {
1091 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1092 mapping->bits, 0, count, align);
1094 if (start > mapping->bits)
1097 bitmap_set(mapping->bitmaps[i], start, count);
1102 * No unused range found. Try to extend the existing mapping
1103 * and perform a second attempt to reserve an IO virtual
1104 * address range of size bytes.
1106 if (i == mapping->nr_bitmaps) {
1107 if (extend_iommu_mapping(mapping)) {
1108 spin_unlock_irqrestore(&mapping->lock, flags);
1109 return DMA_ERROR_CODE;
1112 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1113 mapping->bits, 0, count, align);
1115 if (start > mapping->bits) {
1116 spin_unlock_irqrestore(&mapping->lock, flags);
1117 return DMA_ERROR_CODE;
1120 bitmap_set(mapping->bitmaps[i], start, count);
1122 spin_unlock_irqrestore(&mapping->lock, flags);
1124 iova = mapping->base + (mapping_size * i);
1125 iova += start << PAGE_SHIFT;
1130 static inline void __free_iova(struct dma_iommu_mapping *mapping,
1131 dma_addr_t addr, size_t size)
1133 unsigned int start, count;
1134 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1135 unsigned long flags;
1136 dma_addr_t bitmap_base;
1142 bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size;
1143 BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions);
1145 bitmap_base = mapping->base + mapping_size * bitmap_index;
1147 start = (addr - bitmap_base) >> PAGE_SHIFT;
1149 if (addr + size > bitmap_base + mapping_size) {
1151 * The address range to be freed reaches into the iova
1152 * range of the next bitmap. This should not happen as
1153 * we don't allow this in __alloc_iova (at the
1158 count = size >> PAGE_SHIFT;
1160 spin_lock_irqsave(&mapping->lock, flags);
1161 bitmap_clear(mapping->bitmaps[bitmap_index], start, count);
1162 spin_unlock_irqrestore(&mapping->lock, flags);
1165 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
1166 gfp_t gfp, struct dma_attrs *attrs)
1168 struct page **pages;
1169 int count = size >> PAGE_SHIFT;
1170 int array_size = count * sizeof(struct page *);
1173 if (array_size <= PAGE_SIZE)
1174 pages = kzalloc(array_size, gfp);
1176 pages = vzalloc(array_size);
1180 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs))
1182 unsigned long order = get_order(size);
1185 page = dma_alloc_from_contiguous(dev, count, order);
1189 __dma_clear_buffer(page, size);
1191 for (i = 0; i < count; i++)
1192 pages[i] = page + i;
1198 * IOMMU can map any pages, so himem can also be used here
1200 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
1203 int j, order = __fls(count);
1205 pages[i] = alloc_pages(gfp, order);
1206 while (!pages[i] && order)
1207 pages[i] = alloc_pages(gfp, --order);
1212 split_page(pages[i], order);
1215 pages[i + j] = pages[i] + j;
1218 __dma_clear_buffer(pages[i], PAGE_SIZE << order);
1220 count -= 1 << order;
1227 __free_pages(pages[i], 0);
1228 if (array_size <= PAGE_SIZE)
1235 static int __iommu_free_buffer(struct device *dev, struct page **pages,
1236 size_t size, struct dma_attrs *attrs)
1238 int count = size >> PAGE_SHIFT;
1239 int array_size = count * sizeof(struct page *);
1242 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) {
1243 dma_release_from_contiguous(dev, pages[0], count);
1245 for (i = 0; i < count; i++)
1247 __free_pages(pages[i], 0);
1250 if (array_size <= PAGE_SIZE)
1258 * Create a CPU mapping for a specified pages
1261 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1264 unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1265 struct vm_struct *area;
1268 area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
1273 area->pages = pages;
1274 area->nr_pages = nr_pages;
1275 p = (unsigned long)area->addr;
1277 for (i = 0; i < nr_pages; i++) {
1278 phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i]));
1279 if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot))
1285 unmap_kernel_range((unsigned long)area->addr, size);
1291 * Create a mapping in device IO address space for specified pages
1294 __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
1296 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1297 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1298 dma_addr_t dma_addr, iova;
1299 int i, ret = DMA_ERROR_CODE;
1301 dma_addr = __alloc_iova(mapping, size);
1302 if (dma_addr == DMA_ERROR_CODE)
1306 for (i = 0; i < count; ) {
1307 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1308 phys_addr_t phys = page_to_phys(pages[i]);
1309 unsigned int len, j;
1311 for (j = i + 1; j < count; j++, next_pfn++)
1312 if (page_to_pfn(pages[j]) != next_pfn)
1315 len = (j - i) << PAGE_SHIFT;
1316 ret = iommu_map(mapping->domain, iova, phys, len,
1317 IOMMU_READ|IOMMU_WRITE);
1325 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1326 __free_iova(mapping, dma_addr, size);
1327 return DMA_ERROR_CODE;
1330 static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1332 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1335 * add optional in-page offset from iova to size and align
1336 * result to page size
1338 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1341 iommu_unmap(mapping->domain, iova, size);
1342 __free_iova(mapping, iova, size);
1346 static struct page **__atomic_get_pages(void *addr)
1348 struct dma_pool *pool = &atomic_pool;
1349 struct page **pages = pool->pages;
1350 int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
1352 return pages + offs;
1355 static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
1357 struct vm_struct *area;
1359 if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
1360 return __atomic_get_pages(cpu_addr);
1362 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1365 area = find_vm_area(cpu_addr);
1366 if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
1371 static void *__iommu_alloc_atomic(struct device *dev, size_t size,
1377 addr = __alloc_from_pool(size, &page);
1381 *handle = __iommu_create_mapping(dev, &page, size);
1382 if (*handle == DMA_ERROR_CODE)
1388 __free_from_pool(addr, size);
1392 static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
1393 dma_addr_t handle, size_t size)
1395 __iommu_remove_mapping(dev, handle, size);
1396 __free_from_pool(cpu_addr, size);
1399 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1400 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
1402 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
1403 struct page **pages;
1406 *handle = DMA_ERROR_CODE;
1407 size = PAGE_ALIGN(size);
1409 if (!(gfp & __GFP_WAIT))
1410 return __iommu_alloc_atomic(dev, size, handle);
1413 * Following is a work-around (a.k.a. hack) to prevent pages
1414 * with __GFP_COMP being passed to split_page() which cannot
1415 * handle them. The real problem is that this flag probably
1416 * should be 0 on ARM as it is not supported on this
1417 * platform; see CONFIG_HUGETLBFS.
1419 gfp &= ~(__GFP_COMP);
1421 pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
1425 *handle = __iommu_create_mapping(dev, pages, size);
1426 if (*handle == DMA_ERROR_CODE)
1429 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1432 addr = __iommu_alloc_remap(pages, size, gfp, prot,
1433 __builtin_return_address(0));
1440 __iommu_remove_mapping(dev, *handle, size);
1442 __iommu_free_buffer(dev, pages, size, attrs);
1446 static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1447 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1448 struct dma_attrs *attrs)
1450 unsigned long uaddr = vma->vm_start;
1451 unsigned long usize = vma->vm_end - vma->vm_start;
1452 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1454 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1460 int ret = vm_insert_page(vma, uaddr, *pages++);
1462 pr_err("Remapping memory failed: %d\n", ret);
1467 } while (usize > 0);
1473 * free a page as defined by the above mapping.
1474 * Must not be called with IRQs disabled.
1476 void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1477 dma_addr_t handle, struct dma_attrs *attrs)
1479 struct page **pages;
1480 size = PAGE_ALIGN(size);
1482 if (__in_atomic_pool(cpu_addr, size)) {
1483 __iommu_free_atomic(dev, cpu_addr, handle, size);
1487 pages = __iommu_get_pages(cpu_addr, attrs);
1489 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
1493 if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
1494 unmap_kernel_range((unsigned long)cpu_addr, size);
1498 __iommu_remove_mapping(dev, handle, size);
1499 __iommu_free_buffer(dev, pages, size, attrs);
1502 static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
1503 void *cpu_addr, dma_addr_t dma_addr,
1504 size_t size, struct dma_attrs *attrs)
1506 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1507 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1512 return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
1516 static int __dma_direction_to_prot(enum dma_data_direction dir)
1521 case DMA_BIDIRECTIONAL:
1522 prot = IOMMU_READ | IOMMU_WRITE;
1527 case DMA_FROM_DEVICE:
1538 * Map a part of the scatter-gather list into contiguous io address space
1540 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1541 size_t size, dma_addr_t *handle,
1542 enum dma_data_direction dir, struct dma_attrs *attrs,
1545 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1546 dma_addr_t iova, iova_base;
1549 struct scatterlist *s;
1552 size = PAGE_ALIGN(size);
1553 *handle = DMA_ERROR_CODE;
1555 iova_base = iova = __alloc_iova(mapping, size);
1556 if (iova == DMA_ERROR_CODE)
1559 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1560 phys_addr_t phys = page_to_phys(sg_page(s));
1561 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1564 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1565 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1567 prot = __dma_direction_to_prot(dir);
1569 ret = iommu_map(mapping->domain, iova, phys, len, prot);
1572 count += len >> PAGE_SHIFT;
1575 *handle = iova_base;
1579 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1580 __free_iova(mapping, iova_base, size);
1584 static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1585 enum dma_data_direction dir, struct dma_attrs *attrs,
1588 struct scatterlist *s = sg, *dma = sg, *start = sg;
1590 unsigned int offset = s->offset;
1591 unsigned int size = s->offset + s->length;
1592 unsigned int max = dma_get_max_seg_size(dev);
1594 for (i = 1; i < nents; i++) {
1597 s->dma_address = DMA_ERROR_CODE;
1600 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1601 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1602 dir, attrs, is_coherent) < 0)
1605 dma->dma_address += offset;
1606 dma->dma_length = size - offset;
1608 size = offset = s->offset;
1615 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
1619 dma->dma_address += offset;
1620 dma->dma_length = size - offset;
1625 for_each_sg(sg, s, count, i)
1626 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1631 * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1632 * @dev: valid struct device pointer
1633 * @sg: list of buffers
1634 * @nents: number of buffers to map
1635 * @dir: DMA transfer direction
1637 * Map a set of i/o coherent buffers described by scatterlist in streaming
1638 * mode for DMA. The scatter gather list elements are merged together (if
1639 * possible) and tagged with the appropriate dma address and length. They are
1640 * obtained via sg_dma_{address,length}.
1642 int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1643 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1645 return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
1649 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1650 * @dev: valid struct device pointer
1651 * @sg: list of buffers
1652 * @nents: number of buffers to map
1653 * @dir: DMA transfer direction
1655 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1656 * The scatter gather list elements are merged together (if possible) and
1657 * tagged with the appropriate dma address and length. They are obtained via
1658 * sg_dma_{address,length}.
1660 int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1661 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1663 return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
1666 static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1667 int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
1670 struct scatterlist *s;
1673 for_each_sg(sg, s, nents, i) {
1675 __iommu_remove_mapping(dev, sg_dma_address(s),
1678 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1679 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1685 * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1686 * @dev: valid struct device pointer
1687 * @sg: list of buffers
1688 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1689 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1691 * Unmap a set of streaming mode DMA translations. Again, CPU access
1692 * rules concerning calls here are the same as for dma_unmap_single().
1694 void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1695 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1697 __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
1701 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1702 * @dev: valid struct device pointer
1703 * @sg: list of buffers
1704 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1705 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1707 * Unmap a set of streaming mode DMA translations. Again, CPU access
1708 * rules concerning calls here are the same as for dma_unmap_single().
1710 void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1711 enum dma_data_direction dir, struct dma_attrs *attrs)
1713 __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
1717 * arm_iommu_sync_sg_for_cpu
1718 * @dev: valid struct device pointer
1719 * @sg: list of buffers
1720 * @nents: number of buffers to map (returned from dma_map_sg)
1721 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1723 void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1724 int nents, enum dma_data_direction dir)
1726 struct scatterlist *s;
1729 for_each_sg(sg, s, nents, i)
1730 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1735 * arm_iommu_sync_sg_for_device
1736 * @dev: valid struct device pointer
1737 * @sg: list of buffers
1738 * @nents: number of buffers to map (returned from dma_map_sg)
1739 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1741 void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1742 int nents, enum dma_data_direction dir)
1744 struct scatterlist *s;
1747 for_each_sg(sg, s, nents, i)
1748 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1753 * arm_coherent_iommu_map_page
1754 * @dev: valid struct device pointer
1755 * @page: page that buffer resides in
1756 * @offset: offset into page for start of buffer
1757 * @size: size of buffer to map
1758 * @dir: DMA transfer direction
1760 * Coherent IOMMU aware version of arm_dma_map_page()
1762 static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
1763 unsigned long offset, size_t size, enum dma_data_direction dir,
1764 struct dma_attrs *attrs)
1766 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1767 dma_addr_t dma_addr;
1768 int ret, prot, len = PAGE_ALIGN(size + offset);
1770 dma_addr = __alloc_iova(mapping, len);
1771 if (dma_addr == DMA_ERROR_CODE)
1774 prot = __dma_direction_to_prot(dir);
1776 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
1780 return dma_addr + offset;
1782 __free_iova(mapping, dma_addr, len);
1783 return DMA_ERROR_CODE;
1787 * arm_iommu_map_page
1788 * @dev: valid struct device pointer
1789 * @page: page that buffer resides in
1790 * @offset: offset into page for start of buffer
1791 * @size: size of buffer to map
1792 * @dir: DMA transfer direction
1794 * IOMMU aware version of arm_dma_map_page()
1796 static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1797 unsigned long offset, size_t size, enum dma_data_direction dir,
1798 struct dma_attrs *attrs)
1800 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1801 __dma_page_cpu_to_dev(page, offset, size, dir);
1803 return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
1807 * arm_coherent_iommu_unmap_page
1808 * @dev: valid struct device pointer
1809 * @handle: DMA address of buffer
1810 * @size: size of buffer (same as passed to dma_map_page)
1811 * @dir: DMA transfer direction (same as passed to dma_map_page)
1813 * Coherent IOMMU aware version of arm_dma_unmap_page()
1815 static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1816 size_t size, enum dma_data_direction dir,
1817 struct dma_attrs *attrs)
1819 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1820 dma_addr_t iova = handle & PAGE_MASK;
1821 int offset = handle & ~PAGE_MASK;
1822 int len = PAGE_ALIGN(size + offset);
1827 iommu_unmap(mapping->domain, iova, len);
1828 __free_iova(mapping, iova, len);
1832 * arm_iommu_unmap_page
1833 * @dev: valid struct device pointer
1834 * @handle: DMA address of buffer
1835 * @size: size of buffer (same as passed to dma_map_page)
1836 * @dir: DMA transfer direction (same as passed to dma_map_page)
1838 * IOMMU aware version of arm_dma_unmap_page()
1840 static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1841 size_t size, enum dma_data_direction dir,
1842 struct dma_attrs *attrs)
1844 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1845 dma_addr_t iova = handle & PAGE_MASK;
1846 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1847 int offset = handle & ~PAGE_MASK;
1848 int len = PAGE_ALIGN(size + offset);
1853 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1854 __dma_page_dev_to_cpu(page, offset, size, dir);
1856 iommu_unmap(mapping->domain, iova, len);
1857 __free_iova(mapping, iova, len);
1860 static void arm_iommu_sync_single_for_cpu(struct device *dev,
1861 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1863 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1864 dma_addr_t iova = handle & PAGE_MASK;
1865 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1866 unsigned int offset = handle & ~PAGE_MASK;
1871 __dma_page_dev_to_cpu(page, offset, size, dir);
1874 static void arm_iommu_sync_single_for_device(struct device *dev,
1875 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1877 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1878 dma_addr_t iova = handle & PAGE_MASK;
1879 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1880 unsigned int offset = handle & ~PAGE_MASK;
1885 __dma_page_cpu_to_dev(page, offset, size, dir);
1888 struct dma_map_ops iommu_ops = {
1889 .alloc = arm_iommu_alloc_attrs,
1890 .free = arm_iommu_free_attrs,
1891 .mmap = arm_iommu_mmap_attrs,
1892 .get_sgtable = arm_iommu_get_sgtable,
1894 .map_page = arm_iommu_map_page,
1895 .unmap_page = arm_iommu_unmap_page,
1896 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
1897 .sync_single_for_device = arm_iommu_sync_single_for_device,
1899 .map_sg = arm_iommu_map_sg,
1900 .unmap_sg = arm_iommu_unmap_sg,
1901 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
1902 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
1904 .set_dma_mask = arm_dma_set_mask,
1907 struct dma_map_ops iommu_coherent_ops = {
1908 .alloc = arm_iommu_alloc_attrs,
1909 .free = arm_iommu_free_attrs,
1910 .mmap = arm_iommu_mmap_attrs,
1911 .get_sgtable = arm_iommu_get_sgtable,
1913 .map_page = arm_coherent_iommu_map_page,
1914 .unmap_page = arm_coherent_iommu_unmap_page,
1916 .map_sg = arm_coherent_iommu_map_sg,
1917 .unmap_sg = arm_coherent_iommu_unmap_sg,
1919 .set_dma_mask = arm_dma_set_mask,
1923 * arm_iommu_create_mapping
1924 * @bus: pointer to the bus holding the client device (for IOMMU calls)
1925 * @base: start address of the valid IO address space
1926 * @size: maximum size of the valid IO address space
1928 * Creates a mapping structure which holds information about used/unused
1929 * IO address ranges, which is required to perform memory allocation and
1930 * mapping with IOMMU aware functions.
1932 * The client device need to be attached to the mapping with
1933 * arm_iommu_attach_device function.
1935 struct dma_iommu_mapping *
1936 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size)
1938 unsigned int bits = size >> PAGE_SHIFT;
1939 unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long);
1940 struct dma_iommu_mapping *mapping;
1945 return ERR_PTR(-EINVAL);
1947 if (bitmap_size > PAGE_SIZE) {
1948 extensions = bitmap_size / PAGE_SIZE;
1949 bitmap_size = PAGE_SIZE;
1952 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
1956 mapping->bitmap_size = bitmap_size;
1957 mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *),
1959 if (!mapping->bitmaps)
1962 mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL);
1963 if (!mapping->bitmaps[0])
1966 mapping->nr_bitmaps = 1;
1967 mapping->extensions = extensions;
1968 mapping->base = base;
1969 mapping->bits = BITS_PER_BYTE * bitmap_size;
1971 spin_lock_init(&mapping->lock);
1973 mapping->domain = iommu_domain_alloc(bus);
1974 if (!mapping->domain)
1977 kref_init(&mapping->kref);
1980 kfree(mapping->bitmaps[0]);
1982 kfree(mapping->bitmaps);
1986 return ERR_PTR(err);
1988 EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
1990 static void release_iommu_mapping(struct kref *kref)
1993 struct dma_iommu_mapping *mapping =
1994 container_of(kref, struct dma_iommu_mapping, kref);
1996 iommu_domain_free(mapping->domain);
1997 for (i = 0; i < mapping->nr_bitmaps; i++)
1998 kfree(mapping->bitmaps[i]);
1999 kfree(mapping->bitmaps);
2003 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping)
2007 if (mapping->nr_bitmaps > mapping->extensions)
2010 next_bitmap = mapping->nr_bitmaps;
2011 mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size,
2013 if (!mapping->bitmaps[next_bitmap])
2016 mapping->nr_bitmaps++;
2021 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
2024 kref_put(&mapping->kref, release_iommu_mapping);
2026 EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
2029 * arm_iommu_attach_device
2030 * @dev: valid struct device pointer
2031 * @mapping: io address space mapping structure (returned from
2032 * arm_iommu_create_mapping)
2034 * Attaches specified io address space mapping to the provided device,
2035 * this replaces the dma operations (dma_map_ops pointer) with the
2036 * IOMMU aware version. More than one client might be attached to
2037 * the same io address space mapping.
2039 int arm_iommu_attach_device(struct device *dev,
2040 struct dma_iommu_mapping *mapping)
2044 err = iommu_attach_device(mapping->domain, dev);
2048 kref_get(&mapping->kref);
2049 dev->archdata.mapping = mapping;
2050 set_dma_ops(dev, &iommu_ops);
2052 pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
2055 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
2058 * arm_iommu_detach_device
2059 * @dev: valid struct device pointer
2061 * Detaches the provided device from a previously attached map.
2062 * This voids the dma operations (dma_map_ops pointer)
2064 void arm_iommu_detach_device(struct device *dev)
2066 struct dma_iommu_mapping *mapping;
2068 mapping = to_dma_iommu_mapping(dev);
2070 dev_warn(dev, "Not attached\n");
2074 iommu_detach_device(mapping->domain, dev);
2075 kref_put(&mapping->kref, release_iommu_mapping);
2076 dev->archdata.mapping = NULL;
2077 set_dma_ops(dev, NULL);
2079 pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
2081 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);