arch/arm/mm/mm-armv.c

   1 /*
   2  *  linux/arch/arm/mm/mm-armv.c
   3  *
   4  *  Copyright (C) 1998-2002 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  Page table sludge for ARM v3 and v4 processor architectures.
  11  */
  12 #include <linux/config.h>
  13 #include <linux/module.h>
  14 #include <linux/mm.h>
  15 #include <linux/init.h>
  16 #include <linux/bootmem.h>
  17 #include <linux/highmem.h>
  18 #include <linux/nodemask.h>
  19
  20 #include <asm/pgalloc.h>
  21 #include <asm/page.h>
  22 #include <asm/io.h>
  23 #include <asm/setup.h>
  24 #include <asm/tlbflush.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #define CPOLICY_UNCACHED        0
  29 #define CPOLICY_BUFFERED        1
  30 #define CPOLICY_WRITETHROUGH    2
  31 #define CPOLICY_WRITEBACK       3
  32 #define CPOLICY_WRITEALLOC      4
  33
  34 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  35 static unsigned int ecc_mask __initdata = 0;
  36 pgprot_t pgprot_kernel;
  37
  38 EXPORT_SYMBOL(pgprot_kernel);
  39
  40 struct cachepolicy {
  41         const char      policy[16];
  42         unsigned int    cr_mask;
  43         unsigned int    pmd;
  44         unsigned int    pte;
  45 };
  46
  47 static struct cachepolicy cache_policies[] __initdata = {
  48         {
  49                 .policy         = "uncached",
  50                 .cr_mask        = CR_W|CR_C,
  51                 .pmd            = PMD_SECT_UNCACHED,
  52                 .pte            = 0,
  53         }, {
  54                 .policy         = "buffered",
  55                 .cr_mask        = CR_C,
  56                 .pmd            = PMD_SECT_BUFFERED,
  57                 .pte            = PTE_BUFFERABLE,
  58         }, {
  59                 .policy         = "writethrough",
  60                 .cr_mask        = 0,
  61                 .pmd            = PMD_SECT_WT,
  62                 .pte            = PTE_CACHEABLE,
  63         }, {
  64                 .policy         = "writeback",
  65                 .cr_mask        = 0,
  66                 .pmd            = PMD_SECT_WB,
  67                 .pte            = PTE_BUFFERABLE|PTE_CACHEABLE,
  68         }, {
  69                 .policy         = "writealloc",
  70                 .cr_mask        = 0,
  71                 .pmd            = PMD_SECT_WBWA,
  72                 .pte            = PTE_BUFFERABLE|PTE_CACHEABLE,
  73         }
  74 };
  75
  76 /*
  77  * These are useful for identifing cache coherency
  78  * problems by allowing the cache or the cache and
  79  * writebuffer to be turned off.  (Note: the write
  80  * buffer should not be on and the cache off).
  81  */
  82 static void __init early_cachepolicy(char **p)
  83 {
  84         int i;
  85
  86         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
  87                 int len = strlen(cache_policies[i].policy);
  88
  89                 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
  90                         cachepolicy = i;
  91                         cr_alignment &= ~cache_policies[i].cr_mask;
  92                         cr_no_alignment &= ~cache_policies[i].cr_mask;
  93                         *p += len;
  94                         break;
  95                 }
  96         }
  97         if (i == ARRAY_SIZE(cache_policies))
  98                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
  99         flush_cache_all();
 100         set_cr(cr_alignment);
 101 }
 102
 103 static void __init early_nocache(char **__unused)
 104 {
 105         char *p = "buffered";
 106         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 107         early_cachepolicy(&p);
 108 }
 109
 110 static void __init early_nowrite(char **__unused)
 111 {
 112         char *p = "uncached";
 113         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 114         early_cachepolicy(&p);
 115 }
 116
 117 static void __init early_ecc(char **p)
 118 {
 119         if (memcmp(*p, "on", 2) == 0) {
 120                 ecc_mask = PMD_PROTECTION;
 121                 *p += 2;
 122         } else if (memcmp(*p, "off", 3) == 0) {
 123                 ecc_mask = 0;
 124                 *p += 3;
 125         }
 126 }
 127
 128 __early_param("nocache", early_nocache);
 129 __early_param("nowb", early_nowrite);
 130 __early_param("cachepolicy=", early_cachepolicy);
 131 __early_param("ecc=", early_ecc);
 132
 133 static int __init noalign_setup(char *__unused)
 134 {
 135         cr_alignment &= ~CR_A;
 136         cr_no_alignment &= ~CR_A;
 137         set_cr(cr_alignment);
 138         return 1;
 139 }
 140
 141 __setup("noalign", noalign_setup);
 142
 143 #define FIRST_KERNEL_PGD_NR     (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD)
 144
 145 static inline pmd_t *pmd_off(pgd_t *pgd, unsigned long virt)
 146 {
 147         return pmd_offset(pgd, virt);
 148 }
 149
 150 static inline pmd_t *pmd_off_k(unsigned long virt)
 151 {
 152         return pmd_off(pgd_offset_k(virt), virt);
 153 }
 154
 155 /*
 156  * need to get a 16k page for level 1
 157  */
 158 pgd_t *get_pgd_slow(struct mm_struct *mm)
 159 {
 160         pgd_t *new_pgd, *init_pgd;
 161         pmd_t *new_pmd, *init_pmd;
 162         pte_t *new_pte, *init_pte;
 163
 164         new_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, 2);
 165         if (!new_pgd)
 166                 goto no_pgd;
 167
 168         memzero(new_pgd, FIRST_KERNEL_PGD_NR * sizeof(pgd_t));
 169
 170         init_pgd = pgd_offset_k(0);
 171
 172         if (!vectors_high()) {
 173                 /*
 174                  * This lock is here just to satisfy pmd_alloc and pte_lock
 175                  */
 176                 spin_lock(&mm->page_table_lock);
 177
 178                 /*
 179                  * On ARM, first page must always be allocated since it
 180                  * contains the machine vectors.
 181                  */
 182                 new_pmd = pmd_alloc(mm, new_pgd, 0);
 183                 if (!new_pmd)
 184                         goto no_pmd;
 185
 186                 new_pte = pte_alloc_map(mm, new_pmd, 0);
 187                 if (!new_pte)
 188                         goto no_pte;
 189
 190                 init_pmd = pmd_offset(init_pgd, 0);
 191                 init_pte = pte_offset_map_nested(init_pmd, 0);
 192                 set_pte(new_pte, *init_pte);
 193                 pte_unmap_nested(init_pte);
 194                 pte_unmap(new_pte);
 195
 196                 spin_unlock(&mm->page_table_lock);
 197         }
 198
 199         /*
 200          * Copy over the kernel and IO PGD entries
 201          */
 202         memcpy(new_pgd + FIRST_KERNEL_PGD_NR, init_pgd + FIRST_KERNEL_PGD_NR,
 203                        (PTRS_PER_PGD - FIRST_KERNEL_PGD_NR) * sizeof(pgd_t));
 204
 205         clean_dcache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t));
 206
 207         return new_pgd;
 208
 209 no_pte:
 210         spin_unlock(&mm->page_table_lock);
 211         pmd_free(new_pmd);
 212         free_pages((unsigned long)new_pgd, 2);
 213         return NULL;
 214
 215 no_pmd:
 216         spin_unlock(&mm->page_table_lock);
 217         free_pages((unsigned long)new_pgd, 2);
 218         return NULL;
 219
 220 no_pgd:
 221         return NULL;
 222 }
 223
 224 void free_pgd_slow(pgd_t *pgd)
 225 {
 226         pmd_t *pmd;
 227         struct page *pte;
 228
 229         if (!pgd)
 230                 return;
 231
 232         /* pgd is always present and good */
 233         pmd = pmd_off(pgd, 0);
 234         if (pmd_none(*pmd))
 235                 goto free;
 236         if (pmd_bad(*pmd)) {
 237                 pmd_ERROR(*pmd);
 238                 pmd_clear(pmd);
 239                 goto free;
 240         }
 241
 242         pte = pmd_page(*pmd);
 243         pmd_clear(pmd);
 244         dec_page_state(nr_page_table_pages);
 245         pte_free(pte);
 246         pmd_free(pmd);
 247 free:
 248         free_pages((unsigned long) pgd, 2);
 249 }
 250
 251 /*
 252  * Create a SECTION PGD between VIRT and PHYS in domain
 253  * DOMAIN with protection PROT.  This operates on half-
 254  * pgdir entry increments.
 255  */
 256 static inline void
 257 alloc_init_section(unsigned long virt, unsigned long phys, int prot)
 258 {
 259         pmd_t *pmdp = pmd_off_k(virt);
 260
 261         if (virt & (1 << 20))
 262                 pmdp++;
 263
 264         *pmdp = __pmd(phys | prot);
 265         flush_pmd_entry(pmdp);
 266 }
 267
 268 /*
 269  * Create a SUPER SECTION PGD between VIRT and PHYS with protection PROT
 270  */
 271 static inline void
 272 alloc_init_supersection(unsigned long virt, unsigned long phys, int prot)
 273 {
 274         int i;
 275
 276         for (i = 0; i < 16; i += 1) {
 277                 alloc_init_section(virt, phys & SUPERSECTION_MASK,
 278                                    prot | PMD_SECT_SUPER);
 279
 280                 virt += (PGDIR_SIZE / 2);
 281                 phys += (PGDIR_SIZE / 2);
 282         }
 283 }
 284
 285 /*
 286  * Add a PAGE mapping between VIRT and PHYS in domain
 287  * DOMAIN with protection PROT.  Note that due to the
 288  * way we map the PTEs, we must allocate two PTE_SIZE'd
 289  * blocks - one for the Linux pte table, and one for
 290  * the hardware pte table.
 291  */
 292 static inline void
 293 alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pgprot_t prot)
 294 {
 295         pmd_t *pmdp = pmd_off_k(virt);
 296         pte_t *ptep;
 297
 298         if (pmd_none(*pmdp)) {
 299                 unsigned long pmdval;
 300                 ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
 301                                                sizeof(pte_t));
 302
 303                 pmdval = __pa(ptep) | prot_l1;
 304                 pmdp[0] = __pmd(pmdval);
 305                 pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
 306                 flush_pmd_entry(pmdp);
 307         }
 308         ptep = pte_offset_kernel(pmdp, virt);
 309
 310         set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
 311 }
 312
 313 /*
 314  * Clear any PGD mapping.  On a two-level page table system,
 315  * the clearance is done by the middle-level functions (pmd)
 316  * rather than the top-level (pgd) functions.
 317  */
 318 static inline void clear_mapping(unsigned long virt)
 319 {
 320         pmd_clear(pmd_off_k(virt));
 321 }
 322
 323 struct mem_types {
 324         unsigned int    prot_pte;
 325         unsigned int    prot_l1;
 326         unsigned int    prot_sect;
 327         unsigned int    domain;
 328 };
 329
 330 static struct mem_types mem_types[] __initdata = {
 331         [MT_DEVICE] = {
 332                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 333                                 L_PTE_WRITE,
 334                 .prot_l1   = PMD_TYPE_TABLE,
 335                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED |
 336                                 PMD_SECT_AP_WRITE,
 337                 .domain    = DOMAIN_IO,
 338         },
 339         [MT_CACHECLEAN] = {
 340                 .prot_sect = PMD_TYPE_SECT,
 341                 .domain    = DOMAIN_KERNEL,
 342         },
 343         [MT_MINICLEAN] = {
 344                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_MINICACHE,
 345                 .domain    = DOMAIN_KERNEL,
 346         },
 347         [MT_LOW_VECTORS] = {
 348                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 349                                 L_PTE_EXEC,
 350                 .prot_l1   = PMD_TYPE_TABLE,
 351                 .domain    = DOMAIN_USER,
 352         },
 353         [MT_HIGH_VECTORS] = {
 354                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 355                                 L_PTE_USER | L_PTE_EXEC,
 356                 .prot_l1   = PMD_TYPE_TABLE,
 357                 .domain    = DOMAIN_USER,
 358         },
 359         [MT_MEMORY] = {
 360                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 361                 .domain    = DOMAIN_KERNEL,
 362         },
 363         [MT_ROM] = {
 364                 .prot_sect = PMD_TYPE_SECT,
 365                 .domain    = DOMAIN_KERNEL,
 366         },
 367         [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
 368                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 369                                 L_PTE_WRITE,
 370                 .prot_l1   = PMD_TYPE_TABLE,
 371                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED |
 372                                 PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
 373                                 PMD_SECT_TEX(1),
 374                 .domain    = DOMAIN_IO,
 375         }
 376 };
 377
 378 /*
 379  * Adjust the PMD section entries according to the CPU in use.
 380  */
 381 static void __init build_mem_type_table(void)
 382 {
 383         struct cachepolicy *cp;
 384         unsigned int cr = get_cr();
 385         int cpu_arch = cpu_architecture();
 386         int i;
 387
 388 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 389         if (cachepolicy > CPOLICY_BUFFERED)
 390                 cachepolicy = CPOLICY_BUFFERED;
 391 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 392         if (cachepolicy > CPOLICY_WRITETHROUGH)
 393                 cachepolicy = CPOLICY_WRITETHROUGH;
 394 #endif
 395         if (cpu_arch < CPU_ARCH_ARMv5) {
 396                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 397                         cachepolicy = CPOLICY_WRITEBACK;
 398                 ecc_mask = 0;
 399         }
 400
 401         if (cpu_arch <= CPU_ARCH_ARMv5) {
 402                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 403                         if (mem_types[i].prot_l1)
 404                                 mem_types[i].prot_l1 |= PMD_BIT4;
 405                         if (mem_types[i].prot_sect)
 406                                 mem_types[i].prot_sect |= PMD_BIT4;
 407                 }
 408         }
 409
 410         /*
 411          * ARMv6 and above have extended page tables.
 412          */
 413         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 414                 /*
 415                  * bit 4 becomes XN which we must clear for the
 416                  * kernel memory mapping.
 417                  */
 418                 mem_types[MT_MEMORY].prot_sect &= ~PMD_BIT4;
 419                 mem_types[MT_ROM].prot_sect &= ~PMD_BIT4;
 420                 /*
 421                  * Mark cache clean areas and XIP ROM read only
 422                  * from SVC mode and no access from userspace.
 423                  */
 424                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 425                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 426                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 427         }
 428
 429         cp = &cache_policies[cachepolicy];
 430
 431         if (cpu_arch >= CPU_ARCH_ARMv5) {
 432                 mem_types[MT_LOW_VECTORS].prot_pte |= cp->pte & PTE_CACHEABLE;
 433                 mem_types[MT_HIGH_VECTORS].prot_pte |= cp->pte & PTE_CACHEABLE;
 434         } else {
 435                 mem_types[MT_LOW_VECTORS].prot_pte |= cp->pte;
 436                 mem_types[MT_HIGH_VECTORS].prot_pte |= cp->pte;
 437                 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
 438         }
 439
 440         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 441         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 442         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 443         mem_types[MT_ROM].prot_sect |= cp->pmd;
 444
 445         for (i = 0; i < 16; i++) {
 446                 unsigned long v = pgprot_val(protection_map[i]);
 447                 v &= (~(PTE_BUFFERABLE|PTE_CACHEABLE)) | cp->pte;
 448                 protection_map[i] = __pgprot(v);
 449         }
 450
 451         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 452                                  L_PTE_DIRTY | L_PTE_WRITE |
 453                                  L_PTE_EXEC | cp->pte);
 454
 455         switch (cp->pmd) {
 456         case PMD_SECT_WT:
 457                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 458                 break;
 459         case PMD_SECT_WB:
 460         case PMD_SECT_WBWA:
 461                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 462                 break;
 463         }
 464         printk("Memory policy: ECC %sabled, Data cache %s\n",
 465                 ecc_mask ? "en" : "dis", cp->policy);
 466 }
 467
 468 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 469
 470 /*
 471  * Create the page directory entries and any necessary
 472  * page tables for the mapping specified by `md'.  We
 473  * are able to cope here with varying sizes and address
 474  * offsets, and we take full advantage of sections and
 475  * supersections.
 476  */
 477 static void __init create_mapping(struct map_desc *md)
 478 {
 479         unsigned long virt, length;
 480         int prot_sect, prot_l1, domain;
 481         pgprot_t prot_pte;
 482         long off;
 483
 484         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 485                 printk(KERN_WARNING "BUG: not creating mapping for "
 486                        "0x%08lx at 0x%08lx in user region\n",
 487                        md->physical, md->virtual);
 488                 return;
 489         }
 490
 491         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 492             md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
 493                 printk(KERN_WARNING "BUG: mapping for 0x%08lx at 0x%08lx "
 494                        "overlaps vmalloc space\n",
 495                        md->physical, md->virtual);
 496         }
 497
 498         domain    = mem_types[md->type].domain;
 499         prot_pte  = __pgprot(mem_types[md->type].prot_pte);
 500         prot_l1   = mem_types[md->type].prot_l1 | PMD_DOMAIN(domain);
 501         prot_sect = mem_types[md->type].prot_sect | PMD_DOMAIN(domain);
 502
 503         virt   = md->virtual;
 504         off    = md->physical - virt;
 505         length = md->length;
 506
 507         if (mem_types[md->type].prot_l1 == 0 &&
 508             (virt & 0xfffff || (virt + off) & 0xfffff || (virt + length) & 0xfffff)) {
 509                 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
 510                        "be mapped using pages, ignoring.\n",
 511                        md->physical, md->virtual);
 512                 return;
 513         }
 514
 515         while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) {
 516                 alloc_init_page(virt, virt + off, prot_l1, prot_pte);
 517
 518                 virt   += PAGE_SIZE;
 519                 length -= PAGE_SIZE;
 520         }
 521
 522         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 523          *      Since domain assignments can in fact be arbitrary, the
 524          *      'domain == 0' check below is required to insure that ARMv6
 525          *      supersections are only allocated for domain 0 regardless
 526          *      of the actual domain assignments in use.
 527          */
 528         if (cpu_architecture() >= CPU_ARCH_ARMv6 && domain == 0) {
 529                 /* Align to supersection boundary */
 530                 while ((virt & ~SUPERSECTION_MASK || (virt + off) &
 531                         ~SUPERSECTION_MASK) && length >= (PGDIR_SIZE / 2)) {
 532                         alloc_init_section(virt, virt + off, prot_sect);
 533
 534                         virt   += (PGDIR_SIZE / 2);
 535                         length -= (PGDIR_SIZE / 2);
 536                 }
 537
 538                 while (length >= SUPERSECTION_SIZE) {
 539                         alloc_init_supersection(virt, virt + off, prot_sect);
 540
 541                         virt   += SUPERSECTION_SIZE;
 542                         length -= SUPERSECTION_SIZE;
 543                 }
 544         }
 545
 546         /*
 547          * A section mapping covers half a "pgdir" entry.
 548          */
 549         while (length >= (PGDIR_SIZE / 2)) {
 550                 alloc_init_section(virt, virt + off, prot_sect);
 551
 552                 virt   += (PGDIR_SIZE / 2);
 553                 length -= (PGDIR_SIZE / 2);
 554         }
 555
 556         while (length >= PAGE_SIZE) {
 557                 alloc_init_page(virt, virt + off, prot_l1, prot_pte);
 558
 559                 virt   += PAGE_SIZE;
 560                 length -= PAGE_SIZE;
 561         }
 562 }
 563
 564 /*
 565  * In order to soft-boot, we need to insert a 1:1 mapping in place of
 566  * the user-mode pages.  This will then ensure that we have predictable
 567  * results when turning the mmu off
 568  */
 569 void setup_mm_for_reboot(char mode)
 570 {
 571         unsigned long pmdval;
 572         pgd_t *pgd;
 573         pmd_t *pmd;
 574         int i;
 575         int cpu_arch = cpu_architecture();
 576
 577         if (current->mm && current->mm->pgd)
 578                 pgd = current->mm->pgd;
 579         else
 580                 pgd = init_mm.pgd;
 581
 582         for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++) {
 583                 pmdval = (i << PGDIR_SHIFT) |
 584                          PMD_SECT_AP_WRITE | PMD_SECT_AP_READ |
 585                          PMD_TYPE_SECT;
 586                 if (cpu_arch <= CPU_ARCH_ARMv5)
 587                         pmdval |= PMD_BIT4;
 588                 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
 589                 pmd[0] = __pmd(pmdval);
 590                 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
 591                 flush_pmd_entry(pmd);
 592         }
 593 }
 594
 595 extern void _stext, _etext;
 596
 597 /*
 598  * Setup initial mappings.  We use the page we allocated for zero page to hold
 599  * the mappings, which will get overwritten by the vectors in traps_init().
 600  * The mappings must be in virtual address order.
 601  */
 602 void __init memtable_init(struct meminfo *mi)
 603 {
 604         struct map_desc *init_maps, *p, *q;
 605         unsigned long address = 0;
 606         int i;
 607
 608         build_mem_type_table();
 609
 610         init_maps = p = alloc_bootmem_low_pages(PAGE_SIZE);
 611
 612 #ifdef CONFIG_XIP_KERNEL
 613         p->physical   = CONFIG_XIP_PHYS_ADDR & PMD_MASK;
 614         p->virtual    = (unsigned long)&_stext & PMD_MASK;
 615         p->length     = ((unsigned long)&_etext - p->virtual + ~PMD_MASK) & PMD_MASK;
 616         p->type       = MT_ROM;
 617         p ++;
 618 #endif
 619
 620         for (i = 0; i < mi->nr_banks; i++) {
 621                 if (mi->bank[i].size == 0)
 622                         continue;
 623
 624                 p->physical   = mi->bank[i].start;
 625                 p->virtual    = __phys_to_virt(p->physical);
 626                 p->length     = mi->bank[i].size;
 627                 p->type       = MT_MEMORY;
 628                 p ++;
 629         }
 630
 631 #ifdef FLUSH_BASE
 632         p->physical   = FLUSH_BASE_PHYS;
 633         p->virtual    = FLUSH_BASE;
 634         p->length     = PGDIR_SIZE;
 635         p->type       = MT_CACHECLEAN;
 636         p ++;
 637 #endif
 638
 639 #ifdef FLUSH_BASE_MINICACHE
 640         p->physical   = FLUSH_BASE_PHYS + PGDIR_SIZE;
 641         p->virtual    = FLUSH_BASE_MINICACHE;
 642         p->length     = PGDIR_SIZE;
 643         p->type       = MT_MINICLEAN;
 644         p ++;
 645 #endif
 646
 647         /*
 648          * Go through the initial mappings, but clear out any
 649          * pgdir entries that are not in the description.
 650          */
 651         q = init_maps;
 652         do {
 653                 if (address < q->virtual || q == p) {
 654                         clear_mapping(address);
 655                         address += PGDIR_SIZE;
 656                 } else {
 657                         create_mapping(q);
 658
 659                         address = q->virtual + q->length;
 660                         address = (address + PGDIR_SIZE - 1) & PGDIR_MASK;
 661
 662                         q ++;
 663                 }
 664         } while (address != 0);
 665
 666         /*
 667          * Create a mapping for the machine vectors at the high-vectors
 668          * location (0xffff0000).  If we aren't using high-vectors, also
 669          * create a mapping at the low-vectors virtual address.
 670          */
 671         init_maps->physical   = virt_to_phys(init_maps);
 672         init_maps->virtual    = 0xffff0000;
 673         init_maps->length     = PAGE_SIZE;
 674         init_maps->type       = MT_HIGH_VECTORS;
 675         create_mapping(init_maps);
 676
 677         if (!vectors_high()) {
 678                 init_maps->virtual = 0;
 679                 init_maps->type = MT_LOW_VECTORS;
 680                 create_mapping(init_maps);
 681         }
 682
 683         flush_cache_all();
 684         flush_tlb_all();
 685 }
 686
 687 /*
 688  * Create the architecture specific mappings
 689  */
 690 void __init iotable_init(struct map_desc *io_desc, int nr)
 691 {
 692         int i;
 693
 694         for (i = 0; i < nr; i++)
 695                 create_mapping(io_desc + i);
 696 }
 697
 698 static inline void
 699 free_memmap(int node, unsigned long start_pfn, unsigned long end_pfn)
 700 {
 701         struct page *start_pg, *end_pg;
 702         unsigned long pg, pgend;
 703
 704         /*
 705          * Convert start_pfn/end_pfn to a struct page pointer.
 706          */
 707         start_pg = pfn_to_page(start_pfn);
 708         end_pg = pfn_to_page(end_pfn);
 709
 710         /*
 711          * Convert to physical addresses, and
 712          * round start upwards and end downwards.
 713          */
 714         pg = PAGE_ALIGN(__pa(start_pg));
 715         pgend = __pa(end_pg) & PAGE_MASK;
 716
 717         /*
 718          * If there are free pages between these,
 719          * free the section of the memmap array.
 720          */
 721         if (pg < pgend)
 722                 free_bootmem_node(NODE_DATA(node), pg, pgend - pg);
 723 }
 724
 725 static inline void free_unused_memmap_node(int node, struct meminfo *mi)
 726 {
 727         unsigned long bank_start, prev_bank_end = 0;
 728         unsigned int i;
 729
 730         /*
 731          * [FIXME] This relies on each bank being in address order.  This
 732          * may not be the case, especially if the user has provided the
 733          * information on the command line.
 734          */
 735         for (i = 0; i < mi->nr_banks; i++) {
 736                 if (mi->bank[i].size == 0 || mi->bank[i].node != node)
 737                         continue;
 738
 739                 bank_start = mi->bank[i].start >> PAGE_SHIFT;
 740                 if (bank_start < prev_bank_end) {
 741                         printk(KERN_ERR "MEM: unordered memory banks.  "
 742                                 "Not freeing memmap.\n");
 743                         break;
 744                 }
 745
 746                 /*
 747                  * If we had a previous bank, and there is a space
 748                  * between the current bank and the previous, free it.
 749                  */
 750                 if (prev_bank_end && prev_bank_end != bank_start)
 751                         free_memmap(node, prev_bank_end, bank_start);
 752
 753                 prev_bank_end = PAGE_ALIGN(mi->bank[i].start +
 754                                            mi->bank[i].size) >> PAGE_SHIFT;
 755         }
 756 }
 757
 758 /*
 759  * The mem_map array can get very big.  Free
 760  * the unused area of the memory map.
 761  */
 762 void __init create_memmap_holes(struct meminfo *mi)
 763 {
 764         int node;
 765
 766         for_each_online_node(node)
 767                 free_unused_memmap_node(node, mi);
 768 }