2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
19 #include <asm/cputype.h>
20 #include <asm/sections.h>
21 #include <asm/cachetype.h>
22 #include <asm/setup.h>
23 #include <asm/sizes.h>
24 #include <asm/smp_plat.h>
26 #include <asm/highmem.h>
27 #include <asm/traps.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/map.h>
35 * empty_zero_page is a special page that is used for
36 * zero-initialized data and COW.
38 struct page *empty_zero_page;
39 EXPORT_SYMBOL(empty_zero_page);
42 * The pmd table for the upper-most set of pages.
46 #define CPOLICY_UNCACHED 0
47 #define CPOLICY_BUFFERED 1
48 #define CPOLICY_WRITETHROUGH 2
49 #define CPOLICY_WRITEBACK 3
50 #define CPOLICY_WRITEALLOC 4
52 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
53 static unsigned int ecc_mask __initdata = 0;
55 pgprot_t pgprot_kernel;
57 EXPORT_SYMBOL(pgprot_user);
58 EXPORT_SYMBOL(pgprot_kernel);
61 const char policy[16];
67 static struct cachepolicy cache_policies[] __initdata = {
71 .pmd = PMD_SECT_UNCACHED,
72 .pte = L_PTE_MT_UNCACHED,
76 .pmd = PMD_SECT_BUFFERED,
77 .pte = L_PTE_MT_BUFFERABLE,
79 .policy = "writethrough",
82 .pte = L_PTE_MT_WRITETHROUGH,
84 .policy = "writeback",
87 .pte = L_PTE_MT_WRITEBACK,
89 .policy = "writealloc",
92 .pte = L_PTE_MT_WRITEALLOC,
97 * These are useful for identifying cache coherency
98 * problems by allowing the cache or the cache and
99 * writebuffer to be turned off. (Note: the write
100 * buffer should not be on and the cache off).
102 static int __init early_cachepolicy(char *p)
106 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
107 int len = strlen(cache_policies[i].policy);
109 if (memcmp(p, cache_policies[i].policy, len) == 0) {
111 cr_alignment &= ~cache_policies[i].cr_mask;
112 cr_no_alignment &= ~cache_policies[i].cr_mask;
116 if (i == ARRAY_SIZE(cache_policies))
117 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
119 * This restriction is partly to do with the way we boot; it is
120 * unpredictable to have memory mapped using two different sets of
121 * memory attributes (shared, type, and cache attribs). We can not
122 * change these attributes once the initial assembly has setup the
125 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
126 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
127 cachepolicy = CPOLICY_WRITEBACK;
130 set_cr(cr_alignment);
133 early_param("cachepolicy", early_cachepolicy);
135 static int __init early_nocache(char *__unused)
137 char *p = "buffered";
138 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
139 early_cachepolicy(p);
142 early_param("nocache", early_nocache);
144 static int __init early_nowrite(char *__unused)
146 char *p = "uncached";
147 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
148 early_cachepolicy(p);
151 early_param("nowb", early_nowrite);
153 static int __init early_ecc(char *p)
155 if (memcmp(p, "on", 2) == 0)
156 ecc_mask = PMD_PROTECTION;
157 else if (memcmp(p, "off", 3) == 0)
161 early_param("ecc", early_ecc);
163 static int __init noalign_setup(char *__unused)
165 cr_alignment &= ~CR_A;
166 cr_no_alignment &= ~CR_A;
167 set_cr(cr_alignment);
170 __setup("noalign", noalign_setup);
173 void adjust_cr(unsigned long mask, unsigned long set)
181 local_irq_save(flags);
183 cr_no_alignment = (cr_no_alignment & ~mask) | set;
184 cr_alignment = (cr_alignment & ~mask) | set;
186 set_cr((get_cr() & ~mask) | set);
188 local_irq_restore(flags);
192 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
193 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
195 static struct mem_type mem_types[] = {
196 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
197 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
199 .prot_l1 = PMD_TYPE_TABLE,
200 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
203 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
204 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
205 .prot_l1 = PMD_TYPE_TABLE,
206 .prot_sect = PROT_SECT_DEVICE,
209 [MT_DEVICE_CACHED] = { /* ioremap_cached */
210 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
211 .prot_l1 = PMD_TYPE_TABLE,
212 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
215 [MT_DEVICE_WC] = { /* ioremap_wc */
216 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
217 .prot_l1 = PMD_TYPE_TABLE,
218 .prot_sect = PROT_SECT_DEVICE,
222 .prot_pte = PROT_PTE_DEVICE,
223 .prot_l1 = PMD_TYPE_TABLE,
224 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
228 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
229 .domain = DOMAIN_KERNEL,
232 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
233 .domain = DOMAIN_KERNEL,
236 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
238 .prot_l1 = PMD_TYPE_TABLE,
239 .domain = DOMAIN_USER,
241 [MT_HIGH_VECTORS] = {
242 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
243 L_PTE_USER | L_PTE_RDONLY,
244 .prot_l1 = PMD_TYPE_TABLE,
245 .domain = DOMAIN_USER,
248 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
249 .prot_l1 = PMD_TYPE_TABLE,
250 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
251 .domain = DOMAIN_KERNEL,
254 .prot_sect = PMD_TYPE_SECT,
255 .domain = DOMAIN_KERNEL,
257 [MT_MEMORY_NONCACHED] = {
258 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
260 .prot_l1 = PMD_TYPE_TABLE,
261 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
262 .domain = DOMAIN_KERNEL,
265 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
267 .prot_l1 = PMD_TYPE_TABLE,
268 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
269 .domain = DOMAIN_KERNEL,
272 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
273 .prot_l1 = PMD_TYPE_TABLE,
274 .domain = DOMAIN_KERNEL,
277 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
279 .prot_l1 = PMD_TYPE_TABLE,
280 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
281 PMD_SECT_UNCACHED | PMD_SECT_XN,
282 .domain = DOMAIN_KERNEL,
286 const struct mem_type *get_mem_type(unsigned int type)
288 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
290 EXPORT_SYMBOL(get_mem_type);
293 * Adjust the PMD section entries according to the CPU in use.
295 static void __init build_mem_type_table(void)
297 struct cachepolicy *cp;
298 unsigned int cr = get_cr();
299 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
300 int cpu_arch = cpu_architecture();
303 if (cpu_arch < CPU_ARCH_ARMv6) {
304 #if defined(CONFIG_CPU_DCACHE_DISABLE)
305 if (cachepolicy > CPOLICY_BUFFERED)
306 cachepolicy = CPOLICY_BUFFERED;
307 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
308 if (cachepolicy > CPOLICY_WRITETHROUGH)
309 cachepolicy = CPOLICY_WRITETHROUGH;
312 if (cpu_arch < CPU_ARCH_ARMv5) {
313 if (cachepolicy >= CPOLICY_WRITEALLOC)
314 cachepolicy = CPOLICY_WRITEBACK;
318 cachepolicy = CPOLICY_WRITEALLOC;
321 * Strip out features not present on earlier architectures.
322 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
323 * without extended page tables don't have the 'Shared' bit.
325 if (cpu_arch < CPU_ARCH_ARMv5)
326 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
327 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
328 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
329 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
330 mem_types[i].prot_sect &= ~PMD_SECT_S;
333 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
334 * "update-able on write" bit on ARM610). However, Xscale and
335 * Xscale3 require this bit to be cleared.
337 if (cpu_is_xscale() || cpu_is_xsc3()) {
338 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
339 mem_types[i].prot_sect &= ~PMD_BIT4;
340 mem_types[i].prot_l1 &= ~PMD_BIT4;
342 } else if (cpu_arch < CPU_ARCH_ARMv6) {
343 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
344 if (mem_types[i].prot_l1)
345 mem_types[i].prot_l1 |= PMD_BIT4;
346 if (mem_types[i].prot_sect)
347 mem_types[i].prot_sect |= PMD_BIT4;
352 * Mark the device areas according to the CPU/architecture.
354 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
355 if (!cpu_is_xsc3()) {
357 * Mark device regions on ARMv6+ as execute-never
358 * to prevent speculative instruction fetches.
360 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
361 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
362 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
363 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
365 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
367 * For ARMv7 with TEX remapping,
368 * - shared device is SXCB=1100
369 * - nonshared device is SXCB=0100
370 * - write combine device mem is SXCB=0001
371 * (Uncached Normal memory)
373 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
374 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
375 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
376 } else if (cpu_is_xsc3()) {
379 * - shared device is TEXCB=00101
380 * - nonshared device is TEXCB=01000
381 * - write combine device mem is TEXCB=00100
382 * (Inner/Outer Uncacheable in xsc3 parlance)
384 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
385 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
386 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
389 * For ARMv6 and ARMv7 without TEX remapping,
390 * - shared device is TEXCB=00001
391 * - nonshared device is TEXCB=01000
392 * - write combine device mem is TEXCB=00100
393 * (Uncached Normal in ARMv6 parlance).
395 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
396 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
397 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
401 * On others, write combining is "Uncached/Buffered"
403 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
407 * Now deal with the memory-type mappings
409 cp = &cache_policies[cachepolicy];
410 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
413 * Only use write-through for non-SMP systems
415 if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
416 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
419 * Enable CPU-specific coherency if supported.
420 * (Only available on XSC3 at the moment.)
422 if (arch_is_coherent() && cpu_is_xsc3()) {
423 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
424 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
425 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
426 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
429 * ARMv6 and above have extended page tables.
431 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
433 * Mark cache clean areas and XIP ROM read only
434 * from SVC mode and no access from userspace.
436 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
437 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
438 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
442 * Mark memory with the "shared" attribute
445 user_pgprot |= L_PTE_SHARED;
446 kern_pgprot |= L_PTE_SHARED;
447 vecs_pgprot |= L_PTE_SHARED;
448 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
449 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
450 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
451 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
452 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
453 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
454 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
455 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
460 * Non-cacheable Normal - intended for memory areas that must
461 * not cause dirty cache line writebacks when used
463 if (cpu_arch >= CPU_ARCH_ARMv6) {
464 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
465 /* Non-cacheable Normal is XCB = 001 */
466 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
469 /* For both ARMv6 and non-TEX-remapping ARMv7 */
470 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
474 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
477 for (i = 0; i < 16; i++) {
478 unsigned long v = pgprot_val(protection_map[i]);
479 protection_map[i] = __pgprot(v | user_pgprot);
482 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
483 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
485 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
486 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
487 L_PTE_DIRTY | kern_pgprot);
489 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
490 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
491 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
492 mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
493 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
494 mem_types[MT_ROM].prot_sect |= cp->pmd;
498 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
502 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
505 printk("Memory policy: ECC %sabled, Data cache %s\n",
506 ecc_mask ? "en" : "dis", cp->policy);
508 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
509 struct mem_type *t = &mem_types[i];
511 t->prot_l1 |= PMD_DOMAIN(t->domain);
513 t->prot_sect |= PMD_DOMAIN(t->domain);
517 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
518 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
519 unsigned long size, pgprot_t vma_prot)
522 return pgprot_noncached(vma_prot);
523 else if (file->f_flags & O_SYNC)
524 return pgprot_writecombine(vma_prot);
527 EXPORT_SYMBOL(phys_mem_access_prot);
530 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
532 static void __init *early_alloc(unsigned long sz)
534 void *ptr = __va(memblock_alloc(sz, sz));
539 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
541 if (pmd_none(*pmd)) {
542 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
543 __pmd_populate(pmd, __pa(pte), prot);
545 BUG_ON(pmd_bad(*pmd));
546 return pte_offset_kernel(pmd, addr);
549 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
550 unsigned long end, unsigned long pfn,
551 const struct mem_type *type)
553 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
555 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
557 } while (pte++, addr += PAGE_SIZE, addr != end);
560 static void __init alloc_init_section(pud_t *pud, unsigned long addr,
561 unsigned long end, phys_addr_t phys,
562 const struct mem_type *type)
564 pmd_t *pmd = pmd_offset(pud, addr);
567 * Try a section mapping - end, addr and phys must all be aligned
568 * to a section boundary. Note that PMDs refer to the individual
569 * L1 entries, whereas PGDs refer to a group of L1 entries making
570 * up one logical pointer to an L2 table.
572 if (((addr | end | phys) & ~SECTION_MASK) == 0) {
575 if (addr & SECTION_SIZE)
579 *pmd = __pmd(phys | type->prot_sect);
580 phys += SECTION_SIZE;
581 } while (pmd++, addr += SECTION_SIZE, addr != end);
586 * No need to loop; pte's aren't interested in the
587 * individual L1 entries.
589 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
593 static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
594 unsigned long phys, const struct mem_type *type)
596 pud_t *pud = pud_offset(pgd, addr);
600 next = pud_addr_end(addr, end);
601 alloc_init_section(pud, addr, next, phys, type);
603 } while (pud++, addr = next, addr != end);
606 static void __init create_36bit_mapping(struct map_desc *md,
607 const struct mem_type *type)
609 unsigned long addr, length, end;
614 phys = __pfn_to_phys(md->pfn);
615 length = PAGE_ALIGN(md->length);
617 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
618 printk(KERN_ERR "MM: CPU does not support supersection "
619 "mapping for 0x%08llx at 0x%08lx\n",
620 (long long)__pfn_to_phys((u64)md->pfn), addr);
624 /* N.B. ARMv6 supersections are only defined to work with domain 0.
625 * Since domain assignments can in fact be arbitrary, the
626 * 'domain == 0' check below is required to insure that ARMv6
627 * supersections are only allocated for domain 0 regardless
628 * of the actual domain assignments in use.
631 printk(KERN_ERR "MM: invalid domain in supersection "
632 "mapping for 0x%08llx at 0x%08lx\n",
633 (long long)__pfn_to_phys((u64)md->pfn), addr);
637 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
638 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
639 " at 0x%08lx invalid alignment\n",
640 (long long)__pfn_to_phys((u64)md->pfn), addr);
645 * Shift bits [35:32] of address into bits [23:20] of PMD
648 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
650 pgd = pgd_offset_k(addr);
653 pud_t *pud = pud_offset(pgd, addr);
654 pmd_t *pmd = pmd_offset(pud, addr);
657 for (i = 0; i < 16; i++)
658 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
660 addr += SUPERSECTION_SIZE;
661 phys += SUPERSECTION_SIZE;
662 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
663 } while (addr != end);
667 * Create the page directory entries and any necessary
668 * page tables for the mapping specified by `md'. We
669 * are able to cope here with varying sizes and address
670 * offsets, and we take full advantage of sections and
673 static void __init create_mapping(struct map_desc *md)
675 unsigned long addr, length, end;
677 const struct mem_type *type;
680 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
681 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
682 " at 0x%08lx in user region\n",
683 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
687 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
688 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
689 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
690 " at 0x%08lx overlaps vmalloc space\n",
691 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
694 type = &mem_types[md->type];
697 * Catch 36-bit addresses
699 if (md->pfn >= 0x100000) {
700 create_36bit_mapping(md, type);
704 addr = md->virtual & PAGE_MASK;
705 phys = __pfn_to_phys(md->pfn);
706 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
708 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
709 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
710 "be mapped using pages, ignoring.\n",
711 (long long)__pfn_to_phys(md->pfn), addr);
715 pgd = pgd_offset_k(addr);
718 unsigned long next = pgd_addr_end(addr, end);
720 alloc_init_pud(pgd, addr, next, phys, type);
724 } while (pgd++, addr != end);
728 * Create the architecture specific mappings
730 void __init iotable_init(struct map_desc *io_desc, int nr)
734 for (i = 0; i < nr; i++)
735 create_mapping(io_desc + i);
738 static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
741 * vmalloc=size forces the vmalloc area to be exactly 'size'
742 * bytes. This can be used to increase (or decrease) the vmalloc
743 * area - the default is 128m.
745 static int __init early_vmalloc(char *arg)
747 unsigned long vmalloc_reserve = memparse(arg, NULL);
749 if (vmalloc_reserve < SZ_16M) {
750 vmalloc_reserve = SZ_16M;
752 "vmalloc area too small, limiting to %luMB\n",
753 vmalloc_reserve >> 20);
756 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
757 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
759 "vmalloc area is too big, limiting to %luMB\n",
760 vmalloc_reserve >> 20);
763 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
766 early_param("vmalloc", early_vmalloc);
768 static phys_addr_t lowmem_limit __initdata = 0;
770 void __init sanity_check_meminfo(void)
772 int i, j, highmem = 0;
774 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
775 struct membank *bank = &meminfo.bank[j];
776 *bank = meminfo.bank[i];
778 #ifdef CONFIG_HIGHMEM
779 if (__va(bank->start) >= vmalloc_min ||
780 __va(bank->start) < (void *)PAGE_OFFSET)
783 bank->highmem = highmem;
786 * Split those memory banks which are partially overlapping
787 * the vmalloc area greatly simplifying things later.
789 if (__va(bank->start) < vmalloc_min &&
790 bank->size > vmalloc_min - __va(bank->start)) {
791 if (meminfo.nr_banks >= NR_BANKS) {
792 printk(KERN_CRIT "NR_BANKS too low, "
793 "ignoring high memory\n");
795 memmove(bank + 1, bank,
796 (meminfo.nr_banks - i) * sizeof(*bank));
799 bank[1].size -= vmalloc_min - __va(bank->start);
800 bank[1].start = __pa(vmalloc_min - 1) + 1;
801 bank[1].highmem = highmem = 1;
804 bank->size = vmalloc_min - __va(bank->start);
807 bank->highmem = highmem;
810 * Check whether this memory bank would entirely overlap
813 if (__va(bank->start) >= vmalloc_min ||
814 __va(bank->start) < (void *)PAGE_OFFSET) {
815 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
816 "(vmalloc region overlap).\n",
817 (unsigned long long)bank->start,
818 (unsigned long long)bank->start + bank->size - 1);
823 * Check whether this memory bank would partially overlap
826 if (__va(bank->start + bank->size) > vmalloc_min ||
827 __va(bank->start + bank->size) < __va(bank->start)) {
828 unsigned long newsize = vmalloc_min - __va(bank->start);
829 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
830 "to -%.8llx (vmalloc region overlap).\n",
831 (unsigned long long)bank->start,
832 (unsigned long long)bank->start + bank->size - 1,
833 (unsigned long long)bank->start + newsize - 1);
834 bank->size = newsize;
837 if (!bank->highmem && bank->start + bank->size > lowmem_limit)
838 lowmem_limit = bank->start + bank->size;
842 #ifdef CONFIG_HIGHMEM
844 const char *reason = NULL;
846 if (cache_is_vipt_aliasing()) {
848 * Interactions between kmap and other mappings
849 * make highmem support with aliasing VIPT caches
852 reason = "with VIPT aliasing cache";
855 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
857 while (j > 0 && meminfo.bank[j - 1].highmem)
862 meminfo.nr_banks = j;
863 high_memory = __va(lowmem_limit - 1) + 1;
864 memblock_set_current_limit(lowmem_limit);
867 static inline void prepare_page_table(void)
873 * Clear out all the mappings below the kernel image.
875 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
876 pmd_clear(pmd_off_k(addr));
878 #ifdef CONFIG_XIP_KERNEL
879 /* The XIP kernel is mapped in the module area -- skip over it */
880 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
882 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
883 pmd_clear(pmd_off_k(addr));
886 * Find the end of the first block of lowmem.
888 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
889 if (end >= lowmem_limit)
893 * Clear out all the kernel space mappings, except for the first
894 * memory bank, up to the end of the vmalloc region.
896 for (addr = __phys_to_virt(end);
897 addr < VMALLOC_END; addr += PMD_SIZE)
898 pmd_clear(pmd_off_k(addr));
901 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
904 * Reserve the special regions of memory
906 void __init arm_mm_memblock_reserve(void)
909 * Reserve the page tables. These are already in use,
910 * and can only be in node 0.
912 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
916 * Because of the SA1111 DMA bug, we want to preserve our
917 * precious DMA-able memory...
919 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
924 * Set up device the mappings. Since we clear out the page tables for all
925 * mappings above VMALLOC_END, we will remove any debug device mappings.
926 * This means you have to be careful how you debug this function, or any
927 * called function. This means you can't use any function or debugging
928 * method which may touch any device, otherwise the kernel _will_ crash.
930 static void __init devicemaps_init(struct machine_desc *mdesc)
936 * Allocate the vector page early.
938 vectors_page = early_alloc(PAGE_SIZE);
940 for (addr = VMALLOC_END; addr; addr += PMD_SIZE)
941 pmd_clear(pmd_off_k(addr));
944 * Map the kernel if it is XIP.
945 * It is always first in the modulearea.
947 #ifdef CONFIG_XIP_KERNEL
948 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
949 map.virtual = MODULES_VADDR;
950 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
952 create_mapping(&map);
956 * Map the cache flushing regions.
959 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
960 map.virtual = FLUSH_BASE;
962 map.type = MT_CACHECLEAN;
963 create_mapping(&map);
965 #ifdef FLUSH_BASE_MINICACHE
966 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
967 map.virtual = FLUSH_BASE_MINICACHE;
969 map.type = MT_MINICLEAN;
970 create_mapping(&map);
974 * Create a mapping for the machine vectors at the high-vectors
975 * location (0xffff0000). If we aren't using high-vectors, also
976 * create a mapping at the low-vectors virtual address.
978 map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
979 map.virtual = 0xffff0000;
980 map.length = PAGE_SIZE;
981 map.type = MT_HIGH_VECTORS;
982 create_mapping(&map);
984 if (!vectors_high()) {
986 map.type = MT_LOW_VECTORS;
987 create_mapping(&map);
991 * Ask the machine support to map in the statically mapped devices.
997 * Finally flush the caches and tlb to ensure that we're in a
998 * consistent state wrt the writebuffer. This also ensures that
999 * any write-allocated cache lines in the vector page are written
1000 * back. After this point, we can start to touch devices again.
1002 local_flush_tlb_all();
1006 static void __init kmap_init(void)
1008 #ifdef CONFIG_HIGHMEM
1009 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1010 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1014 static void __init map_lowmem(void)
1016 struct memblock_region *reg;
1018 /* Map all the lowmem memory banks. */
1019 for_each_memblock(memory, reg) {
1020 phys_addr_t start = reg->base;
1021 phys_addr_t end = start + reg->size;
1022 struct map_desc map;
1024 if (end > lowmem_limit)
1029 map.pfn = __phys_to_pfn(start);
1030 map.virtual = __phys_to_virt(start);
1031 map.length = end - start;
1032 map.type = MT_MEMORY;
1034 create_mapping(&map);
1039 * paging_init() sets up the page tables, initialises the zone memory
1040 * maps, and sets up the zero page, bad page and bad page tables.
1042 void __init paging_init(struct machine_desc *mdesc)
1046 memblock_set_current_limit(lowmem_limit);
1048 build_mem_type_table();
1049 prepare_page_table();
1051 devicemaps_init(mdesc);
1054 top_pmd = pmd_off_k(0xffff0000);
1056 /* allocate the zero page. */
1057 zero_page = early_alloc(PAGE_SIZE);
1061 empty_zero_page = virt_to_page(zero_page);
1062 __flush_dcache_page(NULL, empty_zero_page);