2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
19 #include <asm/cputype.h>
20 #include <asm/sections.h>
21 #include <asm/cachetype.h>
22 #include <asm/setup.h>
23 #include <asm/sizes.h>
24 #include <asm/smp_plat.h>
26 #include <asm/highmem.h>
28 #include <asm/mach/arch.h>
29 #include <asm/mach/map.h>
33 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
36 * empty_zero_page is a special page that is used for
37 * zero-initialized data and COW.
39 struct page *empty_zero_page;
40 EXPORT_SYMBOL(empty_zero_page);
43 * The pmd table for the upper-most set of pages.
47 #define CPOLICY_UNCACHED 0
48 #define CPOLICY_BUFFERED 1
49 #define CPOLICY_WRITETHROUGH 2
50 #define CPOLICY_WRITEBACK 3
51 #define CPOLICY_WRITEALLOC 4
53 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
54 static unsigned int ecc_mask __initdata = 0;
56 pgprot_t pgprot_kernel;
58 EXPORT_SYMBOL(pgprot_user);
59 EXPORT_SYMBOL(pgprot_kernel);
62 const char policy[16];
68 static struct cachepolicy cache_policies[] __initdata = {
72 .pmd = PMD_SECT_UNCACHED,
73 .pte = L_PTE_MT_UNCACHED,
77 .pmd = PMD_SECT_BUFFERED,
78 .pte = L_PTE_MT_BUFFERABLE,
80 .policy = "writethrough",
83 .pte = L_PTE_MT_WRITETHROUGH,
85 .policy = "writeback",
88 .pte = L_PTE_MT_WRITEBACK,
90 .policy = "writealloc",
93 .pte = L_PTE_MT_WRITEALLOC,
98 * These are useful for identifying cache coherency
99 * problems by allowing the cache or the cache and
100 * writebuffer to be turned off. (Note: the write
101 * buffer should not be on and the cache off).
103 static int __init early_cachepolicy(char *p)
107 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
108 int len = strlen(cache_policies[i].policy);
110 if (memcmp(p, cache_policies[i].policy, len) == 0) {
112 cr_alignment &= ~cache_policies[i].cr_mask;
113 cr_no_alignment &= ~cache_policies[i].cr_mask;
117 if (i == ARRAY_SIZE(cache_policies))
118 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
120 * This restriction is partly to do with the way we boot; it is
121 * unpredictable to have memory mapped using two different sets of
122 * memory attributes (shared, type, and cache attribs). We can not
123 * change these attributes once the initial assembly has setup the
126 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
127 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
128 cachepolicy = CPOLICY_WRITEBACK;
131 set_cr(cr_alignment);
134 early_param("cachepolicy", early_cachepolicy);
136 static int __init early_nocache(char *__unused)
138 char *p = "buffered";
139 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
140 early_cachepolicy(p);
143 early_param("nocache", early_nocache);
145 static int __init early_nowrite(char *__unused)
147 char *p = "uncached";
148 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
149 early_cachepolicy(p);
152 early_param("nowb", early_nowrite);
154 static int __init early_ecc(char *p)
156 if (memcmp(p, "on", 2) == 0)
157 ecc_mask = PMD_PROTECTION;
158 else if (memcmp(p, "off", 3) == 0)
162 early_param("ecc", early_ecc);
164 static int __init noalign_setup(char *__unused)
166 cr_alignment &= ~CR_A;
167 cr_no_alignment &= ~CR_A;
168 set_cr(cr_alignment);
171 __setup("noalign", noalign_setup);
174 void adjust_cr(unsigned long mask, unsigned long set)
182 local_irq_save(flags);
184 cr_no_alignment = (cr_no_alignment & ~mask) | set;
185 cr_alignment = (cr_alignment & ~mask) | set;
187 set_cr((get_cr() & ~mask) | set);
189 local_irq_restore(flags);
193 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
194 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
196 static struct mem_type mem_types[] = {
197 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
198 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
200 .prot_l1 = PMD_TYPE_TABLE,
201 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
204 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
205 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
206 .prot_l1 = PMD_TYPE_TABLE,
207 .prot_sect = PROT_SECT_DEVICE,
210 [MT_DEVICE_CACHED] = { /* ioremap_cached */
211 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
212 .prot_l1 = PMD_TYPE_TABLE,
213 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
216 [MT_DEVICE_WC] = { /* ioremap_wc */
217 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
218 .prot_l1 = PMD_TYPE_TABLE,
219 .prot_sect = PROT_SECT_DEVICE,
223 .prot_pte = PROT_PTE_DEVICE,
224 .prot_l1 = PMD_TYPE_TABLE,
225 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
229 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
230 .domain = DOMAIN_KERNEL,
233 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
234 .domain = DOMAIN_KERNEL,
237 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
239 .prot_l1 = PMD_TYPE_TABLE,
240 .domain = DOMAIN_USER,
242 [MT_HIGH_VECTORS] = {
243 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
244 L_PTE_USER | L_PTE_EXEC,
245 .prot_l1 = PMD_TYPE_TABLE,
246 .domain = DOMAIN_USER,
249 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
250 L_PTE_WRITE | L_PTE_EXEC,
251 .prot_l1 = PMD_TYPE_TABLE,
252 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
253 .domain = DOMAIN_KERNEL,
256 .prot_sect = PMD_TYPE_SECT,
257 .domain = DOMAIN_KERNEL,
259 [MT_MEMORY_NONCACHED] = {
260 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
261 L_PTE_WRITE | L_PTE_EXEC | L_PTE_MT_BUFFERABLE,
262 .prot_l1 = PMD_TYPE_TABLE,
263 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
264 .domain = DOMAIN_KERNEL,
267 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
269 .prot_l1 = PMD_TYPE_TABLE,
270 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
271 .domain = DOMAIN_KERNEL,
274 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
275 L_PTE_WRITE | L_PTE_EXEC,
276 .prot_l1 = PMD_TYPE_TABLE,
277 .domain = DOMAIN_KERNEL,
281 const struct mem_type *get_mem_type(unsigned int type)
283 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
285 EXPORT_SYMBOL(get_mem_type);
288 * Adjust the PMD section entries according to the CPU in use.
290 static void __init build_mem_type_table(void)
292 struct cachepolicy *cp;
293 unsigned int cr = get_cr();
294 unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
295 int cpu_arch = cpu_architecture();
298 if (cpu_arch < CPU_ARCH_ARMv6) {
299 #if defined(CONFIG_CPU_DCACHE_DISABLE)
300 if (cachepolicy > CPOLICY_BUFFERED)
301 cachepolicy = CPOLICY_BUFFERED;
302 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
303 if (cachepolicy > CPOLICY_WRITETHROUGH)
304 cachepolicy = CPOLICY_WRITETHROUGH;
307 if (cpu_arch < CPU_ARCH_ARMv5) {
308 if (cachepolicy >= CPOLICY_WRITEALLOC)
309 cachepolicy = CPOLICY_WRITEBACK;
313 cachepolicy = CPOLICY_WRITEALLOC;
316 * Strip out features not present on earlier architectures.
317 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
318 * without extended page tables don't have the 'Shared' bit.
320 if (cpu_arch < CPU_ARCH_ARMv5)
321 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
322 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
323 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
324 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
325 mem_types[i].prot_sect &= ~PMD_SECT_S;
328 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
329 * "update-able on write" bit on ARM610). However, Xscale and
330 * Xscale3 require this bit to be cleared.
332 if (cpu_is_xscale() || cpu_is_xsc3()) {
333 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
334 mem_types[i].prot_sect &= ~PMD_BIT4;
335 mem_types[i].prot_l1 &= ~PMD_BIT4;
337 } else if (cpu_arch < CPU_ARCH_ARMv6) {
338 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
339 if (mem_types[i].prot_l1)
340 mem_types[i].prot_l1 |= PMD_BIT4;
341 if (mem_types[i].prot_sect)
342 mem_types[i].prot_sect |= PMD_BIT4;
347 * Mark the device areas according to the CPU/architecture.
349 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
350 if (!cpu_is_xsc3()) {
352 * Mark device regions on ARMv6+ as execute-never
353 * to prevent speculative instruction fetches.
355 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
356 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
357 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
358 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
360 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
362 * For ARMv7 with TEX remapping,
363 * - shared device is SXCB=1100
364 * - nonshared device is SXCB=0100
365 * - write combine device mem is SXCB=0001
366 * (Uncached Normal memory)
368 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
369 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
370 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
371 } else if (cpu_is_xsc3()) {
374 * - shared device is TEXCB=00101
375 * - nonshared device is TEXCB=01000
376 * - write combine device mem is TEXCB=00100
377 * (Inner/Outer Uncacheable in xsc3 parlance)
379 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
380 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
381 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
384 * For ARMv6 and ARMv7 without TEX remapping,
385 * - shared device is TEXCB=00001
386 * - nonshared device is TEXCB=01000
387 * - write combine device mem is TEXCB=00100
388 * (Uncached Normal in ARMv6 parlance).
390 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
391 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
392 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
396 * On others, write combining is "Uncached/Buffered"
398 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
402 * Now deal with the memory-type mappings
404 cp = &cache_policies[cachepolicy];
405 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
408 * Only use write-through for non-SMP systems
410 if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
411 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
414 * Enable CPU-specific coherency if supported.
415 * (Only available on XSC3 at the moment.)
417 if (arch_is_coherent() && cpu_is_xsc3()) {
418 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
419 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
420 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
421 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
424 * ARMv6 and above have extended page tables.
426 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
428 * Mark cache clean areas and XIP ROM read only
429 * from SVC mode and no access from userspace.
431 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
432 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
433 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
437 * Mark memory with the "shared" attribute
440 user_pgprot |= L_PTE_SHARED;
441 kern_pgprot |= L_PTE_SHARED;
442 vecs_pgprot |= L_PTE_SHARED;
443 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
444 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
445 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
446 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
447 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
448 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
449 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
450 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
455 * Non-cacheable Normal - intended for memory areas that must
456 * not cause dirty cache line writebacks when used
458 if (cpu_arch >= CPU_ARCH_ARMv6) {
459 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
460 /* Non-cacheable Normal is XCB = 001 */
461 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
464 /* For both ARMv6 and non-TEX-remapping ARMv7 */
465 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
469 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
472 for (i = 0; i < 16; i++) {
473 unsigned long v = pgprot_val(protection_map[i]);
474 protection_map[i] = __pgprot(v | user_pgprot);
477 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
478 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
480 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
481 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
482 L_PTE_DIRTY | L_PTE_WRITE | kern_pgprot);
484 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
485 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
486 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
487 mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
488 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
489 mem_types[MT_ROM].prot_sect |= cp->pmd;
493 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
497 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
500 printk("Memory policy: ECC %sabled, Data cache %s\n",
501 ecc_mask ? "en" : "dis", cp->policy);
503 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
504 struct mem_type *t = &mem_types[i];
506 t->prot_l1 |= PMD_DOMAIN(t->domain);
508 t->prot_sect |= PMD_DOMAIN(t->domain);
512 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
513 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
514 unsigned long size, pgprot_t vma_prot)
517 return pgprot_noncached(vma_prot);
518 else if (file->f_flags & O_SYNC)
519 return pgprot_writecombine(vma_prot);
522 EXPORT_SYMBOL(phys_mem_access_prot);
525 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
527 static void __init *early_alloc(unsigned long sz)
529 void *ptr = __va(memblock_alloc(sz, sz));
534 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
536 if (pmd_none(*pmd)) {
537 pte_t *pte = early_alloc(2 * PTRS_PER_PTE * sizeof(pte_t));
538 __pmd_populate(pmd, __pa(pte) | prot);
540 BUG_ON(pmd_bad(*pmd));
541 return pte_offset_kernel(pmd, addr);
544 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
545 unsigned long end, unsigned long pfn,
546 const struct mem_type *type)
548 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
550 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
552 } while (pte++, addr += PAGE_SIZE, addr != end);
555 static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
556 unsigned long end, unsigned long phys,
557 const struct mem_type *type)
559 pmd_t *pmd = pmd_offset(pgd, addr);
562 * Try a section mapping - end, addr and phys must all be aligned
563 * to a section boundary. Note that PMDs refer to the individual
564 * L1 entries, whereas PGDs refer to a group of L1 entries making
565 * up one logical pointer to an L2 table.
567 if (((addr | end | phys) & ~SECTION_MASK) == 0) {
570 if (addr & SECTION_SIZE)
574 *pmd = __pmd(phys | type->prot_sect);
575 phys += SECTION_SIZE;
576 } while (pmd++, addr += SECTION_SIZE, addr != end);
581 * No need to loop; pte's aren't interested in the
582 * individual L1 entries.
584 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
588 static void __init create_36bit_mapping(struct map_desc *md,
589 const struct mem_type *type)
591 unsigned long phys, addr, length, end;
595 phys = (unsigned long)__pfn_to_phys(md->pfn);
596 length = PAGE_ALIGN(md->length);
598 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
599 printk(KERN_ERR "MM: CPU does not support supersection "
600 "mapping for 0x%08llx at 0x%08lx\n",
601 __pfn_to_phys((u64)md->pfn), addr);
605 /* N.B. ARMv6 supersections are only defined to work with domain 0.
606 * Since domain assignments can in fact be arbitrary, the
607 * 'domain == 0' check below is required to insure that ARMv6
608 * supersections are only allocated for domain 0 regardless
609 * of the actual domain assignments in use.
612 printk(KERN_ERR "MM: invalid domain in supersection "
613 "mapping for 0x%08llx at 0x%08lx\n",
614 __pfn_to_phys((u64)md->pfn), addr);
618 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
619 printk(KERN_ERR "MM: cannot create mapping for "
620 "0x%08llx at 0x%08lx invalid alignment\n",
621 __pfn_to_phys((u64)md->pfn), addr);
626 * Shift bits [35:32] of address into bits [23:20] of PMD
629 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
631 pgd = pgd_offset_k(addr);
634 pmd_t *pmd = pmd_offset(pgd, addr);
637 for (i = 0; i < 16; i++)
638 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
640 addr += SUPERSECTION_SIZE;
641 phys += SUPERSECTION_SIZE;
642 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
643 } while (addr != end);
647 * Create the page directory entries and any necessary
648 * page tables for the mapping specified by `md'. We
649 * are able to cope here with varying sizes and address
650 * offsets, and we take full advantage of sections and
653 static void __init create_mapping(struct map_desc *md)
655 unsigned long phys, addr, length, end;
656 const struct mem_type *type;
659 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
660 printk(KERN_WARNING "BUG: not creating mapping for "
661 "0x%08llx at 0x%08lx in user region\n",
662 __pfn_to_phys((u64)md->pfn), md->virtual);
666 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
667 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
668 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
669 "overlaps vmalloc space\n",
670 __pfn_to_phys((u64)md->pfn), md->virtual);
673 type = &mem_types[md->type];
676 * Catch 36-bit addresses
678 if (md->pfn >= 0x100000) {
679 create_36bit_mapping(md, type);
683 addr = md->virtual & PAGE_MASK;
684 phys = (unsigned long)__pfn_to_phys(md->pfn);
685 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
687 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
688 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
689 "be mapped using pages, ignoring.\n",
690 __pfn_to_phys(md->pfn), addr);
694 pgd = pgd_offset_k(addr);
697 unsigned long next = pgd_addr_end(addr, end);
699 alloc_init_section(pgd, addr, next, phys, type);
703 } while (pgd++, addr != end);
707 * Create the architecture specific mappings
709 void __init iotable_init(struct map_desc *io_desc, int nr)
713 for (i = 0; i < nr; i++)
714 create_mapping(io_desc + i);
717 static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
720 * vmalloc=size forces the vmalloc area to be exactly 'size'
721 * bytes. This can be used to increase (or decrease) the vmalloc
722 * area - the default is 128m.
724 static int __init early_vmalloc(char *arg)
726 unsigned long vmalloc_reserve = memparse(arg, NULL);
728 if (vmalloc_reserve < SZ_16M) {
729 vmalloc_reserve = SZ_16M;
731 "vmalloc area too small, limiting to %luMB\n",
732 vmalloc_reserve >> 20);
735 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
736 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
738 "vmalloc area is too big, limiting to %luMB\n",
739 vmalloc_reserve >> 20);
742 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
745 early_param("vmalloc", early_vmalloc);
747 static phys_addr_t lowmem_limit __initdata = 0;
749 static void __init sanity_check_meminfo(void)
751 int i, j, highmem = 0;
753 lowmem_limit = __pa(vmalloc_min - 1) + 1;
754 memblock_set_current_limit(lowmem_limit);
756 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
757 struct membank *bank = &meminfo.bank[j];
758 *bank = meminfo.bank[i];
760 #ifdef CONFIG_HIGHMEM
761 if (__va(bank->start) > vmalloc_min ||
762 __va(bank->start) < (void *)PAGE_OFFSET)
765 bank->highmem = highmem;
768 * Split those memory banks which are partially overlapping
769 * the vmalloc area greatly simplifying things later.
771 if (__va(bank->start) < vmalloc_min &&
772 bank->size > vmalloc_min - __va(bank->start)) {
773 if (meminfo.nr_banks >= NR_BANKS) {
774 printk(KERN_CRIT "NR_BANKS too low, "
775 "ignoring high memory\n");
777 memmove(bank + 1, bank,
778 (meminfo.nr_banks - i) * sizeof(*bank));
781 bank[1].size -= vmalloc_min - __va(bank->start);
782 bank[1].start = __pa(vmalloc_min - 1) + 1;
783 bank[1].highmem = highmem = 1;
786 bank->size = vmalloc_min - __va(bank->start);
789 bank->highmem = highmem;
792 * Check whether this memory bank would entirely overlap
795 if (__va(bank->start) >= vmalloc_min ||
796 __va(bank->start) < (void *)PAGE_OFFSET) {
797 printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
798 "(vmalloc region overlap).\n",
799 bank->start, bank->start + bank->size - 1);
804 * Check whether this memory bank would partially overlap
807 if (__va(bank->start + bank->size) > vmalloc_min ||
808 __va(bank->start + bank->size) < __va(bank->start)) {
809 unsigned long newsize = vmalloc_min - __va(bank->start);
810 printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
811 "to -%.8lx (vmalloc region overlap).\n",
812 bank->start, bank->start + bank->size - 1,
813 bank->start + newsize - 1);
814 bank->size = newsize;
819 #ifdef CONFIG_HIGHMEM
821 const char *reason = NULL;
823 if (cache_is_vipt_aliasing()) {
825 * Interactions between kmap and other mappings
826 * make highmem support with aliasing VIPT caches
829 reason = "with VIPT aliasing cache";
830 } else if (is_smp() && tlb_ops_need_broadcast()) {
832 * kmap_high needs to occasionally flush TLB entries,
833 * however, if the TLB entries need to be broadcast
835 * kmap_high(irqs off)->flush_all_zero_pkmaps->
836 * flush_tlb_kernel_range->smp_call_function_many
837 * (must not be called with irqs off)
839 reason = "without hardware TLB ops broadcasting";
842 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
844 while (j > 0 && meminfo.bank[j - 1].highmem)
849 meminfo.nr_banks = j;
852 static inline void prepare_page_table(void)
858 * Clear out all the mappings below the kernel image.
860 for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE)
861 pmd_clear(pmd_off_k(addr));
863 #ifdef CONFIG_XIP_KERNEL
864 /* The XIP kernel is mapped in the module area -- skip over it */
865 addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
867 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
868 pmd_clear(pmd_off_k(addr));
871 * Find the end of the first block of lowmem.
873 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
874 if (end >= lowmem_limit)
878 * Clear out all the kernel space mappings, except for the first
879 * memory bank, up to the end of the vmalloc region.
881 for (addr = __phys_to_virt(end);
882 addr < VMALLOC_END; addr += PGDIR_SIZE)
883 pmd_clear(pmd_off_k(addr));
887 * Reserve the special regions of memory
889 void __init arm_mm_memblock_reserve(void)
892 * Reserve the page tables. These are already in use,
893 * and can only be in node 0.
895 memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t));
899 * Because of the SA1111 DMA bug, we want to preserve our
900 * precious DMA-able memory...
902 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
907 * Set up device the mappings. Since we clear out the page tables for all
908 * mappings above VMALLOC_END, we will remove any debug device mappings.
909 * This means you have to be careful how you debug this function, or any
910 * called function. This means you can't use any function or debugging
911 * method which may touch any device, otherwise the kernel _will_ crash.
913 static void __init devicemaps_init(struct machine_desc *mdesc)
920 * Allocate the vector page early.
922 vectors = early_alloc(PAGE_SIZE);
924 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
925 pmd_clear(pmd_off_k(addr));
928 * Map the kernel if it is XIP.
929 * It is always first in the modulearea.
931 #ifdef CONFIG_XIP_KERNEL
932 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
933 map.virtual = MODULES_VADDR;
934 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
936 create_mapping(&map);
940 * Map the cache flushing regions.
943 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
944 map.virtual = FLUSH_BASE;
946 map.type = MT_CACHECLEAN;
947 create_mapping(&map);
949 #ifdef FLUSH_BASE_MINICACHE
950 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
951 map.virtual = FLUSH_BASE_MINICACHE;
953 map.type = MT_MINICLEAN;
954 create_mapping(&map);
958 * Create a mapping for the machine vectors at the high-vectors
959 * location (0xffff0000). If we aren't using high-vectors, also
960 * create a mapping at the low-vectors virtual address.
962 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
963 map.virtual = 0xffff0000;
964 map.length = PAGE_SIZE;
965 map.type = MT_HIGH_VECTORS;
966 create_mapping(&map);
968 if (!vectors_high()) {
970 map.type = MT_LOW_VECTORS;
971 create_mapping(&map);
975 * Ask the machine support to map in the statically mapped devices.
981 * Finally flush the caches and tlb to ensure that we're in a
982 * consistent state wrt the writebuffer. This also ensures that
983 * any write-allocated cache lines in the vector page are written
984 * back. After this point, we can start to touch devices again.
986 local_flush_tlb_all();
990 static void __init kmap_init(void)
992 #ifdef CONFIG_HIGHMEM
993 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
994 PKMAP_BASE, _PAGE_KERNEL_TABLE);
998 static void __init map_lowmem(void)
1000 struct memblock_region *reg;
1002 /* Map all the lowmem memory banks. */
1003 for_each_memblock(memory, reg) {
1004 phys_addr_t start = reg->base;
1005 phys_addr_t end = start + reg->size;
1006 struct map_desc map;
1008 if (end > lowmem_limit)
1013 map.pfn = __phys_to_pfn(start);
1014 map.virtual = __phys_to_virt(start);
1015 map.length = end - start;
1016 map.type = MT_MEMORY;
1018 create_mapping(&map);
1023 * paging_init() sets up the page tables, initialises the zone memory
1024 * maps, and sets up the zero page, bad page and bad page tables.
1026 void __init paging_init(struct machine_desc *mdesc)
1030 build_mem_type_table();
1031 sanity_check_meminfo();
1032 prepare_page_table();
1034 devicemaps_init(mdesc);
1037 top_pmd = pmd_off_k(0xffff0000);
1039 /* allocate the zero page. */
1040 zero_page = early_alloc(PAGE_SIZE);
1044 empty_zero_page = virt_to_page(zero_page);
1045 __flush_dcache_page(NULL, empty_zero_page);
1049 * In order to soft-boot, we need to insert a 1:1 mapping in place of
1050 * the user-mode pages. This will then ensure that we have predictable
1051 * results when turning the mmu off
1053 void setup_mm_for_reboot(char mode)
1055 unsigned long base_pmdval;
1060 * We need to access to user-mode page tables here. For kernel threads
1061 * we don't have any user-mode mappings so we use the context that we
1064 pgd = current->active_mm->pgd;
1066 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
1067 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
1068 base_pmdval |= PMD_BIT4;
1070 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
1071 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
1074 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
1075 pmd[0] = __pmd(pmdval);
1076 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
1077 flush_pmd_entry(pmd);
1080 local_flush_tlb_all();