arch/arm/mm/mmu.c

   1 /*
   2  *  linux/arch/arm/mm/mmu.c
   3  *
   4  *  Copyright (C) 1995-2005 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/init.h>
  14 #include <linux/mman.h>
  15 #include <linux/nodemask.h>
  16 #include <linux/memblock.h>
  17 #include <linux/fs.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/sizes.h>
  20
  21 #include <asm/cp15.h>
  22 #include <asm/cputype.h>
  23 #include <asm/sections.h>
  24 #include <asm/cachetype.h>
  25 #include <asm/setup.h>
  26 #include <asm/smp_plat.h>
  27 #include <asm/tlb.h>
  28 #include <asm/highmem.h>
  29 #include <asm/system_info.h>
  30 #include <asm/traps.h>
  31
  32 #include <asm/mach/arch.h>
  33 #include <asm/mach/map.h>
  34 #include <asm/mach/pci.h>
  35
  36 #include "mm.h"
  37
  38 /*
  39  * empty_zero_page is a special page that is used for
  40  * zero-initialized data and COW.
  41  */
  42 struct page *empty_zero_page;
  43 EXPORT_SYMBOL(empty_zero_page);
  44
  45 /*
  46  * The pmd table for the upper-most set of pages.
  47  */
  48 pmd_t *top_pmd;
  49
  50 #define CPOLICY_UNCACHED        0
  51 #define CPOLICY_BUFFERED        1
  52 #define CPOLICY_WRITETHROUGH    2
  53 #define CPOLICY_WRITEBACK       3
  54 #define CPOLICY_WRITEALLOC      4
  55
  56 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  57 static unsigned int ecc_mask __initdata = 0;
  58 pgprot_t pgprot_user;
  59 pgprot_t pgprot_kernel;
  60 pgprot_t pgprot_hyp_device;
  61 pgprot_t pgprot_s2;
  62 pgprot_t pgprot_s2_device;
  63
  64 EXPORT_SYMBOL(pgprot_user);
  65 EXPORT_SYMBOL(pgprot_kernel);
  66
  67 struct cachepolicy {
  68         const char      policy[16];
  69         unsigned int    cr_mask;
  70         pmdval_t        pmd;
  71         pteval_t        pte;
  72         pteval_t        pte_s2;
  73 };
  74
  75 #ifdef CONFIG_ARM_LPAE
  76 #define s2_policy(policy)       policy
  77 #else
  78 #define s2_policy(policy)       0
  79 #endif
  80
  81 static struct cachepolicy cache_policies[] __initdata = {
  82         {
  83                 .policy         = "uncached",
  84                 .cr_mask        = CR_W|CR_C,
  85                 .pmd            = PMD_SECT_UNCACHED,
  86                 .pte            = L_PTE_MT_UNCACHED,
  87                 .pte_s2         = s2_policy(L_PTE_S2_MT_UNCACHED),
  88         }, {
  89                 .policy         = "buffered",
  90                 .cr_mask        = CR_C,
  91                 .pmd            = PMD_SECT_BUFFERED,
  92                 .pte            = L_PTE_MT_BUFFERABLE,
  93                 .pte_s2         = s2_policy(L_PTE_S2_MT_UNCACHED),
  94         }, {
  95                 .policy         = "writethrough",
  96                 .cr_mask        = 0,
  97                 .pmd            = PMD_SECT_WT,
  98                 .pte            = L_PTE_MT_WRITETHROUGH,
  99                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
 100         }, {
 101                 .policy         = "writeback",
 102                 .cr_mask        = 0,
 103                 .pmd            = PMD_SECT_WB,
 104                 .pte            = L_PTE_MT_WRITEBACK,
 105                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITEBACK),
 106         }, {
 107                 .policy         = "writealloc",
 108                 .cr_mask        = 0,
 109                 .pmd            = PMD_SECT_WBWA,
 110                 .pte            = L_PTE_MT_WRITEALLOC,
 111                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITEBACK),
 112         }
 113 };
 114
 115 #ifdef CONFIG_CPU_CP15
 116 /*
 117  * These are useful for identifying cache coherency
 118  * problems by allowing the cache or the cache and
 119  * writebuffer to be turned off.  (Note: the write
 120  * buffer should not be on and the cache off).
 121  */
 122 static int __init early_cachepolicy(char *p)
 123 {
 124         int i;
 125
 126         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
 127                 int len = strlen(cache_policies[i].policy);
 128
 129                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
 130                         cachepolicy = i;
 131                         cr_alignment &= ~cache_policies[i].cr_mask;
 132                         cr_no_alignment &= ~cache_policies[i].cr_mask;
 133                         break;
 134                 }
 135         }
 136         if (i == ARRAY_SIZE(cache_policies))
 137                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 138         /*
 139          * This restriction is partly to do with the way we boot; it is
 140          * unpredictable to have memory mapped using two different sets of
 141          * memory attributes (shared, type, and cache attribs).  We can not
 142          * change these attributes once the initial assembly has setup the
 143          * page tables.
 144          */
 145         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
 146                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
 147                 cachepolicy = CPOLICY_WRITEBACK;
 148         }
 149         flush_cache_all();
 150         set_cr(cr_alignment);
 151         return 0;
 152 }
 153 early_param("cachepolicy", early_cachepolicy);
 154
 155 static int __init early_nocache(char *__unused)
 156 {
 157         char *p = "buffered";
 158         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 159         early_cachepolicy(p);
 160         return 0;
 161 }
 162 early_param("nocache", early_nocache);
 163
 164 static int __init early_nowrite(char *__unused)
 165 {
 166         char *p = "uncached";
 167         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 168         early_cachepolicy(p);
 169         return 0;
 170 }
 171 early_param("nowb", early_nowrite);
 172
 173 #ifndef CONFIG_ARM_LPAE
 174 static int __init early_ecc(char *p)
 175 {
 176         if (memcmp(p, "on", 2) == 0)
 177                 ecc_mask = PMD_PROTECTION;
 178         else if (memcmp(p, "off", 3) == 0)
 179                 ecc_mask = 0;
 180         return 0;
 181 }
 182 early_param("ecc", early_ecc);
 183 #endif
 184
 185 static int __init noalign_setup(char *__unused)
 186 {
 187         cr_alignment &= ~CR_A;
 188         cr_no_alignment &= ~CR_A;
 189         set_cr(cr_alignment);
 190         return 1;
 191 }
 192 __setup("noalign", noalign_setup);
 193
 194 #ifndef CONFIG_SMP
 195 void adjust_cr(unsigned long mask, unsigned long set)
 196 {
 197         unsigned long flags;
 198
 199         mask &= ~CR_A;
 200
 201         set &= mask;
 202
 203         local_irq_save(flags);
 204
 205         cr_no_alignment = (cr_no_alignment & ~mask) | set;
 206         cr_alignment = (cr_alignment & ~mask) | set;
 207
 208         set_cr((get_cr() & ~mask) | set);
 209
 210         local_irq_restore(flags);
 211 }
 212 #endif
 213
 214 #else /* ifdef CONFIG_CPU_CP15 */
 215
 216 static int __init early_cachepolicy(char *p)
 217 {
 218         pr_warning("cachepolicy kernel parameter not supported without cp15\n");
 219 }
 220 early_param("cachepolicy", early_cachepolicy);
 221
 222 static int __init noalign_setup(char *__unused)
 223 {
 224         pr_warning("noalign kernel parameter not supported without cp15\n");
 225 }
 226 __setup("noalign", noalign_setup);
 227
 228 #endif /* ifdef CONFIG_CPU_CP15 / else */
 229
 230 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
 231 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 232
 233 static struct mem_type mem_types[] = {
 234         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
 235                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
 236                                   L_PTE_SHARED,
 237                 .prot_l1        = PMD_TYPE_TABLE,
 238                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
 239                 .domain         = DOMAIN_IO,
 240         },
 241         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
 242                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
 243                 .prot_l1        = PMD_TYPE_TABLE,
 244                 .prot_sect      = PROT_SECT_DEVICE,
 245                 .domain         = DOMAIN_IO,
 246         },
 247         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
 248                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
 249                 .prot_l1        = PMD_TYPE_TABLE,
 250                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
 251                 .domain         = DOMAIN_IO,
 252         },
 253         [MT_DEVICE_WC] = {      /* ioremap_wc */
 254                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
 255                 .prot_l1        = PMD_TYPE_TABLE,
 256                 .prot_sect      = PROT_SECT_DEVICE,
 257                 .domain         = DOMAIN_IO,
 258         },
 259         [MT_UNCACHED] = {
 260                 .prot_pte       = PROT_PTE_DEVICE,
 261                 .prot_l1        = PMD_TYPE_TABLE,
 262                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
 263                 .domain         = DOMAIN_IO,
 264         },
 265         [MT_CACHECLEAN] = {
 266                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 267                 .domain    = DOMAIN_KERNEL,
 268         },
 269 #ifndef CONFIG_ARM_LPAE
 270         [MT_MINICLEAN] = {
 271                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
 272                 .domain    = DOMAIN_KERNEL,
 273         },
 274 #endif
 275         [MT_LOW_VECTORS] = {
 276                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 277                                 L_PTE_RDONLY,
 278                 .prot_l1   = PMD_TYPE_TABLE,
 279                 .domain    = DOMAIN_USER,
 280         },
 281         [MT_HIGH_VECTORS] = {
 282                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 283                                 L_PTE_USER | L_PTE_RDONLY,
 284                 .prot_l1   = PMD_TYPE_TABLE,
 285                 .domain    = DOMAIN_USER,
 286         },
 287         [MT_MEMORY] = {
 288                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 289                 .prot_l1   = PMD_TYPE_TABLE,
 290                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 291                 .domain    = DOMAIN_KERNEL,
 292         },
 293         [MT_ROM] = {
 294                 .prot_sect = PMD_TYPE_SECT,
 295                 .domain    = DOMAIN_KERNEL,
 296         },
 297         [MT_MEMORY_NONCACHED] = {
 298                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 299                                 L_PTE_MT_BUFFERABLE,
 300                 .prot_l1   = PMD_TYPE_TABLE,
 301                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 302                 .domain    = DOMAIN_KERNEL,
 303         },
 304         [MT_MEMORY_DTCM] = {
 305                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 306                                 L_PTE_XN,
 307                 .prot_l1   = PMD_TYPE_TABLE,
 308                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 309                 .domain    = DOMAIN_KERNEL,
 310         },
 311         [MT_MEMORY_ITCM] = {
 312                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 313                 .prot_l1   = PMD_TYPE_TABLE,
 314                 .domain    = DOMAIN_KERNEL,
 315         },
 316         [MT_MEMORY_SO] = {
 317                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 318                                 L_PTE_MT_UNCACHED | L_PTE_XN,
 319                 .prot_l1   = PMD_TYPE_TABLE,
 320                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
 321                                 PMD_SECT_UNCACHED | PMD_SECT_XN,
 322                 .domain    = DOMAIN_KERNEL,
 323         },
 324         [MT_MEMORY_DMA_READY] = {
 325                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 326                 .prot_l1   = PMD_TYPE_TABLE,
 327                 .domain    = DOMAIN_KERNEL,
 328         },
 329 };
 330
 331 const struct mem_type *get_mem_type(unsigned int type)
 332 {
 333         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
 334 }
 335 EXPORT_SYMBOL(get_mem_type);
 336
 337 /*
 338  * Adjust the PMD section entries according to the CPU in use.
 339  */
 340 static void __init build_mem_type_table(void)
 341 {
 342         struct cachepolicy *cp;
 343         unsigned int cr = get_cr();
 344         pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
 345         pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
 346         int cpu_arch = cpu_architecture();
 347         int i;
 348
 349         if (cpu_arch < CPU_ARCH_ARMv6) {
 350 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 351                 if (cachepolicy > CPOLICY_BUFFERED)
 352                         cachepolicy = CPOLICY_BUFFERED;
 353 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 354                 if (cachepolicy > CPOLICY_WRITETHROUGH)
 355                         cachepolicy = CPOLICY_WRITETHROUGH;
 356 #endif
 357         }
 358         if (cpu_arch < CPU_ARCH_ARMv5) {
 359                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 360                         cachepolicy = CPOLICY_WRITEBACK;
 361                 ecc_mask = 0;
 362         }
 363         if (is_smp())
 364                 cachepolicy = CPOLICY_WRITEALLOC;
 365
 366         /*
 367          * Strip out features not present on earlier architectures.
 368          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
 369          * without extended page tables don't have the 'Shared' bit.
 370          */
 371         if (cpu_arch < CPU_ARCH_ARMv5)
 372                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 373                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
 374         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
 375                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 376                         mem_types[i].prot_sect &= ~PMD_SECT_S;
 377
 378         /*
 379          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
 380          * "update-able on write" bit on ARM610).  However, Xscale and
 381          * Xscale3 require this bit to be cleared.
 382          */
 383         if (cpu_is_xscale() || cpu_is_xsc3()) {
 384                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 385                         mem_types[i].prot_sect &= ~PMD_BIT4;
 386                         mem_types[i].prot_l1 &= ~PMD_BIT4;
 387                 }
 388         } else if (cpu_arch < CPU_ARCH_ARMv6) {
 389                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 390                         if (mem_types[i].prot_l1)
 391                                 mem_types[i].prot_l1 |= PMD_BIT4;
 392                         if (mem_types[i].prot_sect)
 393                                 mem_types[i].prot_sect |= PMD_BIT4;
 394                 }
 395         }
 396
 397         /*
 398          * Mark the device areas according to the CPU/architecture.
 399          */
 400         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
 401                 if (!cpu_is_xsc3()) {
 402                         /*
 403                          * Mark device regions on ARMv6+ as execute-never
 404                          * to prevent speculative instruction fetches.
 405                          */
 406                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
 407                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
 408                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
 409                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
 410                 }
 411                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 412                         /*
 413                          * For ARMv7 with TEX remapping,
 414                          * - shared device is SXCB=1100
 415                          * - nonshared device is SXCB=0100
 416                          * - write combine device mem is SXCB=0001
 417                          * (Uncached Normal memory)
 418                          */
 419                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
 420                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
 421                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 422                 } else if (cpu_is_xsc3()) {
 423                         /*
 424                          * For Xscale3,
 425                          * - shared device is TEXCB=00101
 426                          * - nonshared device is TEXCB=01000
 427                          * - write combine device mem is TEXCB=00100
 428                          * (Inner/Outer Uncacheable in xsc3 parlance)
 429                          */
 430                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
 431                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 432                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 433                 } else {
 434                         /*
 435                          * For ARMv6 and ARMv7 without TEX remapping,
 436                          * - shared device is TEXCB=00001
 437                          * - nonshared device is TEXCB=01000
 438                          * - write combine device mem is TEXCB=00100
 439                          * (Uncached Normal in ARMv6 parlance).
 440                          */
 441                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 442                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 443                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 444                 }
 445         } else {
 446                 /*
 447                  * On others, write combining is "Uncached/Buffered"
 448                  */
 449                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 450         }
 451
 452         /*
 453          * Now deal with the memory-type mappings
 454          */
 455         cp = &cache_policies[cachepolicy];
 456         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 457         s2_pgprot = cp->pte_s2;
 458         hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
 459
 460         /*
 461          * ARMv6 and above have extended page tables.
 462          */
 463         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 464 #ifndef CONFIG_ARM_LPAE
 465                 /*
 466                  * Mark cache clean areas and XIP ROM read only
 467                  * from SVC mode and no access from userspace.
 468                  */
 469                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 470                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 471                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 472 #endif
 473
 474                 if (is_smp()) {
 475                         /*
 476                          * Mark memory with the "shared" attribute
 477                          * for SMP systems
 478                          */
 479                         user_pgprot |= L_PTE_SHARED;
 480                         kern_pgprot |= L_PTE_SHARED;
 481                         vecs_pgprot |= L_PTE_SHARED;
 482                         s2_pgprot |= L_PTE_SHARED;
 483                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
 484                         mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
 485                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
 486                         mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
 487                         mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 488                         mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 489                         mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
 490                         mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 491                         mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 492                 }
 493         }
 494
 495         /*
 496          * Non-cacheable Normal - intended for memory areas that must
 497          * not cause dirty cache line writebacks when used
 498          */
 499         if (cpu_arch >= CPU_ARCH_ARMv6) {
 500                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 501                         /* Non-cacheable Normal is XCB = 001 */
 502                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 503                                 PMD_SECT_BUFFERED;
 504                 } else {
 505                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
 506                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 507                                 PMD_SECT_TEX(1);
 508                 }
 509         } else {
 510                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
 511         }
 512
 513 #ifdef CONFIG_ARM_LPAE
 514         /*
 515          * Do not generate access flag faults for the kernel mappings.
 516          */
 517         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 518                 mem_types[i].prot_pte |= PTE_EXT_AF;
 519                 if (mem_types[i].prot_sect)
 520                         mem_types[i].prot_sect |= PMD_SECT_AF;
 521         }
 522         kern_pgprot |= PTE_EXT_AF;
 523         vecs_pgprot |= PTE_EXT_AF;
 524 #endif
 525
 526         for (i = 0; i < 16; i++) {
 527                 pteval_t v = pgprot_val(protection_map[i]);
 528                 protection_map[i] = __pgprot(v | user_pgprot);
 529         }
 530
 531         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
 532         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
 533
 534         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
 535         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 536                                  L_PTE_DIRTY | kern_pgprot);
 537         pgprot_s2  = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
 538         pgprot_s2_device  = __pgprot(s2_device_pgprot);
 539         pgprot_hyp_device  = __pgprot(hyp_device_pgprot);
 540
 541         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 542         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 543         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 544         mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
 545         mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
 546         mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
 547         mem_types[MT_ROM].prot_sect |= cp->pmd;
 548
 549         switch (cp->pmd) {
 550         case PMD_SECT_WT:
 551                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 552                 break;
 553         case PMD_SECT_WB:
 554         case PMD_SECT_WBWA:
 555                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 556                 break;
 557         }
 558         printk("Memory policy: ECC %sabled, Data cache %s\n",
 559                 ecc_mask ? "en" : "dis", cp->policy);
 560
 561         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 562                 struct mem_type *t = &mem_types[i];
 563                 if (t->prot_l1)
 564                         t->prot_l1 |= PMD_DOMAIN(t->domain);
 565                 if (t->prot_sect)
 566                         t->prot_sect |= PMD_DOMAIN(t->domain);
 567         }
 568 }
 569
 570 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 571 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 572                               unsigned long size, pgprot_t vma_prot)
 573 {
 574         if (!pfn_valid(pfn))
 575                 return pgprot_noncached(vma_prot);
 576         else if (file->f_flags & O_SYNC)
 577                 return pgprot_writecombine(vma_prot);
 578         return vma_prot;
 579 }
 580 EXPORT_SYMBOL(phys_mem_access_prot);
 581 #endif
 582
 583 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 584
 585 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
 586 {
 587         void *ptr = __va(memblock_alloc(sz, align));
 588         memset(ptr, 0, sz);
 589         return ptr;
 590 }
 591
 592 static void __init *early_alloc(unsigned long sz)
 593 {
 594         return early_alloc_aligned(sz, sz);
 595 }
 596
 597 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
 598 {
 599         if (pmd_none(*pmd)) {
 600                 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
 601                 __pmd_populate(pmd, __pa(pte), prot);
 602         }
 603         BUG_ON(pmd_bad(*pmd));
 604         return pte_offset_kernel(pmd, addr);
 605 }
 606
 607 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 608                                   unsigned long end, unsigned long pfn,
 609                                   const struct mem_type *type)
 610 {
 611         pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
 612         do {
 613                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
 614                 pfn++;
 615         } while (pte++, addr += PAGE_SIZE, addr != end);
 616 }
 617
 618 static void __init map_init_section(pmd_t *pmd, unsigned long addr,
 619                         unsigned long end, phys_addr_t phys,
 620                         const struct mem_type *type)
 621 {
 622 #ifndef CONFIG_ARM_LPAE
 623         /*
 624          * In classic MMU format, puds and pmds are folded in to
 625          * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
 626          * group of L1 entries making up one logical pointer to
 627          * an L2 table (2MB), where as PMDs refer to the individual
 628          * L1 entries (1MB). Hence increment to get the correct
 629          * offset for odd 1MB sections.
 630          * (See arch/arm/include/asm/pgtable-2level.h)
 631          */
 632         if (addr & SECTION_SIZE)
 633                 pmd++;
 634 #endif
 635         do {
 636                 *pmd = __pmd(phys | type->prot_sect);
 637                 phys += SECTION_SIZE;
 638         } while (pmd++, addr += SECTION_SIZE, addr != end);
 639
 640         flush_pmd_entry(pmd);
 641 }
 642
 643 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
 644                                       unsigned long end, phys_addr_t phys,
 645                                       const struct mem_type *type)
 646 {
 647         pmd_t *pmd = pmd_offset(pud, addr);
 648         unsigned long next;
 649
 650         do {
 651                 /*
 652                  * With LPAE, we must loop over to map
 653                  * all the pmds for the given range.
 654                  */
 655                 next = pmd_addr_end(addr, end);
 656
 657                 /*
 658                  * Try a section mapping - addr, next and phys must all be
 659                  * aligned to a section boundary.
 660                  */
 661                 if (type->prot_sect &&
 662                                 ((addr | next | phys) & ~SECTION_MASK) == 0) {
 663                         map_init_section(pmd, addr, next, phys, type);
 664                 } else {
 665                         alloc_init_pte(pmd, addr, next,
 666                                                 __phys_to_pfn(phys), type);
 667                 }
 668
 669                 phys += next - addr;
 670
 671         } while (pmd++, addr = next, addr != end);
 672 }
 673
 674 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
 675         unsigned long end, unsigned long phys, const struct mem_type *type)
 676 {
 677         pud_t *pud = pud_offset(pgd, addr);
 678         unsigned long next;
 679
 680         do {
 681                 next = pud_addr_end(addr, end);
 682                 alloc_init_pmd(pud, addr, next, phys, type);
 683                 phys += next - addr;
 684         } while (pud++, addr = next, addr != end);
 685 }
 686
 687 #ifndef CONFIG_ARM_LPAE
 688 static void __init create_36bit_mapping(struct map_desc *md,
 689                                         const struct mem_type *type)
 690 {
 691         unsigned long addr, length, end;
 692         phys_addr_t phys;
 693         pgd_t *pgd;
 694
 695         addr = md->virtual;
 696         phys = __pfn_to_phys(md->pfn);
 697         length = PAGE_ALIGN(md->length);
 698
 699         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
 700                 printk(KERN_ERR "MM: CPU does not support supersection "
 701                        "mapping for 0x%08llx at 0x%08lx\n",
 702                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 703                 return;
 704         }
 705
 706         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 707          *      Since domain assignments can in fact be arbitrary, the
 708          *      'domain == 0' check below is required to insure that ARMv6
 709          *      supersections are only allocated for domain 0 regardless
 710          *      of the actual domain assignments in use.
 711          */
 712         if (type->domain) {
 713                 printk(KERN_ERR "MM: invalid domain in supersection "
 714                        "mapping for 0x%08llx at 0x%08lx\n",
 715                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 716                 return;
 717         }
 718
 719         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
 720                 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
 721                        " at 0x%08lx invalid alignment\n",
 722                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 723                 return;
 724         }
 725
 726         /*
 727          * Shift bits [35:32] of address into bits [23:20] of PMD
 728          * (See ARMv6 spec).
 729          */
 730         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
 731
 732         pgd = pgd_offset_k(addr);
 733         end = addr + length;
 734         do {
 735                 pud_t *pud = pud_offset(pgd, addr);
 736                 pmd_t *pmd = pmd_offset(pud, addr);
 737                 int i;
 738
 739                 for (i = 0; i < 16; i++)
 740                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
 741
 742                 addr += SUPERSECTION_SIZE;
 743                 phys += SUPERSECTION_SIZE;
 744                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
 745         } while (addr != end);
 746 }
 747 #endif  /* !CONFIG_ARM_LPAE */
 748
 749 /*
 750  * Create the page directory entries and any necessary
 751  * page tables for the mapping specified by `md'.  We
 752  * are able to cope here with varying sizes and address
 753  * offsets, and we take full advantage of sections and
 754  * supersections.
 755  */
 756 static void __init create_mapping(struct map_desc *md)
 757 {
 758         unsigned long addr, length, end;
 759         phys_addr_t phys;
 760         const struct mem_type *type;
 761         pgd_t *pgd;
 762
 763         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 764                 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
 765                        " at 0x%08lx in user region\n",
 766                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 767                 return;
 768         }
 769
 770         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 771             md->virtual >= PAGE_OFFSET &&
 772             (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
 773                 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
 774                        " at 0x%08lx out of vmalloc space\n",
 775                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 776         }
 777
 778         type = &mem_types[md->type];
 779
 780 #ifndef CONFIG_ARM_LPAE
 781         /*
 782          * Catch 36-bit addresses
 783          */
 784         if (md->pfn >= 0x100000) {
 785                 create_36bit_mapping(md, type);
 786                 return;
 787         }
 788 #endif
 789
 790         addr = md->virtual & PAGE_MASK;
 791         phys = __pfn_to_phys(md->pfn);
 792         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 793
 794         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
 795                 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
 796                        "be mapped using pages, ignoring.\n",
 797                        (long long)__pfn_to_phys(md->pfn), addr);
 798                 return;
 799         }
 800
 801         pgd = pgd_offset_k(addr);
 802         end = addr + length;
 803         do {
 804                 unsigned long next = pgd_addr_end(addr, end);
 805
 806                 alloc_init_pud(pgd, addr, next, phys, type);
 807
 808                 phys += next - addr;
 809                 addr = next;
 810         } while (pgd++, addr != end);
 811 }
 812
 813 /*
 814  * Create the architecture specific mappings
 815  */
 816 void __init iotable_init(struct map_desc *io_desc, int nr)
 817 {
 818         struct map_desc *md;
 819         struct vm_struct *vm;
 820         struct static_vm *svm;
 821
 822         if (!nr)
 823                 return;
 824
 825         svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
 826
 827         for (md = io_desc; nr; md++, nr--) {
 828                 create_mapping(md);
 829
 830                 vm = &svm->vm;
 831                 vm->addr = (void *)(md->virtual & PAGE_MASK);
 832                 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 833                 vm->phys_addr = __pfn_to_phys(md->pfn);
 834                 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
 835                 vm->flags |= VM_ARM_MTYPE(md->type);
 836                 vm->caller = iotable_init;
 837                 add_static_vm_early(svm++);
 838         }
 839 }
 840
 841 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
 842                                   void *caller)
 843 {
 844         struct vm_struct *vm;
 845         struct static_vm *svm;
 846
 847         svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
 848
 849         vm = &svm->vm;
 850         vm->addr = (void *)addr;
 851         vm->size = size;
 852         vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
 853         vm->caller = caller;
 854         add_static_vm_early(svm);
 855 }
 856
 857 #ifndef CONFIG_ARM_LPAE
 858
 859 /*
 860  * The Linux PMD is made of two consecutive section entries covering 2MB
 861  * (see definition in include/asm/pgtable-2level.h).  However a call to
 862  * create_mapping() may optimize static mappings by using individual
 863  * 1MB section mappings.  This leaves the actual PMD potentially half
 864  * initialized if the top or bottom section entry isn't used, leaving it
 865  * open to problems if a subsequent ioremap() or vmalloc() tries to use
 866  * the virtual space left free by that unused section entry.
 867  *
 868  * Let's avoid the issue by inserting dummy vm entries covering the unused
 869  * PMD halves once the static mappings are in place.
 870  */
 871
 872 static void __init pmd_empty_section_gap(unsigned long addr)
 873 {
 874         vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
 875 }
 876
 877 static void __init fill_pmd_gaps(void)
 878 {
 879         struct static_vm *svm;
 880         struct vm_struct *vm;
 881         unsigned long addr, next = 0;
 882         pmd_t *pmd;
 883
 884         list_for_each_entry(svm, &static_vmlist, list) {
 885                 vm = &svm->vm;
 886                 addr = (unsigned long)vm->addr;
 887                 if (addr < next)
 888                         continue;
 889
 890                 /*
 891                  * Check if this vm starts on an odd section boundary.
 892                  * If so and the first section entry for this PMD is free
 893                  * then we block the corresponding virtual address.
 894                  */
 895                 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
 896                         pmd = pmd_off_k(addr);
 897                         if (pmd_none(*pmd))
 898                                 pmd_empty_section_gap(addr & PMD_MASK);
 899                 }
 900
 901                 /*
 902                  * Then check if this vm ends on an odd section boundary.
 903                  * If so and the second section entry for this PMD is empty
 904                  * then we block the corresponding virtual address.
 905                  */
 906                 addr += vm->size;
 907                 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
 908                         pmd = pmd_off_k(addr) + 1;
 909                         if (pmd_none(*pmd))
 910                                 pmd_empty_section_gap(addr);
 911                 }
 912
 913                 /* no need to look at any vm entry until we hit the next PMD */
 914                 next = (addr + PMD_SIZE - 1) & PMD_MASK;
 915         }
 916 }
 917
 918 #else
 919 #define fill_pmd_gaps() do { } while (0)
 920 #endif
 921
 922 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
 923 static void __init pci_reserve_io(void)
 924 {
 925         struct static_vm *svm;
 926
 927         svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
 928         if (svm)
 929                 return;
 930
 931         vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
 932 }
 933 #else
 934 #define pci_reserve_io() do { } while (0)
 935 #endif
 936
 937 #ifdef CONFIG_DEBUG_LL
 938 void __init debug_ll_io_init(void)
 939 {
 940         struct map_desc map;
 941
 942         debug_ll_addr(&map.pfn, &map.virtual);
 943         if (!map.pfn || !map.virtual)
 944                 return;
 945         map.pfn = __phys_to_pfn(map.pfn);
 946         map.virtual &= PAGE_MASK;
 947         map.length = PAGE_SIZE;
 948         map.type = MT_DEVICE;
 949         create_mapping(&map);
 950 }
 951 #endif
 952
 953 static void * __initdata vmalloc_min =
 954         (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
 955
 956 /*
 957  * vmalloc=size forces the vmalloc area to be exactly 'size'
 958  * bytes. This can be used to increase (or decrease) the vmalloc
 959  * area - the default is 240m.
 960  */
 961 static int __init early_vmalloc(char *arg)
 962 {
 963         unsigned long vmalloc_reserve = memparse(arg, NULL);
 964
 965         if (vmalloc_reserve < SZ_16M) {
 966                 vmalloc_reserve = SZ_16M;
 967                 printk(KERN_WARNING
 968                         "vmalloc area too small, limiting to %luMB\n",
 969                         vmalloc_reserve >> 20);
 970         }
 971
 972         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
 973                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
 974                 printk(KERN_WARNING
 975                         "vmalloc area is too big, limiting to %luMB\n",
 976                         vmalloc_reserve >> 20);
 977         }
 978
 979         vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
 980         return 0;
 981 }
 982 early_param("vmalloc", early_vmalloc);
 983
 984 phys_addr_t arm_lowmem_limit __initdata = 0;
 985
 986 void __init sanity_check_meminfo(void)
 987 {
 988         int i, j, highmem = 0;
 989
 990         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 991                 struct membank *bank = &meminfo.bank[j];
 992                 *bank = meminfo.bank[i];
 993
 994                 if (bank->start > ULONG_MAX)
 995                         highmem = 1;
 996
 997 #ifdef CONFIG_HIGHMEM
 998                 if (__va(bank->start) >= vmalloc_min ||
 999                     __va(bank->start) < (void *)PAGE_OFFSET)
1000                         highmem = 1;
1001
1002                 bank->highmem = highmem;
1003
1004                 /*
1005                  * Split those memory banks which are partially overlapping
1006                  * the vmalloc area greatly simplifying things later.
1007                  */
1008                 if (!highmem && __va(bank->start) < vmalloc_min &&
1009                     bank->size > vmalloc_min - __va(bank->start)) {
1010                         if (meminfo.nr_banks >= NR_BANKS) {
1011                                 printk(KERN_CRIT "NR_BANKS too low, "
1012                                                  "ignoring high memory\n");
1013                         } else {
1014                                 memmove(bank + 1, bank,
1015                                         (meminfo.nr_banks - i) * sizeof(*bank));
1016                                 meminfo.nr_banks++;
1017                                 i++;
1018                                 bank[1].size -= vmalloc_min - __va(bank->start);
1019                                 bank[1].start = __pa(vmalloc_min - 1) + 1;
1020                                 bank[1].highmem = highmem = 1;
1021                                 j++;
1022                         }
1023                         bank->size = vmalloc_min - __va(bank->start);
1024                 }
1025 #else
1026                 bank->highmem = highmem;
1027
1028                 /*
1029                  * Highmem banks not allowed with !CONFIG_HIGHMEM.
1030                  */
1031                 if (highmem) {
1032                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1033                                "(!CONFIG_HIGHMEM).\n",
1034                                (unsigned long long)bank->start,
1035                                (unsigned long long)bank->start + bank->size - 1);
1036                         continue;
1037                 }
1038
1039                 /*
1040                  * Check whether this memory bank would entirely overlap
1041                  * the vmalloc area.
1042                  */
1043                 if (__va(bank->start) >= vmalloc_min ||
1044                     __va(bank->start) < (void *)PAGE_OFFSET) {
1045                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1046                                "(vmalloc region overlap).\n",
1047                                (unsigned long long)bank->start,
1048                                (unsigned long long)bank->start + bank->size - 1);
1049                         continue;
1050                 }
1051
1052                 /*
1053                  * Check whether this memory bank would partially overlap
1054                  * the vmalloc area.
1055                  */
1056                 if (__va(bank->start + bank->size - 1) >= vmalloc_min ||
1057                     __va(bank->start + bank->size - 1) <= __va(bank->start)) {
1058                         unsigned long newsize = vmalloc_min - __va(bank->start);
1059                         printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
1060                                "to -%.8llx (vmalloc region overlap).\n",
1061                                (unsigned long long)bank->start,
1062                                (unsigned long long)bank->start + bank->size - 1,
1063                                (unsigned long long)bank->start + newsize - 1);
1064                         bank->size = newsize;
1065                 }
1066 #endif
1067                 if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
1068                         arm_lowmem_limit = bank->start + bank->size;
1069
1070                 j++;
1071         }
1072 #ifdef CONFIG_HIGHMEM
1073         if (highmem) {
1074                 const char *reason = NULL;
1075
1076                 if (cache_is_vipt_aliasing()) {
1077                         /*
1078                          * Interactions between kmap and other mappings
1079                          * make highmem support with aliasing VIPT caches
1080                          * rather difficult.
1081                          */
1082                         reason = "with VIPT aliasing cache";
1083                 }
1084                 if (reason) {
1085                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1086                                 reason);
1087                         while (j > 0 && meminfo.bank[j - 1].highmem)
1088                                 j--;
1089                 }
1090         }
1091 #endif
1092         meminfo.nr_banks = j;
1093         high_memory = __va(arm_lowmem_limit - 1) + 1;
1094         memblock_set_current_limit(arm_lowmem_limit);
1095 }
1096
1097 static inline void prepare_page_table(void)
1098 {
1099         unsigned long addr;
1100         phys_addr_t end;
1101
1102         /*
1103          * Clear out all the mappings below the kernel image.
1104          */
1105         for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1106                 pmd_clear(pmd_off_k(addr));
1107
1108 #ifdef CONFIG_XIP_KERNEL
1109         /* The XIP kernel is mapped in the module area -- skip over it */
1110         addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1111 #endif
1112         for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1113                 pmd_clear(pmd_off_k(addr));
1114
1115         /*
1116          * Find the end of the first block of lowmem.
1117          */
1118         end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1119         if (end >= arm_lowmem_limit)
1120                 end = arm_lowmem_limit;
1121
1122         /*
1123          * Clear out all the kernel space mappings, except for the first
1124          * memory bank, up to the vmalloc region.
1125          */
1126         for (addr = __phys_to_virt(end);
1127              addr < VMALLOC_START; addr += PMD_SIZE)
1128                 pmd_clear(pmd_off_k(addr));
1129 }
1130
1131 #ifdef CONFIG_ARM_LPAE
1132 /* the first page is reserved for pgd */
1133 #define SWAPPER_PG_DIR_SIZE     (PAGE_SIZE + \
1134                                  PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1135 #else
1136 #define SWAPPER_PG_DIR_SIZE     (PTRS_PER_PGD * sizeof(pgd_t))
1137 #endif
1138
1139 /*
1140  * Reserve the special regions of memory
1141  */
1142 void __init arm_mm_memblock_reserve(void)
1143 {
1144         /*
1145          * Reserve the page tables.  These are already in use,
1146          * and can only be in node 0.
1147          */
1148         memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1149
1150 #ifdef CONFIG_SA1111
1151         /*
1152          * Because of the SA1111 DMA bug, we want to preserve our
1153          * precious DMA-able memory...
1154          */
1155         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1156 #endif
1157 }
1158
1159 /*
1160  * Set up the device mappings.  Since we clear out the page tables for all
1161  * mappings above VMALLOC_START, we will remove any debug device mappings.
1162  * This means you have to be careful how you debug this function, or any
1163  * called function.  This means you can't use any function or debugging
1164  * method which may touch any device, otherwise the kernel _will_ crash.
1165  */
1166 static void __init devicemaps_init(struct machine_desc *mdesc)
1167 {
1168         struct map_desc map;
1169         unsigned long addr;
1170         void *vectors;
1171
1172         /*
1173          * Allocate the vector page early.
1174          */
1175         vectors = early_alloc(PAGE_SIZE);
1176
1177         early_trap_init(vectors);
1178
1179         for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1180                 pmd_clear(pmd_off_k(addr));
1181
1182         /*
1183          * Map the kernel if it is XIP.
1184          * It is always first in the modulearea.
1185          */
1186 #ifdef CONFIG_XIP_KERNEL
1187         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1188         map.virtual = MODULES_VADDR;
1189         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1190         map.type = MT_ROM;
1191         create_mapping(&map);
1192 #endif
1193
1194         /*
1195          * Map the cache flushing regions.
1196          */
1197 #ifdef FLUSH_BASE
1198         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1199         map.virtual = FLUSH_BASE;
1200         map.length = SZ_1M;
1201         map.type = MT_CACHECLEAN;
1202         create_mapping(&map);
1203 #endif
1204 #ifdef FLUSH_BASE_MINICACHE
1205         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1206         map.virtual = FLUSH_BASE_MINICACHE;
1207         map.length = SZ_1M;
1208         map.type = MT_MINICLEAN;
1209         create_mapping(&map);
1210 #endif
1211
1212         /*
1213          * Create a mapping for the machine vectors at the high-vectors
1214          * location (0xffff0000).  If we aren't using high-vectors, also
1215          * create a mapping at the low-vectors virtual address.
1216          */
1217         map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1218         map.virtual = 0xffff0000;
1219         map.length = PAGE_SIZE;
1220         map.type = MT_HIGH_VECTORS;
1221         create_mapping(&map);
1222
1223         if (!vectors_high()) {
1224                 map.virtual = 0;
1225                 map.type = MT_LOW_VECTORS;
1226                 create_mapping(&map);
1227         }
1228
1229         /*
1230          * Ask the machine support to map in the statically mapped devices.
1231          */
1232         if (mdesc->map_io)
1233                 mdesc->map_io();
1234         fill_pmd_gaps();
1235
1236         /* Reserve fixed i/o space in VMALLOC region */
1237         pci_reserve_io();
1238
1239         /*
1240          * Finally flush the caches and tlb to ensure that we're in a
1241          * consistent state wrt the writebuffer.  This also ensures that
1242          * any write-allocated cache lines in the vector page are written
1243          * back.  After this point, we can start to touch devices again.
1244          */
1245         local_flush_tlb_all();
1246         flush_cache_all();
1247 }
1248
1249 static void __init kmap_init(void)
1250 {
1251 #ifdef CONFIG_HIGHMEM
1252         pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1253                 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1254 #endif
1255 }
1256
1257 static void __init map_lowmem(void)
1258 {
1259         struct memblock_region *reg;
1260
1261         /* Map all the lowmem memory banks. */
1262         for_each_memblock(memory, reg) {
1263                 phys_addr_t start = reg->base;
1264                 phys_addr_t end = start + reg->size;
1265                 struct map_desc map;
1266
1267                 if (end > arm_lowmem_limit)
1268                         end = arm_lowmem_limit;
1269                 if (start >= end)
1270                         break;
1271
1272                 map.pfn = __phys_to_pfn(start);
1273                 map.virtual = __phys_to_virt(start);
1274                 map.length = end - start;
1275                 map.type = MT_MEMORY;
1276
1277                 create_mapping(&map);
1278         }
1279 }
1280
1281 /*
1282  * paging_init() sets up the page tables, initialises the zone memory
1283  * maps, and sets up the zero page, bad page and bad page tables.
1284  */
1285 void __init paging_init(struct machine_desc *mdesc)
1286 {
1287         void *zero_page;
1288
1289         memblock_set_current_limit(arm_lowmem_limit);
1290
1291         build_mem_type_table();
1292         prepare_page_table();
1293         map_lowmem();
1294         dma_contiguous_remap();
1295         devicemaps_init(mdesc);
1296         kmap_init();
1297
1298         top_pmd = pmd_off_k(0xffff0000);
1299
1300         /* allocate the zero page. */
1301         zero_page = early_alloc(PAGE_SIZE);
1302
1303         bootmem_init();
1304
1305         empty_zero_page = virt_to_page(zero_page);
1306         __flush_dcache_page(NULL, empty_zero_page);
1307 }