2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
18 #include <linux/vmalloc.h>
20 #include <asm/cputype.h>
21 #include <asm/sections.h>
22 #include <asm/cachetype.h>
23 #include <asm/setup.h>
24 #include <asm/sizes.h>
25 #include <asm/smp_plat.h>
27 #include <asm/highmem.h>
28 #include <asm/traps.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
36 * empty_zero_page is a special page that is used for
37 * zero-initialized data and COW.
39 struct page *empty_zero_page;
40 EXPORT_SYMBOL(empty_zero_page);
43 * The pmd table for the upper-most set of pages.
47 #define CPOLICY_UNCACHED 0
48 #define CPOLICY_BUFFERED 1
49 #define CPOLICY_WRITETHROUGH 2
50 #define CPOLICY_WRITEBACK 3
51 #define CPOLICY_WRITEALLOC 4
53 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
54 static unsigned int ecc_mask __initdata = 0;
56 pgprot_t pgprot_kernel;
58 EXPORT_SYMBOL(pgprot_user);
59 EXPORT_SYMBOL(pgprot_kernel);
62 const char policy[16];
68 static struct cachepolicy cache_policies[] __initdata = {
72 .pmd = PMD_SECT_UNCACHED,
73 .pte = L_PTE_MT_UNCACHED,
77 .pmd = PMD_SECT_BUFFERED,
78 .pte = L_PTE_MT_BUFFERABLE,
80 .policy = "writethrough",
83 .pte = L_PTE_MT_WRITETHROUGH,
85 .policy = "writeback",
88 .pte = L_PTE_MT_WRITEBACK,
90 .policy = "writealloc",
93 .pte = L_PTE_MT_WRITEALLOC,
98 * These are useful for identifying cache coherency
99 * problems by allowing the cache or the cache and
100 * writebuffer to be turned off. (Note: the write
101 * buffer should not be on and the cache off).
103 static int __init early_cachepolicy(char *p)
107 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
108 int len = strlen(cache_policies[i].policy);
110 if (memcmp(p, cache_policies[i].policy, len) == 0) {
112 cr_alignment &= ~cache_policies[i].cr_mask;
113 cr_no_alignment &= ~cache_policies[i].cr_mask;
117 if (i == ARRAY_SIZE(cache_policies))
118 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
120 * This restriction is partly to do with the way we boot; it is
121 * unpredictable to have memory mapped using two different sets of
122 * memory attributes (shared, type, and cache attribs). We can not
123 * change these attributes once the initial assembly has setup the
126 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
127 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
128 cachepolicy = CPOLICY_WRITEBACK;
131 set_cr(cr_alignment);
134 early_param("cachepolicy", early_cachepolicy);
136 static int __init early_nocache(char *__unused)
138 char *p = "buffered";
139 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
140 early_cachepolicy(p);
143 early_param("nocache", early_nocache);
145 static int __init early_nowrite(char *__unused)
147 char *p = "uncached";
148 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
149 early_cachepolicy(p);
152 early_param("nowb", early_nowrite);
154 static int __init early_ecc(char *p)
156 if (memcmp(p, "on", 2) == 0)
157 ecc_mask = PMD_PROTECTION;
158 else if (memcmp(p, "off", 3) == 0)
162 early_param("ecc", early_ecc);
164 static int __init noalign_setup(char *__unused)
166 cr_alignment &= ~CR_A;
167 cr_no_alignment &= ~CR_A;
168 set_cr(cr_alignment);
171 __setup("noalign", noalign_setup);
174 void adjust_cr(unsigned long mask, unsigned long set)
182 local_irq_save(flags);
184 cr_no_alignment = (cr_no_alignment & ~mask) | set;
185 cr_alignment = (cr_alignment & ~mask) | set;
187 set_cr((get_cr() & ~mask) | set);
189 local_irq_restore(flags);
193 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
194 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
196 static struct mem_type mem_types[] = {
197 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
198 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
200 .prot_l1 = PMD_TYPE_TABLE,
201 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
204 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
205 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
206 .prot_l1 = PMD_TYPE_TABLE,
207 .prot_sect = PROT_SECT_DEVICE,
210 [MT_DEVICE_CACHED] = { /* ioremap_cached */
211 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
212 .prot_l1 = PMD_TYPE_TABLE,
213 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
216 [MT_DEVICE_WC] = { /* ioremap_wc */
217 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
218 .prot_l1 = PMD_TYPE_TABLE,
219 .prot_sect = PROT_SECT_DEVICE,
223 .prot_pte = PROT_PTE_DEVICE,
224 .prot_l1 = PMD_TYPE_TABLE,
225 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
229 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
230 .domain = DOMAIN_KERNEL,
233 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
234 .domain = DOMAIN_KERNEL,
237 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
239 .prot_l1 = PMD_TYPE_TABLE,
240 .domain = DOMAIN_USER,
242 [MT_HIGH_VECTORS] = {
243 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
244 L_PTE_USER | L_PTE_RDONLY,
245 .prot_l1 = PMD_TYPE_TABLE,
246 .domain = DOMAIN_USER,
249 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
250 .prot_l1 = PMD_TYPE_TABLE,
251 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
252 .domain = DOMAIN_KERNEL,
255 .prot_sect = PMD_TYPE_SECT,
256 .domain = DOMAIN_KERNEL,
258 [MT_MEMORY_NONCACHED] = {
259 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
261 .prot_l1 = PMD_TYPE_TABLE,
262 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
263 .domain = DOMAIN_KERNEL,
266 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
268 .prot_l1 = PMD_TYPE_TABLE,
269 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
270 .domain = DOMAIN_KERNEL,
273 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
274 .prot_l1 = PMD_TYPE_TABLE,
275 .domain = DOMAIN_KERNEL,
278 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
280 .prot_l1 = PMD_TYPE_TABLE,
281 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
282 PMD_SECT_UNCACHED | PMD_SECT_XN,
283 .domain = DOMAIN_KERNEL,
287 const struct mem_type *get_mem_type(unsigned int type)
289 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
291 EXPORT_SYMBOL(get_mem_type);
294 * Adjust the PMD section entries according to the CPU in use.
296 static void __init build_mem_type_table(void)
298 struct cachepolicy *cp;
299 unsigned int cr = get_cr();
300 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
301 int cpu_arch = cpu_architecture();
304 if (cpu_arch < CPU_ARCH_ARMv6) {
305 #if defined(CONFIG_CPU_DCACHE_DISABLE)
306 if (cachepolicy > CPOLICY_BUFFERED)
307 cachepolicy = CPOLICY_BUFFERED;
308 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
309 if (cachepolicy > CPOLICY_WRITETHROUGH)
310 cachepolicy = CPOLICY_WRITETHROUGH;
313 if (cpu_arch < CPU_ARCH_ARMv5) {
314 if (cachepolicy >= CPOLICY_WRITEALLOC)
315 cachepolicy = CPOLICY_WRITEBACK;
319 cachepolicy = CPOLICY_WRITEALLOC;
322 * Strip out features not present on earlier architectures.
323 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
324 * without extended page tables don't have the 'Shared' bit.
326 if (cpu_arch < CPU_ARCH_ARMv5)
327 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
328 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
329 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
330 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
331 mem_types[i].prot_sect &= ~PMD_SECT_S;
334 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
335 * "update-able on write" bit on ARM610). However, Xscale and
336 * Xscale3 require this bit to be cleared.
338 if (cpu_is_xscale() || cpu_is_xsc3()) {
339 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
340 mem_types[i].prot_sect &= ~PMD_BIT4;
341 mem_types[i].prot_l1 &= ~PMD_BIT4;
343 } else if (cpu_arch < CPU_ARCH_ARMv6) {
344 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
345 if (mem_types[i].prot_l1)
346 mem_types[i].prot_l1 |= PMD_BIT4;
347 if (mem_types[i].prot_sect)
348 mem_types[i].prot_sect |= PMD_BIT4;
353 * Mark the device areas according to the CPU/architecture.
355 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
356 if (!cpu_is_xsc3()) {
358 * Mark device regions on ARMv6+ as execute-never
359 * to prevent speculative instruction fetches.
361 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
362 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
363 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
364 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
366 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
368 * For ARMv7 with TEX remapping,
369 * - shared device is SXCB=1100
370 * - nonshared device is SXCB=0100
371 * - write combine device mem is SXCB=0001
372 * (Uncached Normal memory)
374 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
375 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
376 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
377 } else if (cpu_is_xsc3()) {
380 * - shared device is TEXCB=00101
381 * - nonshared device is TEXCB=01000
382 * - write combine device mem is TEXCB=00100
383 * (Inner/Outer Uncacheable in xsc3 parlance)
385 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
386 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
387 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
390 * For ARMv6 and ARMv7 without TEX remapping,
391 * - shared device is TEXCB=00001
392 * - nonshared device is TEXCB=01000
393 * - write combine device mem is TEXCB=00100
394 * (Uncached Normal in ARMv6 parlance).
396 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
397 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
398 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
402 * On others, write combining is "Uncached/Buffered"
404 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
408 * Now deal with the memory-type mappings
410 cp = &cache_policies[cachepolicy];
411 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
414 * Only use write-through for non-SMP systems
416 if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
417 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
420 * Enable CPU-specific coherency if supported.
421 * (Only available on XSC3 at the moment.)
423 if (arch_is_coherent() && cpu_is_xsc3()) {
424 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
425 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
426 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
427 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
430 * ARMv6 and above have extended page tables.
432 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
434 * Mark cache clean areas and XIP ROM read only
435 * from SVC mode and no access from userspace.
437 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
438 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
439 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
443 * Mark memory with the "shared" attribute
446 user_pgprot |= L_PTE_SHARED;
447 kern_pgprot |= L_PTE_SHARED;
448 vecs_pgprot |= L_PTE_SHARED;
449 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
450 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
451 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
452 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
453 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
454 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
455 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
456 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
461 * Non-cacheable Normal - intended for memory areas that must
462 * not cause dirty cache line writebacks when used
464 if (cpu_arch >= CPU_ARCH_ARMv6) {
465 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
466 /* Non-cacheable Normal is XCB = 001 */
467 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
470 /* For both ARMv6 and non-TEX-remapping ARMv7 */
471 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
475 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
478 for (i = 0; i < 16; i++) {
479 unsigned long v = pgprot_val(protection_map[i]);
480 protection_map[i] = __pgprot(v | user_pgprot);
483 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
484 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
486 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
487 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
488 L_PTE_DIRTY | kern_pgprot);
490 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
491 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
492 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
493 mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
494 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
495 mem_types[MT_ROM].prot_sect |= cp->pmd;
499 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
503 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
506 printk("Memory policy: ECC %sabled, Data cache %s\n",
507 ecc_mask ? "en" : "dis", cp->policy);
509 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
510 struct mem_type *t = &mem_types[i];
512 t->prot_l1 |= PMD_DOMAIN(t->domain);
514 t->prot_sect |= PMD_DOMAIN(t->domain);
518 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
519 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
520 unsigned long size, pgprot_t vma_prot)
523 return pgprot_noncached(vma_prot);
524 else if (file->f_flags & O_SYNC)
525 return pgprot_writecombine(vma_prot);
528 EXPORT_SYMBOL(phys_mem_access_prot);
531 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
533 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
535 void *ptr = __va(memblock_alloc(sz, align));
540 static void __init *early_alloc(unsigned long sz)
542 return early_alloc_aligned(sz, sz);
545 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
547 if (pmd_none(*pmd)) {
548 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
549 __pmd_populate(pmd, __pa(pte), prot);
551 BUG_ON(pmd_bad(*pmd));
552 return pte_offset_kernel(pmd, addr);
555 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
556 unsigned long end, unsigned long pfn,
557 const struct mem_type *type)
559 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
561 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
563 } while (pte++, addr += PAGE_SIZE, addr != end);
566 static void __init alloc_init_section(pud_t *pud, unsigned long addr,
567 unsigned long end, phys_addr_t phys,
568 const struct mem_type *type)
570 pmd_t *pmd = pmd_offset(pud, addr);
573 * Try a section mapping - end, addr and phys must all be aligned
574 * to a section boundary. Note that PMDs refer to the individual
575 * L1 entries, whereas PGDs refer to a group of L1 entries making
576 * up one logical pointer to an L2 table.
578 if (((addr | end | phys) & ~SECTION_MASK) == 0) {
581 if (addr & SECTION_SIZE)
585 *pmd = __pmd(phys | type->prot_sect);
586 phys += SECTION_SIZE;
587 } while (pmd++, addr += SECTION_SIZE, addr != end);
592 * No need to loop; pte's aren't interested in the
593 * individual L1 entries.
595 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
599 static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
600 unsigned long phys, const struct mem_type *type)
602 pud_t *pud = pud_offset(pgd, addr);
606 next = pud_addr_end(addr, end);
607 alloc_init_section(pud, addr, next, phys, type);
609 } while (pud++, addr = next, addr != end);
612 static void __init create_36bit_mapping(struct map_desc *md,
613 const struct mem_type *type)
615 unsigned long addr, length, end;
620 phys = __pfn_to_phys(md->pfn);
621 length = PAGE_ALIGN(md->length);
623 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
624 printk(KERN_ERR "MM: CPU does not support supersection "
625 "mapping for 0x%08llx at 0x%08lx\n",
626 (long long)__pfn_to_phys((u64)md->pfn), addr);
630 /* N.B. ARMv6 supersections are only defined to work with domain 0.
631 * Since domain assignments can in fact be arbitrary, the
632 * 'domain == 0' check below is required to insure that ARMv6
633 * supersections are only allocated for domain 0 regardless
634 * of the actual domain assignments in use.
637 printk(KERN_ERR "MM: invalid domain in supersection "
638 "mapping for 0x%08llx at 0x%08lx\n",
639 (long long)__pfn_to_phys((u64)md->pfn), addr);
643 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
644 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
645 " at 0x%08lx invalid alignment\n",
646 (long long)__pfn_to_phys((u64)md->pfn), addr);
651 * Shift bits [35:32] of address into bits [23:20] of PMD
654 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
656 pgd = pgd_offset_k(addr);
659 pud_t *pud = pud_offset(pgd, addr);
660 pmd_t *pmd = pmd_offset(pud, addr);
663 for (i = 0; i < 16; i++)
664 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
666 addr += SUPERSECTION_SIZE;
667 phys += SUPERSECTION_SIZE;
668 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
669 } while (addr != end);
673 * Create the page directory entries and any necessary
674 * page tables for the mapping specified by `md'. We
675 * are able to cope here with varying sizes and address
676 * offsets, and we take full advantage of sections and
679 static void __init create_mapping(struct map_desc *md)
681 unsigned long addr, length, end;
683 const struct mem_type *type;
686 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
687 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
688 " at 0x%08lx in user region\n",
689 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
693 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
694 md->virtual >= PAGE_OFFSET &&
695 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
696 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
697 " at 0x%08lx out of vmalloc space\n",
698 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
701 type = &mem_types[md->type];
704 * Catch 36-bit addresses
706 if (md->pfn >= 0x100000) {
707 create_36bit_mapping(md, type);
711 addr = md->virtual & PAGE_MASK;
712 phys = __pfn_to_phys(md->pfn);
713 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
715 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
716 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
717 "be mapped using pages, ignoring.\n",
718 (long long)__pfn_to_phys(md->pfn), addr);
722 pgd = pgd_offset_k(addr);
725 unsigned long next = pgd_addr_end(addr, end);
727 alloc_init_pud(pgd, addr, next, phys, type);
731 } while (pgd++, addr != end);
735 * Create the architecture specific mappings
737 void __init iotable_init(struct map_desc *io_desc, int nr)
740 struct vm_struct *vm;
745 vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm));
747 for (md = io_desc; nr; md++, nr--) {
749 vm->addr = (void *)(md->virtual & PAGE_MASK);
750 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
751 vm->phys_addr = __pfn_to_phys(md->pfn);
752 vm->flags = VM_IOREMAP;
753 vm->caller = iotable_init;
754 vm_area_add_early(vm++);
758 static void * __initdata vmalloc_min =
759 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
762 * vmalloc=size forces the vmalloc area to be exactly 'size'
763 * bytes. This can be used to increase (or decrease) the vmalloc
764 * area - the default is 240m.
766 static int __init early_vmalloc(char *arg)
768 unsigned long vmalloc_reserve = memparse(arg, NULL);
770 if (vmalloc_reserve < SZ_16M) {
771 vmalloc_reserve = SZ_16M;
773 "vmalloc area too small, limiting to %luMB\n",
774 vmalloc_reserve >> 20);
777 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
778 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
780 "vmalloc area is too big, limiting to %luMB\n",
781 vmalloc_reserve >> 20);
784 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
787 early_param("vmalloc", early_vmalloc);
789 static phys_addr_t lowmem_limit __initdata = 0;
791 void __init sanity_check_meminfo(void)
793 int i, j, highmem = 0;
795 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
796 struct membank *bank = &meminfo.bank[j];
797 *bank = meminfo.bank[i];
799 #ifdef CONFIG_HIGHMEM
800 if (__va(bank->start) >= vmalloc_min ||
801 __va(bank->start) < (void *)PAGE_OFFSET)
804 bank->highmem = highmem;
807 * Split those memory banks which are partially overlapping
808 * the vmalloc area greatly simplifying things later.
810 if (__va(bank->start) < vmalloc_min &&
811 bank->size > vmalloc_min - __va(bank->start)) {
812 if (meminfo.nr_banks >= NR_BANKS) {
813 printk(KERN_CRIT "NR_BANKS too low, "
814 "ignoring high memory\n");
816 memmove(bank + 1, bank,
817 (meminfo.nr_banks - i) * sizeof(*bank));
820 bank[1].size -= vmalloc_min - __va(bank->start);
821 bank[1].start = __pa(vmalloc_min - 1) + 1;
822 bank[1].highmem = highmem = 1;
825 bank->size = vmalloc_min - __va(bank->start);
828 bank->highmem = highmem;
831 * Check whether this memory bank would entirely overlap
834 if (__va(bank->start) >= vmalloc_min ||
835 __va(bank->start) < (void *)PAGE_OFFSET) {
836 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
837 "(vmalloc region overlap).\n",
838 (unsigned long long)bank->start,
839 (unsigned long long)bank->start + bank->size - 1);
844 * Check whether this memory bank would partially overlap
847 if (__va(bank->start + bank->size) > vmalloc_min ||
848 __va(bank->start + bank->size) < __va(bank->start)) {
849 unsigned long newsize = vmalloc_min - __va(bank->start);
850 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
851 "to -%.8llx (vmalloc region overlap).\n",
852 (unsigned long long)bank->start,
853 (unsigned long long)bank->start + bank->size - 1,
854 (unsigned long long)bank->start + newsize - 1);
855 bank->size = newsize;
858 if (!bank->highmem && bank->start + bank->size > lowmem_limit)
859 lowmem_limit = bank->start + bank->size;
863 #ifdef CONFIG_HIGHMEM
865 const char *reason = NULL;
867 if (cache_is_vipt_aliasing()) {
869 * Interactions between kmap and other mappings
870 * make highmem support with aliasing VIPT caches
873 reason = "with VIPT aliasing cache";
876 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
878 while (j > 0 && meminfo.bank[j - 1].highmem)
883 meminfo.nr_banks = j;
884 high_memory = __va(lowmem_limit - 1) + 1;
885 memblock_set_current_limit(lowmem_limit);
888 static inline void prepare_page_table(void)
894 * Clear out all the mappings below the kernel image.
896 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
897 pmd_clear(pmd_off_k(addr));
899 #ifdef CONFIG_XIP_KERNEL
900 /* The XIP kernel is mapped in the module area -- skip over it */
901 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
903 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
904 pmd_clear(pmd_off_k(addr));
907 * Find the end of the first block of lowmem.
909 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
910 if (end >= lowmem_limit)
914 * Clear out all the kernel space mappings, except for the first
915 * memory bank, up to the vmalloc region.
917 for (addr = __phys_to_virt(end);
918 addr < VMALLOC_START; addr += PMD_SIZE)
919 pmd_clear(pmd_off_k(addr));
922 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
925 * Reserve the special regions of memory
927 void __init arm_mm_memblock_reserve(void)
930 * Reserve the page tables. These are already in use,
931 * and can only be in node 0.
933 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
937 * Because of the SA1111 DMA bug, we want to preserve our
938 * precious DMA-able memory...
940 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
945 * Set up the device mappings. Since we clear out the page tables for all
946 * mappings above VMALLOC_START, we will remove any debug device mappings.
947 * This means you have to be careful how you debug this function, or any
948 * called function. This means you can't use any function or debugging
949 * method which may touch any device, otherwise the kernel _will_ crash.
951 static void __init devicemaps_init(struct machine_desc *mdesc)
957 * Allocate the vector page early.
959 vectors_page = early_alloc(PAGE_SIZE);
961 for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
962 pmd_clear(pmd_off_k(addr));
965 * Map the kernel if it is XIP.
966 * It is always first in the modulearea.
968 #ifdef CONFIG_XIP_KERNEL
969 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
970 map.virtual = MODULES_VADDR;
971 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
973 create_mapping(&map);
977 * Map the cache flushing regions.
980 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
981 map.virtual = FLUSH_BASE;
983 map.type = MT_CACHECLEAN;
984 create_mapping(&map);
986 #ifdef FLUSH_BASE_MINICACHE
987 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
988 map.virtual = FLUSH_BASE_MINICACHE;
990 map.type = MT_MINICLEAN;
991 create_mapping(&map);
995 * Create a mapping for the machine vectors at the high-vectors
996 * location (0xffff0000). If we aren't using high-vectors, also
997 * create a mapping at the low-vectors virtual address.
999 map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
1000 map.virtual = 0xffff0000;
1001 map.length = PAGE_SIZE;
1002 map.type = MT_HIGH_VECTORS;
1003 create_mapping(&map);
1005 if (!vectors_high()) {
1007 map.type = MT_LOW_VECTORS;
1008 create_mapping(&map);
1012 * Ask the machine support to map in the statically mapped devices.
1018 * Finally flush the caches and tlb to ensure that we're in a
1019 * consistent state wrt the writebuffer. This also ensures that
1020 * any write-allocated cache lines in the vector page are written
1021 * back. After this point, we can start to touch devices again.
1023 local_flush_tlb_all();
1027 static void __init kmap_init(void)
1029 #ifdef CONFIG_HIGHMEM
1030 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1031 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1035 static void __init map_lowmem(void)
1037 struct memblock_region *reg;
1039 /* Map all the lowmem memory banks. */
1040 for_each_memblock(memory, reg) {
1041 phys_addr_t start = reg->base;
1042 phys_addr_t end = start + reg->size;
1043 struct map_desc map;
1045 if (end > lowmem_limit)
1050 map.pfn = __phys_to_pfn(start);
1051 map.virtual = __phys_to_virt(start);
1052 map.length = end - start;
1053 map.type = MT_MEMORY;
1055 create_mapping(&map);
1060 * paging_init() sets up the page tables, initialises the zone memory
1061 * maps, and sets up the zero page, bad page and bad page tables.
1063 void __init paging_init(struct machine_desc *mdesc)
1067 memblock_set_current_limit(lowmem_limit);
1069 build_mem_type_table();
1070 prepare_page_table();
1072 devicemaps_init(mdesc);
1075 top_pmd = pmd_off_k(0xffff0000);
1077 /* allocate the zero page. */
1078 zero_page = early_alloc(PAGE_SIZE);
1082 empty_zero_page = virt_to_page(zero_page);
1083 __flush_dcache_page(NULL, empty_zero_page);