2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sizes.h>
22 #include <asm/cputype.h>
23 #include <asm/sections.h>
24 #include <asm/cachetype.h>
25 #include <asm/sections.h>
26 #include <asm/setup.h>
27 #include <asm/smp_plat.h>
29 #include <asm/highmem.h>
30 #include <asm/system_info.h>
31 #include <asm/traps.h>
32 #include <asm/procinfo.h>
33 #include <asm/memory.h>
35 #include <asm/mach/arch.h>
36 #include <asm/mach/map.h>
37 #include <asm/mach/pci.h>
43 * empty_zero_page is a special page that is used for
44 * zero-initialized data and COW.
46 struct page *empty_zero_page;
47 EXPORT_SYMBOL(empty_zero_page);
50 * The pmd table for the upper-most set of pages.
54 #define CPOLICY_UNCACHED 0
55 #define CPOLICY_BUFFERED 1
56 #define CPOLICY_WRITETHROUGH 2
57 #define CPOLICY_WRITEBACK 3
58 #define CPOLICY_WRITEALLOC 4
60 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
61 static unsigned int ecc_mask __initdata = 0;
63 pgprot_t pgprot_kernel;
64 pgprot_t pgprot_hyp_device;
66 pgprot_t pgprot_s2_device;
68 EXPORT_SYMBOL(pgprot_user);
69 EXPORT_SYMBOL(pgprot_kernel);
72 const char policy[16];
79 #ifdef CONFIG_ARM_LPAE
80 #define s2_policy(policy) policy
82 #define s2_policy(policy) 0
85 static struct cachepolicy cache_policies[] __initdata = {
89 .pmd = PMD_SECT_UNCACHED,
90 .pte = L_PTE_MT_UNCACHED,
91 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
95 .pmd = PMD_SECT_BUFFERED,
96 .pte = L_PTE_MT_BUFFERABLE,
97 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
99 .policy = "writethrough",
102 .pte = L_PTE_MT_WRITETHROUGH,
103 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
105 .policy = "writeback",
108 .pte = L_PTE_MT_WRITEBACK,
109 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
111 .policy = "writealloc",
113 .pmd = PMD_SECT_WBWA,
114 .pte = L_PTE_MT_WRITEALLOC,
115 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
119 #ifdef CONFIG_CPU_CP15
121 * These are useful for identifying cache coherency
122 * problems by allowing the cache or the cache and
123 * writebuffer to be turned off. (Note: the write
124 * buffer should not be on and the cache off).
126 static int __init early_cachepolicy(char *p)
128 unsigned long cr = get_cr();
131 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
132 int len = strlen(cache_policies[i].policy);
134 if (memcmp(p, cache_policies[i].policy, len) == 0) {
136 cr = __clear_cr(cache_policies[i].cr_mask);
140 if (i == ARRAY_SIZE(cache_policies))
141 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
143 * This restriction is partly to do with the way we boot; it is
144 * unpredictable to have memory mapped using two different sets of
145 * memory attributes (shared, type, and cache attribs). We can not
146 * change these attributes once the initial assembly has setup the
149 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
150 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
151 cachepolicy = CPOLICY_WRITEBACK;
157 early_param("cachepolicy", early_cachepolicy);
159 static int __init early_nocache(char *__unused)
161 char *p = "buffered";
162 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
163 early_cachepolicy(p);
166 early_param("nocache", early_nocache);
168 static int __init early_nowrite(char *__unused)
170 char *p = "uncached";
171 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
172 early_cachepolicy(p);
175 early_param("nowb", early_nowrite);
177 #ifndef CONFIG_ARM_LPAE
178 static int __init early_ecc(char *p)
180 if (memcmp(p, "on", 2) == 0)
181 ecc_mask = PMD_PROTECTION;
182 else if (memcmp(p, "off", 3) == 0)
186 early_param("ecc", early_ecc);
189 static int __init noalign_setup(char *__unused)
191 set_cr(__clear_cr(CR_A));
194 __setup("noalign", noalign_setup);
197 void adjust_cr(unsigned long mask, unsigned long set)
205 local_irq_save(flags);
207 cr_no_alignment = (cr_no_alignment & ~mask) | set;
208 cr_alignment = (cr_alignment & ~mask) | set;
210 set_cr((get_cr() & ~mask) | set);
212 local_irq_restore(flags);
216 #else /* ifdef CONFIG_CPU_CP15 */
218 static int __init early_cachepolicy(char *p)
220 pr_warning("cachepolicy kernel parameter not supported without cp15\n");
222 early_param("cachepolicy", early_cachepolicy);
224 static int __init noalign_setup(char *__unused)
226 pr_warning("noalign kernel parameter not supported without cp15\n");
228 __setup("noalign", noalign_setup);
230 #endif /* ifdef CONFIG_CPU_CP15 / else */
232 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
233 #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
234 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
236 static struct mem_type mem_types[] = {
237 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
238 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
240 .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
241 s2_policy(L_PTE_S2_MT_DEV_SHARED) |
243 .prot_l1 = PMD_TYPE_TABLE,
244 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
247 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
248 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
249 .prot_l1 = PMD_TYPE_TABLE,
250 .prot_sect = PROT_SECT_DEVICE,
253 [MT_DEVICE_CACHED] = { /* ioremap_cached */
254 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
255 .prot_l1 = PMD_TYPE_TABLE,
256 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
259 [MT_DEVICE_WC] = { /* ioremap_wc */
260 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
261 .prot_l1 = PMD_TYPE_TABLE,
262 .prot_sect = PROT_SECT_DEVICE,
266 .prot_pte = PROT_PTE_DEVICE,
267 .prot_l1 = PMD_TYPE_TABLE,
268 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
272 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
273 .domain = DOMAIN_KERNEL,
275 #ifndef CONFIG_ARM_LPAE
277 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
278 .domain = DOMAIN_KERNEL,
282 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
284 .prot_l1 = PMD_TYPE_TABLE,
285 .domain = DOMAIN_USER,
287 [MT_HIGH_VECTORS] = {
288 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
289 L_PTE_USER | L_PTE_RDONLY,
290 .prot_l1 = PMD_TYPE_TABLE,
291 .domain = DOMAIN_USER,
294 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
295 .prot_l1 = PMD_TYPE_TABLE,
296 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
297 .domain = DOMAIN_KERNEL,
300 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
302 .prot_l1 = PMD_TYPE_TABLE,
303 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
304 .domain = DOMAIN_KERNEL,
307 .prot_sect = PMD_TYPE_SECT,
308 .domain = DOMAIN_KERNEL,
310 [MT_MEMORY_RWX_NONCACHED] = {
311 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
313 .prot_l1 = PMD_TYPE_TABLE,
314 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
315 .domain = DOMAIN_KERNEL,
317 [MT_MEMORY_RW_DTCM] = {
318 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
320 .prot_l1 = PMD_TYPE_TABLE,
321 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
322 .domain = DOMAIN_KERNEL,
324 [MT_MEMORY_RWX_ITCM] = {
325 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
326 .prot_l1 = PMD_TYPE_TABLE,
327 .domain = DOMAIN_KERNEL,
329 [MT_MEMORY_RW_SO] = {
330 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
331 L_PTE_MT_UNCACHED | L_PTE_XN,
332 .prot_l1 = PMD_TYPE_TABLE,
333 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
334 PMD_SECT_UNCACHED | PMD_SECT_XN,
335 .domain = DOMAIN_KERNEL,
337 [MT_MEMORY_DMA_READY] = {
338 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
340 .prot_l1 = PMD_TYPE_TABLE,
341 .domain = DOMAIN_KERNEL,
345 const struct mem_type *get_mem_type(unsigned int type)
347 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
349 EXPORT_SYMBOL(get_mem_type);
351 #define PTE_SET_FN(_name, pteop) \
352 static int pte_set_##_name(pte_t *ptep, pgtable_t token, unsigned long addr, \
355 pte_t pte = pteop(*ptep); \
357 set_pte_ext(ptep, pte, 0); \
361 #define SET_MEMORY_FN(_name, callback) \
362 int set_memory_##_name(unsigned long addr, int numpages) \
364 unsigned long start = addr; \
365 unsigned long size = PAGE_SIZE*numpages; \
366 unsigned end = start + size; \
368 if (start < MODULES_VADDR || start >= MODULES_END) \
371 if (end < MODULES_VADDR || end >= MODULES_END) \
374 apply_to_page_range(&init_mm, start, size, callback, NULL); \
375 flush_tlb_kernel_range(start, end); \
379 PTE_SET_FN(ro, pte_wrprotect)
380 PTE_SET_FN(rw, pte_mkwrite)
381 PTE_SET_FN(x, pte_mkexec)
382 PTE_SET_FN(nx, pte_mknexec)
384 SET_MEMORY_FN(ro, pte_set_ro)
385 SET_MEMORY_FN(rw, pte_set_rw)
386 SET_MEMORY_FN(x, pte_set_x)
387 SET_MEMORY_FN(nx, pte_set_nx)
390 * Adjust the PMD section entries according to the CPU in use.
392 static void __init build_mem_type_table(void)
394 struct cachepolicy *cp;
395 unsigned int cr = get_cr();
396 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
397 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
398 int cpu_arch = cpu_architecture();
401 if (cpu_arch < CPU_ARCH_ARMv6) {
402 #if defined(CONFIG_CPU_DCACHE_DISABLE)
403 if (cachepolicy > CPOLICY_BUFFERED)
404 cachepolicy = CPOLICY_BUFFERED;
405 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
406 if (cachepolicy > CPOLICY_WRITETHROUGH)
407 cachepolicy = CPOLICY_WRITETHROUGH;
410 if (cpu_arch < CPU_ARCH_ARMv5) {
411 if (cachepolicy >= CPOLICY_WRITEALLOC)
412 cachepolicy = CPOLICY_WRITEBACK;
416 cachepolicy = CPOLICY_WRITEALLOC;
419 * Strip out features not present on earlier architectures.
420 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
421 * without extended page tables don't have the 'Shared' bit.
423 if (cpu_arch < CPU_ARCH_ARMv5)
424 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
425 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
426 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
427 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
428 mem_types[i].prot_sect &= ~PMD_SECT_S;
431 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
432 * "update-able on write" bit on ARM610). However, Xscale and
433 * Xscale3 require this bit to be cleared.
435 if (cpu_is_xscale() || cpu_is_xsc3()) {
436 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
437 mem_types[i].prot_sect &= ~PMD_BIT4;
438 mem_types[i].prot_l1 &= ~PMD_BIT4;
440 } else if (cpu_arch < CPU_ARCH_ARMv6) {
441 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
442 if (mem_types[i].prot_l1)
443 mem_types[i].prot_l1 |= PMD_BIT4;
444 if (mem_types[i].prot_sect)
445 mem_types[i].prot_sect |= PMD_BIT4;
450 * Mark the device areas according to the CPU/architecture.
452 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
453 if (!cpu_is_xsc3()) {
455 * Mark device regions on ARMv6+ as execute-never
456 * to prevent speculative instruction fetches.
458 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
459 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
460 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
461 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
463 /* Also setup NX memory mapping */
464 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
466 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
468 * For ARMv7 with TEX remapping,
469 * - shared device is SXCB=1100
470 * - nonshared device is SXCB=0100
471 * - write combine device mem is SXCB=0001
472 * (Uncached Normal memory)
474 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
475 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
476 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
477 } else if (cpu_is_xsc3()) {
480 * - shared device is TEXCB=00101
481 * - nonshared device is TEXCB=01000
482 * - write combine device mem is TEXCB=00100
483 * (Inner/Outer Uncacheable in xsc3 parlance)
485 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
486 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
487 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
490 * For ARMv6 and ARMv7 without TEX remapping,
491 * - shared device is TEXCB=00001
492 * - nonshared device is TEXCB=01000
493 * - write combine device mem is TEXCB=00100
494 * (Uncached Normal in ARMv6 parlance).
496 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
497 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
498 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
502 * On others, write combining is "Uncached/Buffered"
504 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
508 * Now deal with the memory-type mappings
510 cp = &cache_policies[cachepolicy];
511 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
512 s2_pgprot = cp->pte_s2;
513 hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
514 s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
517 * We don't use domains on ARMv6 (since this causes problems with
518 * v6/v7 kernels), so we must use a separate memory type for user
519 * r/o, kernel r/w to map the vectors page.
521 #ifndef CONFIG_ARM_LPAE
522 if (cpu_arch == CPU_ARCH_ARMv6)
523 vecs_pgprot |= L_PTE_MT_VECTORS;
527 * ARMv6 and above have extended page tables.
529 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
530 #ifndef CONFIG_ARM_LPAE
532 * Mark cache clean areas and XIP ROM read only
533 * from SVC mode and no access from userspace.
535 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
536 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
537 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
542 * Mark memory with the "shared" attribute
545 user_pgprot |= L_PTE_SHARED;
546 kern_pgprot |= L_PTE_SHARED;
547 vecs_pgprot |= L_PTE_SHARED;
548 s2_pgprot |= L_PTE_SHARED;
549 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
550 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
551 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
552 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
553 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
554 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
555 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
556 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
557 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
558 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
559 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
564 * Non-cacheable Normal - intended for memory areas that must
565 * not cause dirty cache line writebacks when used
567 if (cpu_arch >= CPU_ARCH_ARMv6) {
568 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
569 /* Non-cacheable Normal is XCB = 001 */
570 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
573 /* For both ARMv6 and non-TEX-remapping ARMv7 */
574 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
578 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
581 #ifdef CONFIG_ARM_LPAE
583 * Do not generate access flag faults for the kernel mappings.
585 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
586 mem_types[i].prot_pte |= PTE_EXT_AF;
587 if (mem_types[i].prot_sect)
588 mem_types[i].prot_sect |= PMD_SECT_AF;
590 kern_pgprot |= PTE_EXT_AF;
591 vecs_pgprot |= PTE_EXT_AF;
594 for (i = 0; i < 16; i++) {
595 pteval_t v = pgprot_val(protection_map[i]);
596 protection_map[i] = __pgprot(v | user_pgprot);
599 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
600 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
602 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
603 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
604 L_PTE_DIRTY | kern_pgprot);
605 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
606 pgprot_s2_device = __pgprot(s2_device_pgprot);
607 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
609 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
610 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
611 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
612 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
613 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
614 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
615 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
616 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
617 mem_types[MT_ROM].prot_sect |= cp->pmd;
621 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
625 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
628 pr_info("Memory policy: %sData cache %s\n",
629 ecc_mask ? "ECC enabled, " : "", cp->policy);
631 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
632 struct mem_type *t = &mem_types[i];
634 t->prot_l1 |= PMD_DOMAIN(t->domain);
636 t->prot_sect |= PMD_DOMAIN(t->domain);
640 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
641 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
642 unsigned long size, pgprot_t vma_prot)
645 return pgprot_noncached(vma_prot);
646 else if (file->f_flags & O_SYNC)
647 return pgprot_writecombine(vma_prot);
650 EXPORT_SYMBOL(phys_mem_access_prot);
653 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
655 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
657 void *ptr = __va(memblock_alloc(sz, align));
662 static void __init *early_alloc(unsigned long sz)
664 return early_alloc_aligned(sz, sz);
667 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
669 if (pmd_none(*pmd)) {
670 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
671 __pmd_populate(pmd, __pa(pte), prot);
673 BUG_ON(pmd_bad(*pmd));
674 return pte_offset_kernel(pmd, addr);
677 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
678 unsigned long end, unsigned long pfn,
679 const struct mem_type *type)
681 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
683 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
685 } while (pte++, addr += PAGE_SIZE, addr != end);
688 static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
689 unsigned long end, phys_addr_t phys,
690 const struct mem_type *type)
694 #ifndef CONFIG_ARM_LPAE
696 * In classic MMU format, puds and pmds are folded in to
697 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
698 * group of L1 entries making up one logical pointer to
699 * an L2 table (2MB), where as PMDs refer to the individual
700 * L1 entries (1MB). Hence increment to get the correct
701 * offset for odd 1MB sections.
702 * (See arch/arm/include/asm/pgtable-2level.h)
704 if (addr & SECTION_SIZE)
708 *pmd = __pmd(phys | type->prot_sect);
709 phys += SECTION_SIZE;
710 } while (pmd++, addr += SECTION_SIZE, addr != end);
715 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
716 unsigned long end, phys_addr_t phys,
717 const struct mem_type *type)
719 pmd_t *pmd = pmd_offset(pud, addr);
724 * With LPAE, we must loop over to map
725 * all the pmds for the given range.
727 next = pmd_addr_end(addr, end);
730 * Try a section mapping - addr, next and phys must all be
731 * aligned to a section boundary.
733 if (type->prot_sect &&
734 ((addr | next | phys) & ~SECTION_MASK) == 0) {
735 __map_init_section(pmd, addr, next, phys, type);
737 alloc_init_pte(pmd, addr, next,
738 __phys_to_pfn(phys), type);
743 } while (pmd++, addr = next, addr != end);
746 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
747 unsigned long end, phys_addr_t phys,
748 const struct mem_type *type)
750 pud_t *pud = pud_offset(pgd, addr);
754 next = pud_addr_end(addr, end);
755 alloc_init_pmd(pud, addr, next, phys, type);
757 } while (pud++, addr = next, addr != end);
760 #ifndef CONFIG_ARM_LPAE
761 static void __init create_36bit_mapping(struct map_desc *md,
762 const struct mem_type *type)
764 unsigned long addr, length, end;
769 phys = __pfn_to_phys(md->pfn);
770 length = PAGE_ALIGN(md->length);
772 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
773 printk(KERN_ERR "MM: CPU does not support supersection "
774 "mapping for 0x%08llx at 0x%08lx\n",
775 (long long)__pfn_to_phys((u64)md->pfn), addr);
779 /* N.B. ARMv6 supersections are only defined to work with domain 0.
780 * Since domain assignments can in fact be arbitrary, the
781 * 'domain == 0' check below is required to insure that ARMv6
782 * supersections are only allocated for domain 0 regardless
783 * of the actual domain assignments in use.
786 printk(KERN_ERR "MM: invalid domain in supersection "
787 "mapping for 0x%08llx at 0x%08lx\n",
788 (long long)__pfn_to_phys((u64)md->pfn), addr);
792 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
793 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
794 " at 0x%08lx invalid alignment\n",
795 (long long)__pfn_to_phys((u64)md->pfn), addr);
800 * Shift bits [35:32] of address into bits [23:20] of PMD
803 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
805 pgd = pgd_offset_k(addr);
808 pud_t *pud = pud_offset(pgd, addr);
809 pmd_t *pmd = pmd_offset(pud, addr);
812 for (i = 0; i < 16; i++)
813 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
815 addr += SUPERSECTION_SIZE;
816 phys += SUPERSECTION_SIZE;
817 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
818 } while (addr != end);
820 #endif /* !CONFIG_ARM_LPAE */
823 * Create the page directory entries and any necessary
824 * page tables for the mapping specified by `md'. We
825 * are able to cope here with varying sizes and address
826 * offsets, and we take full advantage of sections and
829 static void __init create_mapping(struct map_desc *md)
831 unsigned long addr, length, end;
833 const struct mem_type *type;
836 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
837 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
838 " at 0x%08lx in user region\n",
839 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
843 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
844 md->virtual >= PAGE_OFFSET &&
845 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
846 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
847 " at 0x%08lx out of vmalloc space\n",
848 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
851 type = &mem_types[md->type];
853 #ifndef CONFIG_ARM_LPAE
855 * Catch 36-bit addresses
857 if (md->pfn >= 0x100000) {
858 create_36bit_mapping(md, type);
863 addr = md->virtual & PAGE_MASK;
864 phys = __pfn_to_phys(md->pfn);
865 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
867 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
868 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
869 "be mapped using pages, ignoring.\n",
870 (long long)__pfn_to_phys(md->pfn), addr);
874 pgd = pgd_offset_k(addr);
877 unsigned long next = pgd_addr_end(addr, end);
879 alloc_init_pud(pgd, addr, next, phys, type);
883 } while (pgd++, addr != end);
887 * Create the architecture specific mappings
889 void __init iotable_init(struct map_desc *io_desc, int nr)
892 struct vm_struct *vm;
893 struct static_vm *svm;
898 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
900 for (md = io_desc; nr; md++, nr--) {
904 vm->addr = (void *)(md->virtual & PAGE_MASK);
905 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
906 vm->phys_addr = __pfn_to_phys(md->pfn);
907 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
908 vm->flags |= VM_ARM_MTYPE(md->type);
909 vm->caller = iotable_init;
910 add_static_vm_early(svm++);
914 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
917 struct vm_struct *vm;
918 struct static_vm *svm;
920 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
923 vm->addr = (void *)addr;
925 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
927 add_static_vm_early(svm);
930 #ifndef CONFIG_ARM_LPAE
933 * The Linux PMD is made of two consecutive section entries covering 2MB
934 * (see definition in include/asm/pgtable-2level.h). However a call to
935 * create_mapping() may optimize static mappings by using individual
936 * 1MB section mappings. This leaves the actual PMD potentially half
937 * initialized if the top or bottom section entry isn't used, leaving it
938 * open to problems if a subsequent ioremap() or vmalloc() tries to use
939 * the virtual space left free by that unused section entry.
941 * Let's avoid the issue by inserting dummy vm entries covering the unused
942 * PMD halves once the static mappings are in place.
945 static void __init pmd_empty_section_gap(unsigned long addr)
947 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
950 static void __init fill_pmd_gaps(void)
952 struct static_vm *svm;
953 struct vm_struct *vm;
954 unsigned long addr, next = 0;
957 list_for_each_entry(svm, &static_vmlist, list) {
959 addr = (unsigned long)vm->addr;
964 * Check if this vm starts on an odd section boundary.
965 * If so and the first section entry for this PMD is free
966 * then we block the corresponding virtual address.
968 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
969 pmd = pmd_off_k(addr);
971 pmd_empty_section_gap(addr & PMD_MASK);
975 * Then check if this vm ends on an odd section boundary.
976 * If so and the second section entry for this PMD is empty
977 * then we block the corresponding virtual address.
980 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
981 pmd = pmd_off_k(addr) + 1;
983 pmd_empty_section_gap(addr);
986 /* no need to look at any vm entry until we hit the next PMD */
987 next = (addr + PMD_SIZE - 1) & PMD_MASK;
992 #define fill_pmd_gaps() do { } while (0)
995 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
996 static void __init pci_reserve_io(void)
998 struct static_vm *svm;
1000 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1004 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1007 #define pci_reserve_io() do { } while (0)
1010 #ifdef CONFIG_DEBUG_LL
1011 void __init debug_ll_io_init(void)
1013 struct map_desc map;
1015 debug_ll_addr(&map.pfn, &map.virtual);
1016 if (!map.pfn || !map.virtual)
1018 map.pfn = __phys_to_pfn(map.pfn);
1019 map.virtual &= PAGE_MASK;
1020 map.length = PAGE_SIZE;
1021 map.type = MT_DEVICE;
1022 iotable_init(&map, 1);
1026 static void * __initdata vmalloc_min =
1027 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
1030 * vmalloc=size forces the vmalloc area to be exactly 'size'
1031 * bytes. This can be used to increase (or decrease) the vmalloc
1032 * area - the default is 240m.
1034 static int __init early_vmalloc(char *arg)
1036 unsigned long vmalloc_reserve = memparse(arg, NULL);
1038 if (vmalloc_reserve < SZ_16M) {
1039 vmalloc_reserve = SZ_16M;
1041 "vmalloc area too small, limiting to %luMB\n",
1042 vmalloc_reserve >> 20);
1045 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
1046 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
1048 "vmalloc area is too big, limiting to %luMB\n",
1049 vmalloc_reserve >> 20);
1052 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
1055 early_param("vmalloc", early_vmalloc);
1057 phys_addr_t arm_lowmem_limit __initdata = 0;
1059 void __init sanity_check_meminfo(void)
1061 phys_addr_t memblock_limit = 0;
1062 int i, j, highmem = 0;
1063 phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
1065 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
1066 struct membank *bank = &meminfo.bank[j];
1067 phys_addr_t size_limit;
1069 *bank = meminfo.bank[i];
1070 size_limit = bank->size;
1072 if (bank->start >= vmalloc_limit)
1075 size_limit = vmalloc_limit - bank->start;
1077 bank->highmem = highmem;
1079 #ifdef CONFIG_HIGHMEM
1081 * Split those memory banks which are partially overlapping
1082 * the vmalloc area greatly simplifying things later.
1084 if (!highmem && bank->size > size_limit) {
1085 if (meminfo.nr_banks >= NR_BANKS) {
1086 printk(KERN_CRIT "NR_BANKS too low, "
1087 "ignoring high memory\n");
1089 memmove(bank + 1, bank,
1090 (meminfo.nr_banks - i) * sizeof(*bank));
1093 bank[1].size -= size_limit;
1094 bank[1].start = vmalloc_limit;
1095 bank[1].highmem = highmem = 1;
1098 bank->size = size_limit;
1102 * Highmem banks not allowed with !CONFIG_HIGHMEM.
1105 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1106 "(!CONFIG_HIGHMEM).\n",
1107 (unsigned long long)bank->start,
1108 (unsigned long long)bank->start + bank->size - 1);
1113 * Check whether this memory bank would partially overlap
1116 if (bank->size > size_limit) {
1117 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
1118 "to -%.8llx (vmalloc region overlap).\n",
1119 (unsigned long long)bank->start,
1120 (unsigned long long)bank->start + bank->size - 1,
1121 (unsigned long long)bank->start + size_limit - 1);
1122 bank->size = size_limit;
1125 if (!bank->highmem) {
1126 phys_addr_t bank_end = bank->start + bank->size;
1128 if (bank_end > arm_lowmem_limit)
1129 arm_lowmem_limit = bank_end;
1132 * Find the first non-section-aligned page, and point
1133 * memblock_limit at it. This relies on rounding the
1134 * limit down to be section-aligned, which happens at
1135 * the end of this function.
1137 * With this algorithm, the start or end of almost any
1138 * bank can be non-section-aligned. The only exception
1139 * is that the start of the bank 0 must be section-
1140 * aligned, since otherwise memory would need to be
1141 * allocated when mapping the start of bank 0, which
1142 * occurs before any free memory is mapped.
1144 if (!memblock_limit) {
1145 if (!IS_ALIGNED(bank->start, SECTION_SIZE))
1146 memblock_limit = bank->start;
1147 else if (!IS_ALIGNED(bank_end, SECTION_SIZE))
1148 memblock_limit = bank_end;
1153 #ifdef CONFIG_HIGHMEM
1155 const char *reason = NULL;
1157 if (cache_is_vipt_aliasing()) {
1159 * Interactions between kmap and other mappings
1160 * make highmem support with aliasing VIPT caches
1163 reason = "with VIPT aliasing cache";
1166 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1168 while (j > 0 && meminfo.bank[j - 1].highmem)
1173 meminfo.nr_banks = j;
1174 high_memory = __va(arm_lowmem_limit - 1) + 1;
1177 * Round the memblock limit down to a section size. This
1178 * helps to ensure that we will allocate memory from the
1179 * last full section, which should be mapped.
1182 memblock_limit = round_down(memblock_limit, SECTION_SIZE);
1183 if (!memblock_limit)
1184 memblock_limit = arm_lowmem_limit;
1186 memblock_set_current_limit(memblock_limit);
1189 static inline void prepare_page_table(void)
1195 * Clear out all the mappings below the kernel image.
1197 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1198 pmd_clear(pmd_off_k(addr));
1200 #ifdef CONFIG_XIP_KERNEL
1201 /* The XIP kernel is mapped in the module area -- skip over it */
1202 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1204 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1205 pmd_clear(pmd_off_k(addr));
1208 * Find the end of the first block of lowmem.
1210 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1211 if (end >= arm_lowmem_limit)
1212 end = arm_lowmem_limit;
1215 * Clear out all the kernel space mappings, except for the first
1216 * memory bank, up to the vmalloc region.
1218 for (addr = __phys_to_virt(end);
1219 addr < VMALLOC_START; addr += PMD_SIZE)
1220 pmd_clear(pmd_off_k(addr));
1223 #ifdef CONFIG_ARM_LPAE
1224 /* the first page is reserved for pgd */
1225 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1226 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1228 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1232 * Reserve the special regions of memory
1234 void __init arm_mm_memblock_reserve(void)
1237 * Reserve the page tables. These are already in use,
1238 * and can only be in node 0.
1240 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1242 #ifdef CONFIG_SA1111
1244 * Because of the SA1111 DMA bug, we want to preserve our
1245 * precious DMA-able memory...
1247 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1252 * Set up the device mappings. Since we clear out the page tables for all
1253 * mappings above VMALLOC_START, we will remove any debug device mappings.
1254 * This means you have to be careful how you debug this function, or any
1255 * called function. This means you can't use any function or debugging
1256 * method which may touch any device, otherwise the kernel _will_ crash.
1258 static void __init devicemaps_init(const struct machine_desc *mdesc)
1260 struct map_desc map;
1265 * Allocate the vector page early.
1267 vectors = early_alloc(PAGE_SIZE * 2);
1269 early_trap_init(vectors);
1271 for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1272 pmd_clear(pmd_off_k(addr));
1275 * Map the kernel if it is XIP.
1276 * It is always first in the modulearea.
1278 #ifdef CONFIG_XIP_KERNEL
1279 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1280 map.virtual = MODULES_VADDR;
1281 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1283 create_mapping(&map);
1287 * Map the cache flushing regions.
1290 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1291 map.virtual = FLUSH_BASE;
1293 map.type = MT_CACHECLEAN;
1294 create_mapping(&map);
1296 #ifdef FLUSH_BASE_MINICACHE
1297 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1298 map.virtual = FLUSH_BASE_MINICACHE;
1300 map.type = MT_MINICLEAN;
1301 create_mapping(&map);
1305 * Create a mapping for the machine vectors at the high-vectors
1306 * location (0xffff0000). If we aren't using high-vectors, also
1307 * create a mapping at the low-vectors virtual address.
1309 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1310 map.virtual = 0xffff0000;
1311 map.length = PAGE_SIZE;
1312 #ifdef CONFIG_KUSER_HELPERS
1313 map.type = MT_HIGH_VECTORS;
1315 map.type = MT_LOW_VECTORS;
1317 create_mapping(&map);
1319 if (!vectors_high()) {
1321 map.length = PAGE_SIZE * 2;
1322 map.type = MT_LOW_VECTORS;
1323 create_mapping(&map);
1326 /* Now create a kernel read-only mapping */
1328 map.virtual = 0xffff0000 + PAGE_SIZE;
1329 map.length = PAGE_SIZE;
1330 map.type = MT_LOW_VECTORS;
1331 create_mapping(&map);
1334 * Ask the machine support to map in the statically mapped devices.
1342 /* Reserve fixed i/o space in VMALLOC region */
1346 * Finally flush the caches and tlb to ensure that we're in a
1347 * consistent state wrt the writebuffer. This also ensures that
1348 * any write-allocated cache lines in the vector page are written
1349 * back. After this point, we can start to touch devices again.
1351 local_flush_tlb_all();
1355 static void __init kmap_init(void)
1357 #ifdef CONFIG_HIGHMEM
1358 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1359 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1363 static void __init map_lowmem(void)
1365 struct memblock_region *reg;
1366 unsigned long kernel_x_start = round_down(__pa(_stext), SECTION_SIZE);
1367 unsigned long kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1369 /* Map all the lowmem memory banks. */
1370 for_each_memblock(memory, reg) {
1371 phys_addr_t start = reg->base;
1372 phys_addr_t end = start + reg->size;
1373 struct map_desc map;
1375 if (end > arm_lowmem_limit)
1376 end = arm_lowmem_limit;
1380 if (end < kernel_x_start || start >= kernel_x_end) {
1381 map.pfn = __phys_to_pfn(start);
1382 map.virtual = __phys_to_virt(start);
1383 map.length = end - start;
1384 map.type = MT_MEMORY_RWX;
1386 create_mapping(&map);
1388 /* This better cover the entire kernel */
1389 if (start < kernel_x_start) {
1390 map.pfn = __phys_to_pfn(start);
1391 map.virtual = __phys_to_virt(start);
1392 map.length = kernel_x_start - start;
1393 map.type = MT_MEMORY_RW;
1395 create_mapping(&map);
1398 map.pfn = __phys_to_pfn(kernel_x_start);
1399 map.virtual = __phys_to_virt(kernel_x_start);
1400 map.length = kernel_x_end - kernel_x_start;
1401 map.type = MT_MEMORY_RWX;
1403 create_mapping(&map);
1405 if (kernel_x_end < end) {
1406 map.pfn = __phys_to_pfn(kernel_x_end);
1407 map.virtual = __phys_to_virt(kernel_x_end);
1408 map.length = end - kernel_x_end;
1409 map.type = MT_MEMORY_RW;
1411 create_mapping(&map);
1417 #ifdef CONFIG_ARM_LPAE
1419 * early_paging_init() recreates boot time page table setup, allowing machines
1420 * to switch over to a high (>4G) address space on LPAE systems
1422 void __init early_paging_init(const struct machine_desc *mdesc,
1423 struct proc_info_list *procinfo)
1425 pmdval_t pmdprot = procinfo->__cpu_mm_mmu_flags;
1426 unsigned long map_start, map_end;
1428 pud_t *pud0, *pudk, *pud_start;
1433 if (!(mdesc->init_meminfo))
1436 /* remap kernel code and data */
1437 map_start = init_mm.start_code;
1438 map_end = init_mm.brk;
1440 /* get a handle on things... */
1441 pgd0 = pgd_offset_k(0);
1442 pud_start = pud0 = pud_offset(pgd0, 0);
1443 pmd0 = pmd_offset(pud0, 0);
1445 pgdk = pgd_offset_k(map_start);
1446 pudk = pud_offset(pgdk, map_start);
1447 pmdk = pmd_offset(pudk, map_start);
1449 mdesc->init_meminfo();
1451 /* Run the patch stub to update the constants */
1452 fixup_pv_table(&__pv_table_begin,
1453 (&__pv_table_end - &__pv_table_begin) << 2);
1456 * Cache cleaning operations for self-modifying code
1457 * We should clean the entries by MVA but running a
1458 * for loop over every pv_table entry pointer would
1459 * just complicate the code.
1461 flush_cache_louis();
1465 /* remap level 1 table */
1466 for (i = 0; i < PTRS_PER_PGD; pud0++, i++) {
1468 __pud(__pa(pmd0) | PMD_TYPE_TABLE | L_PGD_SWAPPER));
1469 pmd0 += PTRS_PER_PMD;
1472 /* remap pmds for kernel mapping */
1473 phys = __pa(map_start) & PMD_MASK;
1475 *pmdk++ = __pmd(phys | pmdprot);
1477 } while (phys < map_end);
1480 cpu_switch_mm(pgd0, &init_mm);
1481 cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET);
1482 local_flush_bp_all();
1483 local_flush_tlb_all();
1488 void __init early_paging_init(const struct machine_desc *mdesc,
1489 struct proc_info_list *procinfo)
1491 if (mdesc->init_meminfo)
1492 mdesc->init_meminfo();
1498 * paging_init() sets up the page tables, initialises the zone memory
1499 * maps, and sets up the zero page, bad page and bad page tables.
1501 void __init paging_init(const struct machine_desc *mdesc)
1505 build_mem_type_table();
1506 prepare_page_table();
1508 dma_contiguous_remap();
1509 devicemaps_init(mdesc);
1513 top_pmd = pmd_off_k(0xffff0000);
1515 /* allocate the zero page. */
1516 zero_page = early_alloc(PAGE_SIZE);
1520 empty_zero_page = virt_to_page(zero_page);
1521 __flush_dcache_page(NULL, empty_zero_page);