arch/arm/mm/mmu.c

   1 /*
   2  *  linux/arch/arm/mm/mmu.c
   3  *
   4  *  Copyright (C) 1995-2005 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/init.h>
  14 #include <linux/mman.h>
  15 #include <linux/nodemask.h>
  16 #include <linux/memblock.h>
  17 #include <linux/fs.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/sizes.h>
  20
  21 #include <asm/cp15.h>
  22 #include <asm/cputype.h>
  23 #include <asm/sections.h>
  24 #include <asm/cachetype.h>
  25 #include <asm/setup.h>
  26 #include <asm/smp_plat.h>
  27 #include <asm/tlb.h>
  28 #include <asm/highmem.h>
  29 #include <asm/system_info.h>
  30 #include <asm/traps.h>
  31
  32 #include <asm/mach/arch.h>
  33 #include <asm/mach/map.h>
  34 #include <asm/mach/pci.h>
  35
  36 #include "mm.h"
  37
  38 /*
  39  * empty_zero_page is a special page that is used for
  40  * zero-initialized data and COW.
  41  */
  42 struct page *empty_zero_page;
  43 EXPORT_SYMBOL(empty_zero_page);
  44
  45 /*
  46  * The pmd table for the upper-most set of pages.
  47  */
  48 pmd_t *top_pmd;
  49
  50 #define CPOLICY_UNCACHED        0
  51 #define CPOLICY_BUFFERED        1
  52 #define CPOLICY_WRITETHROUGH    2
  53 #define CPOLICY_WRITEBACK       3
  54 #define CPOLICY_WRITEALLOC      4
  55
  56 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  57 static unsigned int ecc_mask __initdata = 0;
  58 pgprot_t pgprot_user;
  59 pgprot_t pgprot_kernel;
  60 pgprot_t pgprot_hyp_device;
  61 pgprot_t pgprot_s2;
  62 pgprot_t pgprot_s2_device;
  63
  64 EXPORT_SYMBOL(pgprot_user);
  65 EXPORT_SYMBOL(pgprot_kernel);
  66
  67 struct cachepolicy {
  68         const char      policy[16];
  69         unsigned int    cr_mask;
  70         pmdval_t        pmd;
  71         pteval_t        pte;
  72         pteval_t        pte_s2;
  73 };
  74
  75 #ifdef CONFIG_ARM_LPAE
  76 #define s2_policy(policy)       policy
  77 #else
  78 #define s2_policy(policy)       0
  79 #endif
  80
  81 static struct cachepolicy cache_policies[] __initdata = {
  82         {
  83                 .policy         = "uncached",
  84                 .cr_mask        = CR_W|CR_C,
  85                 .pmd            = PMD_SECT_UNCACHED,
  86                 .pte            = L_PTE_MT_UNCACHED,
  87                 .pte_s2         = s2_policy(L_PTE_S2_MT_UNCACHED),
  88         }, {
  89                 .policy         = "buffered",
  90                 .cr_mask        = CR_C,
  91                 .pmd            = PMD_SECT_BUFFERED,
  92                 .pte            = L_PTE_MT_BUFFERABLE,
  93                 .pte_s2         = s2_policy(L_PTE_S2_MT_UNCACHED),
  94         }, {
  95                 .policy         = "writethrough",
  96                 .cr_mask        = 0,
  97                 .pmd            = PMD_SECT_WT,
  98                 .pte            = L_PTE_MT_WRITETHROUGH,
  99                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
 100         }, {
 101                 .policy         = "writeback",
 102                 .cr_mask        = 0,
 103                 .pmd            = PMD_SECT_WB,
 104                 .pte            = L_PTE_MT_WRITEBACK,
 105                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITEBACK),
 106         }, {
 107                 .policy         = "writealloc",
 108                 .cr_mask        = 0,
 109                 .pmd            = PMD_SECT_WBWA,
 110                 .pte            = L_PTE_MT_WRITEALLOC,
 111                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITEBACK),
 112         }
 113 };
 114
 115 #ifdef CONFIG_CPU_CP15
 116 /*
 117  * These are useful for identifying cache coherency
 118  * problems by allowing the cache or the cache and
 119  * writebuffer to be turned off.  (Note: the write
 120  * buffer should not be on and the cache off).
 121  */
 122 static int __init early_cachepolicy(char *p)
 123 {
 124         int i;
 125
 126         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
 127                 int len = strlen(cache_policies[i].policy);
 128
 129                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
 130                         cachepolicy = i;
 131                         cr_alignment &= ~cache_policies[i].cr_mask;
 132                         cr_no_alignment &= ~cache_policies[i].cr_mask;
 133                         break;
 134                 }
 135         }
 136         if (i == ARRAY_SIZE(cache_policies))
 137                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 138         /*
 139          * This restriction is partly to do with the way we boot; it is
 140          * unpredictable to have memory mapped using two different sets of
 141          * memory attributes (shared, type, and cache attribs).  We can not
 142          * change these attributes once the initial assembly has setup the
 143          * page tables.
 144          */
 145         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
 146                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
 147                 cachepolicy = CPOLICY_WRITEBACK;
 148         }
 149         flush_cache_all();
 150         set_cr(cr_alignment);
 151         return 0;
 152 }
 153 early_param("cachepolicy", early_cachepolicy);
 154
 155 static int __init early_nocache(char *__unused)
 156 {
 157         char *p = "buffered";
 158         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 159         early_cachepolicy(p);
 160         return 0;
 161 }
 162 early_param("nocache", early_nocache);
 163
 164 static int __init early_nowrite(char *__unused)
 165 {
 166         char *p = "uncached";
 167         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 168         early_cachepolicy(p);
 169         return 0;
 170 }
 171 early_param("nowb", early_nowrite);
 172
 173 #ifndef CONFIG_ARM_LPAE
 174 static int __init early_ecc(char *p)
 175 {
 176         if (memcmp(p, "on", 2) == 0)
 177                 ecc_mask = PMD_PROTECTION;
 178         else if (memcmp(p, "off", 3) == 0)
 179                 ecc_mask = 0;
 180         return 0;
 181 }
 182 early_param("ecc", early_ecc);
 183 #endif
 184
 185 static int __init noalign_setup(char *__unused)
 186 {
 187         cr_alignment &= ~CR_A;
 188         cr_no_alignment &= ~CR_A;
 189         set_cr(cr_alignment);
 190         return 1;
 191 }
 192 __setup("noalign", noalign_setup);
 193
 194 #ifndef CONFIG_SMP
 195 void adjust_cr(unsigned long mask, unsigned long set)
 196 {
 197         unsigned long flags;
 198
 199         mask &= ~CR_A;
 200
 201         set &= mask;
 202
 203         local_irq_save(flags);
 204
 205         cr_no_alignment = (cr_no_alignment & ~mask) | set;
 206         cr_alignment = (cr_alignment & ~mask) | set;
 207
 208         set_cr((get_cr() & ~mask) | set);
 209
 210         local_irq_restore(flags);
 211 }
 212 #endif
 213
 214 #else /* ifdef CONFIG_CPU_CP15 */
 215
 216 static int __init early_cachepolicy(char *p)
 217 {
 218         pr_warning("cachepolicy kernel parameter not supported without cp15\n");
 219 }
 220 early_param("cachepolicy", early_cachepolicy);
 221
 222 static int __init noalign_setup(char *__unused)
 223 {
 224         pr_warning("noalign kernel parameter not supported without cp15\n");
 225 }
 226 __setup("noalign", noalign_setup);
 227
 228 #endif /* ifdef CONFIG_CPU_CP15 / else */
 229
 230 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
 231 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 232
 233 static struct mem_type mem_types[] = {
 234         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
 235                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
 236                                   L_PTE_SHARED,
 237                 .prot_l1        = PMD_TYPE_TABLE,
 238                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
 239                 .domain         = DOMAIN_IO,
 240         },
 241         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
 242                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
 243                 .prot_l1        = PMD_TYPE_TABLE,
 244                 .prot_sect      = PROT_SECT_DEVICE,
 245                 .domain         = DOMAIN_IO,
 246         },
 247         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
 248                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
 249                 .prot_l1        = PMD_TYPE_TABLE,
 250                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
 251                 .domain         = DOMAIN_IO,
 252         },
 253         [MT_DEVICE_WC] = {      /* ioremap_wc */
 254                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
 255                 .prot_l1        = PMD_TYPE_TABLE,
 256                 .prot_sect      = PROT_SECT_DEVICE,
 257                 .domain         = DOMAIN_IO,
 258         },
 259         [MT_UNCACHED] = {
 260                 .prot_pte       = PROT_PTE_DEVICE,
 261                 .prot_l1        = PMD_TYPE_TABLE,
 262                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
 263                 .domain         = DOMAIN_IO,
 264         },
 265         [MT_CACHECLEAN] = {
 266                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 267                 .domain    = DOMAIN_KERNEL,
 268         },
 269 #ifndef CONFIG_ARM_LPAE
 270         [MT_MINICLEAN] = {
 271                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
 272                 .domain    = DOMAIN_KERNEL,
 273         },
 274 #endif
 275         [MT_LOW_VECTORS] = {
 276                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 277                                 L_PTE_RDONLY,
 278                 .prot_l1   = PMD_TYPE_TABLE,
 279                 .domain    = DOMAIN_USER,
 280         },
 281         [MT_HIGH_VECTORS] = {
 282                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 283                                 L_PTE_USER | L_PTE_RDONLY,
 284                 .prot_l1   = PMD_TYPE_TABLE,
 285                 .domain    = DOMAIN_USER,
 286         },
 287         [MT_MEMORY] = {
 288                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 289                 .prot_l1   = PMD_TYPE_TABLE,
 290                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 291                 .domain    = DOMAIN_KERNEL,
 292         },
 293         [MT_ROM] = {
 294                 .prot_sect = PMD_TYPE_SECT,
 295                 .domain    = DOMAIN_KERNEL,
 296         },
 297         [MT_MEMORY_NONCACHED] = {
 298                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 299                                 L_PTE_MT_BUFFERABLE,
 300                 .prot_l1   = PMD_TYPE_TABLE,
 301                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 302                 .domain    = DOMAIN_KERNEL,
 303         },
 304         [MT_MEMORY_DTCM] = {
 305                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 306                                 L_PTE_XN,
 307                 .prot_l1   = PMD_TYPE_TABLE,
 308                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 309                 .domain    = DOMAIN_KERNEL,
 310         },
 311         [MT_MEMORY_ITCM] = {
 312                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 313                 .prot_l1   = PMD_TYPE_TABLE,
 314                 .domain    = DOMAIN_KERNEL,
 315         },
 316         [MT_MEMORY_SO] = {
 317                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 318                                 L_PTE_MT_UNCACHED | L_PTE_XN,
 319                 .prot_l1   = PMD_TYPE_TABLE,
 320                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
 321                                 PMD_SECT_UNCACHED | PMD_SECT_XN,
 322                 .domain    = DOMAIN_KERNEL,
 323         },
 324         [MT_MEMORY_DMA_READY] = {
 325                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 326                 .prot_l1   = PMD_TYPE_TABLE,
 327                 .domain    = DOMAIN_KERNEL,
 328         },
 329 };
 330
 331 const struct mem_type *get_mem_type(unsigned int type)
 332 {
 333         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
 334 }
 335 EXPORT_SYMBOL(get_mem_type);
 336
 337 /*
 338  * Adjust the PMD section entries according to the CPU in use.
 339  */
 340 static void __init build_mem_type_table(void)
 341 {
 342         struct cachepolicy *cp;
 343         unsigned int cr = get_cr();
 344         pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
 345         pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
 346         int cpu_arch = cpu_architecture();
 347         int i;
 348
 349         if (cpu_arch < CPU_ARCH_ARMv6) {
 350 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 351                 if (cachepolicy > CPOLICY_BUFFERED)
 352                         cachepolicy = CPOLICY_BUFFERED;
 353 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 354                 if (cachepolicy > CPOLICY_WRITETHROUGH)
 355                         cachepolicy = CPOLICY_WRITETHROUGH;
 356 #endif
 357         }
 358         if (cpu_arch < CPU_ARCH_ARMv5) {
 359                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 360                         cachepolicy = CPOLICY_WRITEBACK;
 361                 ecc_mask = 0;
 362         }
 363         if (is_smp())
 364                 cachepolicy = CPOLICY_WRITEALLOC;
 365
 366         /*
 367          * Strip out features not present on earlier architectures.
 368          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
 369          * without extended page tables don't have the 'Shared' bit.
 370          */
 371         if (cpu_arch < CPU_ARCH_ARMv5)
 372                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 373                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
 374         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
 375                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 376                         mem_types[i].prot_sect &= ~PMD_SECT_S;
 377
 378         /*
 379          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
 380          * "update-able on write" bit on ARM610).  However, Xscale and
 381          * Xscale3 require this bit to be cleared.
 382          */
 383         if (cpu_is_xscale() || cpu_is_xsc3()) {
 384                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 385                         mem_types[i].prot_sect &= ~PMD_BIT4;
 386                         mem_types[i].prot_l1 &= ~PMD_BIT4;
 387                 }
 388         } else if (cpu_arch < CPU_ARCH_ARMv6) {
 389                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 390                         if (mem_types[i].prot_l1)
 391                                 mem_types[i].prot_l1 |= PMD_BIT4;
 392                         if (mem_types[i].prot_sect)
 393                                 mem_types[i].prot_sect |= PMD_BIT4;
 394                 }
 395         }
 396
 397         /*
 398          * Mark the device areas according to the CPU/architecture.
 399          */
 400         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
 401                 if (!cpu_is_xsc3()) {
 402                         /*
 403                          * Mark device regions on ARMv6+ as execute-never
 404                          * to prevent speculative instruction fetches.
 405                          */
 406                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
 407                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
 408                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
 409                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
 410                 }
 411                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 412                         /*
 413                          * For ARMv7 with TEX remapping,
 414                          * - shared device is SXCB=1100
 415                          * - nonshared device is SXCB=0100
 416                          * - write combine device mem is SXCB=0001
 417                          * (Uncached Normal memory)
 418                          */
 419                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
 420                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
 421                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 422                 } else if (cpu_is_xsc3()) {
 423                         /*
 424                          * For Xscale3,
 425                          * - shared device is TEXCB=00101
 426                          * - nonshared device is TEXCB=01000
 427                          * - write combine device mem is TEXCB=00100
 428                          * (Inner/Outer Uncacheable in xsc3 parlance)
 429                          */
 430                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
 431                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 432                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 433                 } else {
 434                         /*
 435                          * For ARMv6 and ARMv7 without TEX remapping,
 436                          * - shared device is TEXCB=00001
 437                          * - nonshared device is TEXCB=01000
 438                          * - write combine device mem is TEXCB=00100
 439                          * (Uncached Normal in ARMv6 parlance).
 440                          */
 441                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 442                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 443                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 444                 }
 445         } else {
 446                 /*
 447                  * On others, write combining is "Uncached/Buffered"
 448                  */
 449                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 450         }
 451
 452         /*
 453          * Now deal with the memory-type mappings
 454          */
 455         cp = &cache_policies[cachepolicy];
 456         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 457         s2_pgprot = cp->pte_s2;
 458         hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
 459
 460         /*
 461          * ARMv6 and above have extended page tables.
 462          */
 463         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 464 #ifndef CONFIG_ARM_LPAE
 465                 /*
 466                  * Mark cache clean areas and XIP ROM read only
 467                  * from SVC mode and no access from userspace.
 468                  */
 469                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 470                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 471                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 472 #endif
 473
 474                 if (is_smp()) {
 475                         /*
 476                          * Mark memory with the "shared" attribute
 477                          * for SMP systems
 478                          */
 479                         user_pgprot |= L_PTE_SHARED;
 480                         kern_pgprot |= L_PTE_SHARED;
 481                         vecs_pgprot |= L_PTE_SHARED;
 482                         s2_pgprot |= L_PTE_SHARED;
 483                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
 484                         mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
 485                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
 486                         mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
 487                         mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 488                         mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 489                         mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
 490                         mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 491                         mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 492                 }
 493         }
 494
 495         /*
 496          * Non-cacheable Normal - intended for memory areas that must
 497          * not cause dirty cache line writebacks when used
 498          */
 499         if (cpu_arch >= CPU_ARCH_ARMv6) {
 500                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 501                         /* Non-cacheable Normal is XCB = 001 */
 502                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 503                                 PMD_SECT_BUFFERED;
 504                 } else {
 505                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
 506                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 507                                 PMD_SECT_TEX(1);
 508                 }
 509         } else {
 510                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
 511         }
 512
 513 #ifdef CONFIG_ARM_LPAE
 514         /*
 515          * Do not generate access flag faults for the kernel mappings.
 516          */
 517         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 518                 mem_types[i].prot_pte |= PTE_EXT_AF;
 519                 if (mem_types[i].prot_sect)
 520                         mem_types[i].prot_sect |= PMD_SECT_AF;
 521         }
 522         kern_pgprot |= PTE_EXT_AF;
 523         vecs_pgprot |= PTE_EXT_AF;
 524 #endif
 525
 526         for (i = 0; i < 16; i++) {
 527                 pteval_t v = pgprot_val(protection_map[i]);
 528                 protection_map[i] = __pgprot(v | user_pgprot);
 529         }
 530
 531         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
 532         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
 533
 534         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
 535         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 536                                  L_PTE_DIRTY | kern_pgprot);
 537         pgprot_s2  = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
 538         pgprot_s2_device  = __pgprot(s2_device_pgprot);
 539         pgprot_hyp_device  = __pgprot(hyp_device_pgprot);
 540
 541         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 542         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 543         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 544         mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
 545         mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
 546         mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
 547         mem_types[MT_ROM].prot_sect |= cp->pmd;
 548
 549         switch (cp->pmd) {
 550         case PMD_SECT_WT:
 551                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 552                 break;
 553         case PMD_SECT_WB:
 554         case PMD_SECT_WBWA:
 555                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 556                 break;
 557         }
 558         printk("Memory policy: ECC %sabled, Data cache %s\n",
 559                 ecc_mask ? "en" : "dis", cp->policy);
 560
 561         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 562                 struct mem_type *t = &mem_types[i];
 563                 if (t->prot_l1)
 564                         t->prot_l1 |= PMD_DOMAIN(t->domain);
 565                 if (t->prot_sect)
 566                         t->prot_sect |= PMD_DOMAIN(t->domain);
 567         }
 568 }
 569
 570 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 571 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 572                               unsigned long size, pgprot_t vma_prot)
 573 {
 574         if (!pfn_valid(pfn))
 575                 return pgprot_noncached(vma_prot);
 576         else if (file->f_flags & O_SYNC)
 577                 return pgprot_writecombine(vma_prot);
 578         return vma_prot;
 579 }
 580 EXPORT_SYMBOL(phys_mem_access_prot);
 581 #endif
 582
 583 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 584
 585 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
 586 {
 587         void *ptr = __va(memblock_alloc(sz, align));
 588         memset(ptr, 0, sz);
 589         return ptr;
 590 }
 591
 592 static void __init *early_alloc(unsigned long sz)
 593 {
 594         return early_alloc_aligned(sz, sz);
 595 }
 596
 597 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
 598 {
 599         if (pmd_none(*pmd)) {
 600                 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
 601                 __pmd_populate(pmd, __pa(pte), prot);
 602         }
 603         BUG_ON(pmd_bad(*pmd));
 604         return pte_offset_kernel(pmd, addr);
 605 }
 606
 607 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 608                                   unsigned long end, unsigned long pfn,
 609                                   const struct mem_type *type)
 610 {
 611         pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
 612         do {
 613                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
 614                 pfn++;
 615         } while (pte++, addr += PAGE_SIZE, addr != end);
 616 }
 617
 618 static void __init alloc_init_section(pud_t *pud, unsigned long addr,
 619                                       unsigned long end, phys_addr_t phys,
 620                                       const struct mem_type *type)
 621 {
 622         pmd_t *pmd = pmd_offset(pud, addr);
 623
 624         /*
 625          * Try a section mapping - end, addr and phys must all be aligned
 626          * to a section boundary.  Note that PMDs refer to the individual
 627          * L1 entries, whereas PGDs refer to a group of L1 entries making
 628          * up one logical pointer to an L2 table.
 629          */
 630         if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) {
 631                 pmd_t *p = pmd;
 632
 633 #ifndef CONFIG_ARM_LPAE
 634                 if (addr & SECTION_SIZE)
 635                         pmd++;
 636 #endif
 637
 638                 do {
 639                         *pmd = __pmd(phys | type->prot_sect);
 640                         phys += SECTION_SIZE;
 641                 } while (pmd++, addr += SECTION_SIZE, addr != end);
 642
 643                 flush_pmd_entry(p);
 644         } else {
 645                 /*
 646                  * No need to loop; pte's aren't interested in the
 647                  * individual L1 entries.
 648                  */
 649                 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
 650         }
 651 }
 652
 653 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
 654         unsigned long end, unsigned long phys, const struct mem_type *type)
 655 {
 656         pud_t *pud = pud_offset(pgd, addr);
 657         unsigned long next;
 658
 659         do {
 660                 next = pud_addr_end(addr, end);
 661                 alloc_init_section(pud, addr, next, phys, type);
 662                 phys += next - addr;
 663         } while (pud++, addr = next, addr != end);
 664 }
 665
 666 #ifndef CONFIG_ARM_LPAE
 667 static void __init create_36bit_mapping(struct map_desc *md,
 668                                         const struct mem_type *type)
 669 {
 670         unsigned long addr, length, end;
 671         phys_addr_t phys;
 672         pgd_t *pgd;
 673
 674         addr = md->virtual;
 675         phys = __pfn_to_phys(md->pfn);
 676         length = PAGE_ALIGN(md->length);
 677
 678         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
 679                 printk(KERN_ERR "MM: CPU does not support supersection "
 680                        "mapping for 0x%08llx at 0x%08lx\n",
 681                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 682                 return;
 683         }
 684
 685         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 686          *      Since domain assignments can in fact be arbitrary, the
 687          *      'domain == 0' check below is required to insure that ARMv6
 688          *      supersections are only allocated for domain 0 regardless
 689          *      of the actual domain assignments in use.
 690          */
 691         if (type->domain) {
 692                 printk(KERN_ERR "MM: invalid domain in supersection "
 693                        "mapping for 0x%08llx at 0x%08lx\n",
 694                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 695                 return;
 696         }
 697
 698         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
 699                 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
 700                        " at 0x%08lx invalid alignment\n",
 701                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 702                 return;
 703         }
 704
 705         /*
 706          * Shift bits [35:32] of address into bits [23:20] of PMD
 707          * (See ARMv6 spec).
 708          */
 709         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
 710
 711         pgd = pgd_offset_k(addr);
 712         end = addr + length;
 713         do {
 714                 pud_t *pud = pud_offset(pgd, addr);
 715                 pmd_t *pmd = pmd_offset(pud, addr);
 716                 int i;
 717
 718                 for (i = 0; i < 16; i++)
 719                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
 720
 721                 addr += SUPERSECTION_SIZE;
 722                 phys += SUPERSECTION_SIZE;
 723                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
 724         } while (addr != end);
 725 }
 726 #endif  /* !CONFIG_ARM_LPAE */
 727
 728 /*
 729  * Create the page directory entries and any necessary
 730  * page tables for the mapping specified by `md'.  We
 731  * are able to cope here with varying sizes and address
 732  * offsets, and we take full advantage of sections and
 733  * supersections.
 734  */
 735 static void __init create_mapping(struct map_desc *md)
 736 {
 737         unsigned long addr, length, end;
 738         phys_addr_t phys;
 739         const struct mem_type *type;
 740         pgd_t *pgd;
 741
 742         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 743                 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
 744                        " at 0x%08lx in user region\n",
 745                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 746                 return;
 747         }
 748
 749         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 750             md->virtual >= PAGE_OFFSET &&
 751             (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
 752                 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
 753                        " at 0x%08lx out of vmalloc space\n",
 754                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 755         }
 756
 757         type = &mem_types[md->type];
 758
 759 #ifndef CONFIG_ARM_LPAE
 760         /*
 761          * Catch 36-bit addresses
 762          */
 763         if (md->pfn >= 0x100000) {
 764                 create_36bit_mapping(md, type);
 765                 return;
 766         }
 767 #endif
 768
 769         addr = md->virtual & PAGE_MASK;
 770         phys = __pfn_to_phys(md->pfn);
 771         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 772
 773         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
 774                 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
 775                        "be mapped using pages, ignoring.\n",
 776                        (long long)__pfn_to_phys(md->pfn), addr);
 777                 return;
 778         }
 779
 780         pgd = pgd_offset_k(addr);
 781         end = addr + length;
 782         do {
 783                 unsigned long next = pgd_addr_end(addr, end);
 784
 785                 alloc_init_pud(pgd, addr, next, phys, type);
 786
 787                 phys += next - addr;
 788                 addr = next;
 789         } while (pgd++, addr != end);
 790 }
 791
 792 /*
 793  * Create the architecture specific mappings
 794  */
 795 void __init iotable_init(struct map_desc *io_desc, int nr)
 796 {
 797         struct map_desc *md;
 798         struct vm_struct *vm;
 799         struct static_vm *svm;
 800
 801         if (!nr)
 802                 return;
 803
 804         svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
 805
 806         for (md = io_desc; nr; md++, nr--) {
 807                 create_mapping(md);
 808
 809                 vm = &svm->vm;
 810                 vm->addr = (void *)(md->virtual & PAGE_MASK);
 811                 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 812                 vm->phys_addr = __pfn_to_phys(md->pfn);
 813                 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
 814                 vm->flags |= VM_ARM_MTYPE(md->type);
 815                 vm->caller = iotable_init;
 816                 add_static_vm_early(svm++);
 817         }
 818 }
 819
 820 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
 821                                   void *caller)
 822 {
 823         struct vm_struct *vm;
 824         struct static_vm *svm;
 825
 826         svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
 827
 828         vm = &svm->vm;
 829         vm->addr = (void *)addr;
 830         vm->size = size;
 831         vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
 832         vm->caller = caller;
 833         add_static_vm_early(svm);
 834 }
 835
 836 #ifndef CONFIG_ARM_LPAE
 837
 838 /*
 839  * The Linux PMD is made of two consecutive section entries covering 2MB
 840  * (see definition in include/asm/pgtable-2level.h).  However a call to
 841  * create_mapping() may optimize static mappings by using individual
 842  * 1MB section mappings.  This leaves the actual PMD potentially half
 843  * initialized if the top or bottom section entry isn't used, leaving it
 844  * open to problems if a subsequent ioremap() or vmalloc() tries to use
 845  * the virtual space left free by that unused section entry.
 846  *
 847  * Let's avoid the issue by inserting dummy vm entries covering the unused
 848  * PMD halves once the static mappings are in place.
 849  */
 850
 851 static void __init pmd_empty_section_gap(unsigned long addr)
 852 {
 853         vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
 854 }
 855
 856 static void __init fill_pmd_gaps(void)
 857 {
 858         struct static_vm *svm;
 859         struct vm_struct *vm;
 860         unsigned long addr, next = 0;
 861         pmd_t *pmd;
 862
 863         list_for_each_entry(svm, &static_vmlist, list) {
 864                 vm = &svm->vm;
 865                 addr = (unsigned long)vm->addr;
 866                 if (addr < next)
 867                         continue;
 868
 869                 /*
 870                  * Check if this vm starts on an odd section boundary.
 871                  * If so and the first section entry for this PMD is free
 872                  * then we block the corresponding virtual address.
 873                  */
 874                 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
 875                         pmd = pmd_off_k(addr);
 876                         if (pmd_none(*pmd))
 877                                 pmd_empty_section_gap(addr & PMD_MASK);
 878                 }
 879
 880                 /*
 881                  * Then check if this vm ends on an odd section boundary.
 882                  * If so and the second section entry for this PMD is empty
 883                  * then we block the corresponding virtual address.
 884                  */
 885                 addr += vm->size;
 886                 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
 887                         pmd = pmd_off_k(addr) + 1;
 888                         if (pmd_none(*pmd))
 889                                 pmd_empty_section_gap(addr);
 890                 }
 891
 892                 /* no need to look at any vm entry until we hit the next PMD */
 893                 next = (addr + PMD_SIZE - 1) & PMD_MASK;
 894         }
 895 }
 896
 897 #else
 898 #define fill_pmd_gaps() do { } while (0)
 899 #endif
 900
 901 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
 902 static void __init pci_reserve_io(void)
 903 {
 904         struct static_vm *svm;
 905
 906         svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
 907         if (svm)
 908                 return;
 909
 910         vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
 911 }
 912 #else
 913 #define pci_reserve_io() do { } while (0)
 914 #endif
 915
 916 #ifdef CONFIG_DEBUG_LL
 917 void __init debug_ll_io_init(void)
 918 {
 919         struct map_desc map;
 920
 921         debug_ll_addr(&map.pfn, &map.virtual);
 922         if (!map.pfn || !map.virtual)
 923                 return;
 924         map.pfn = __phys_to_pfn(map.pfn);
 925         map.virtual &= PAGE_MASK;
 926         map.length = PAGE_SIZE;
 927         map.type = MT_DEVICE;
 928         create_mapping(&map);
 929 }
 930 #endif
 931
 932 static void * __initdata vmalloc_min =
 933         (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
 934
 935 /*
 936  * vmalloc=size forces the vmalloc area to be exactly 'size'
 937  * bytes. This can be used to increase (or decrease) the vmalloc
 938  * area - the default is 240m.
 939  */
 940 static int __init early_vmalloc(char *arg)
 941 {
 942         unsigned long vmalloc_reserve = memparse(arg, NULL);
 943
 944         if (vmalloc_reserve < SZ_16M) {
 945                 vmalloc_reserve = SZ_16M;
 946                 printk(KERN_WARNING
 947                         "vmalloc area too small, limiting to %luMB\n",
 948                         vmalloc_reserve >> 20);
 949         }
 950
 951         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
 952                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
 953                 printk(KERN_WARNING
 954                         "vmalloc area is too big, limiting to %luMB\n",
 955                         vmalloc_reserve >> 20);
 956         }
 957
 958         vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
 959         return 0;
 960 }
 961 early_param("vmalloc", early_vmalloc);
 962
 963 phys_addr_t arm_lowmem_limit __initdata = 0;
 964
 965 void __init sanity_check_meminfo(void)
 966 {
 967         int i, j, highmem = 0;
 968
 969         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 970                 struct membank *bank = &meminfo.bank[j];
 971                 *bank = meminfo.bank[i];
 972
 973                 if (bank->start > ULONG_MAX)
 974                         highmem = 1;
 975
 976 #ifdef CONFIG_HIGHMEM
 977                 if (__va(bank->start) >= vmalloc_min ||
 978                     __va(bank->start) < (void *)PAGE_OFFSET)
 979                         highmem = 1;
 980
 981                 bank->highmem = highmem;
 982
 983                 /*
 984                  * Split those memory banks which are partially overlapping
 985                  * the vmalloc area greatly simplifying things later.
 986                  */
 987                 if (!highmem && __va(bank->start) < vmalloc_min &&
 988                     bank->size > vmalloc_min - __va(bank->start)) {
 989                         if (meminfo.nr_banks >= NR_BANKS) {
 990                                 printk(KERN_CRIT "NR_BANKS too low, "
 991                                                  "ignoring high memory\n");
 992                         } else {
 993                                 memmove(bank + 1, bank,
 994                                         (meminfo.nr_banks - i) * sizeof(*bank));
 995                                 meminfo.nr_banks++;
 996                                 i++;
 997                                 bank[1].size -= vmalloc_min - __va(bank->start);
 998                                 bank[1].start = __pa(vmalloc_min - 1) + 1;
 999                                 bank[1].highmem = highmem = 1;
1000                                 j++;
1001                         }
1002                         bank->size = vmalloc_min - __va(bank->start);
1003                 }
1004 #else
1005                 bank->highmem = highmem;
1006
1007                 /*
1008                  * Highmem banks not allowed with !CONFIG_HIGHMEM.
1009                  */
1010                 if (highmem) {
1011                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1012                                "(!CONFIG_HIGHMEM).\n",
1013                                (unsigned long long)bank->start,
1014                                (unsigned long long)bank->start + bank->size - 1);
1015                         continue;
1016                 }
1017
1018                 /*
1019                  * Check whether this memory bank would entirely overlap
1020                  * the vmalloc area.
1021                  */
1022                 if (__va(bank->start) >= vmalloc_min ||
1023                     __va(bank->start) < (void *)PAGE_OFFSET) {
1024                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1025                                "(vmalloc region overlap).\n",
1026                                (unsigned long long)bank->start,
1027                                (unsigned long long)bank->start + bank->size - 1);
1028                         continue;
1029                 }
1030
1031                 /*
1032                  * Check whether this memory bank would partially overlap
1033                  * the vmalloc area.
1034                  */
1035                 if (__va(bank->start + bank->size - 1) >= vmalloc_min ||
1036                     __va(bank->start + bank->size - 1) <= __va(bank->start)) {
1037                         unsigned long newsize = vmalloc_min - __va(bank->start);
1038                         printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
1039                                "to -%.8llx (vmalloc region overlap).\n",
1040                                (unsigned long long)bank->start,
1041                                (unsigned long long)bank->start + bank->size - 1,
1042                                (unsigned long long)bank->start + newsize - 1);
1043                         bank->size = newsize;
1044                 }
1045 #endif
1046                 if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
1047                         arm_lowmem_limit = bank->start + bank->size;
1048
1049                 j++;
1050         }
1051 #ifdef CONFIG_HIGHMEM
1052         if (highmem) {
1053                 const char *reason = NULL;
1054
1055                 if (cache_is_vipt_aliasing()) {
1056                         /*
1057                          * Interactions between kmap and other mappings
1058                          * make highmem support with aliasing VIPT caches
1059                          * rather difficult.
1060                          */
1061                         reason = "with VIPT aliasing cache";
1062                 }
1063                 if (reason) {
1064                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1065                                 reason);
1066                         while (j > 0 && meminfo.bank[j - 1].highmem)
1067                                 j--;
1068                 }
1069         }
1070 #endif
1071         meminfo.nr_banks = j;
1072         high_memory = __va(arm_lowmem_limit - 1) + 1;
1073         memblock_set_current_limit(arm_lowmem_limit);
1074 }
1075
1076 static inline void prepare_page_table(void)
1077 {
1078         unsigned long addr;
1079         phys_addr_t end;
1080
1081         /*
1082          * Clear out all the mappings below the kernel image.
1083          */
1084         for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1085                 pmd_clear(pmd_off_k(addr));
1086
1087 #ifdef CONFIG_XIP_KERNEL
1088         /* The XIP kernel is mapped in the module area -- skip over it */
1089         addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1090 #endif
1091         for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1092                 pmd_clear(pmd_off_k(addr));
1093
1094         /*
1095          * Find the end of the first block of lowmem.
1096          */
1097         end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1098         if (end >= arm_lowmem_limit)
1099                 end = arm_lowmem_limit;
1100
1101         /*
1102          * Clear out all the kernel space mappings, except for the first
1103          * memory bank, up to the vmalloc region.
1104          */
1105         for (addr = __phys_to_virt(end);
1106              addr < VMALLOC_START; addr += PMD_SIZE)
1107                 pmd_clear(pmd_off_k(addr));
1108 }
1109
1110 #ifdef CONFIG_ARM_LPAE
1111 /* the first page is reserved for pgd */
1112 #define SWAPPER_PG_DIR_SIZE     (PAGE_SIZE + \
1113                                  PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1114 #else
1115 #define SWAPPER_PG_DIR_SIZE     (PTRS_PER_PGD * sizeof(pgd_t))
1116 #endif
1117
1118 /*
1119  * Reserve the special regions of memory
1120  */
1121 void __init arm_mm_memblock_reserve(void)
1122 {
1123         /*
1124          * Reserve the page tables.  These are already in use,
1125          * and can only be in node 0.
1126          */
1127         memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1128
1129 #ifdef CONFIG_SA1111
1130         /*
1131          * Because of the SA1111 DMA bug, we want to preserve our
1132          * precious DMA-able memory...
1133          */
1134         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1135 #endif
1136 }
1137
1138 /*
1139  * Set up the device mappings.  Since we clear out the page tables for all
1140  * mappings above VMALLOC_START, we will remove any debug device mappings.
1141  * This means you have to be careful how you debug this function, or any
1142  * called function.  This means you can't use any function or debugging
1143  * method which may touch any device, otherwise the kernel _will_ crash.
1144  */
1145 static void __init devicemaps_init(struct machine_desc *mdesc)
1146 {
1147         struct map_desc map;
1148         unsigned long addr;
1149         void *vectors;
1150
1151         /*
1152          * Allocate the vector page early.
1153          */
1154         vectors = early_alloc(PAGE_SIZE);
1155
1156         early_trap_init(vectors);
1157
1158         for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1159                 pmd_clear(pmd_off_k(addr));
1160
1161         /*
1162          * Map the kernel if it is XIP.
1163          * It is always first in the modulearea.
1164          */
1165 #ifdef CONFIG_XIP_KERNEL
1166         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1167         map.virtual = MODULES_VADDR;
1168         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1169         map.type = MT_ROM;
1170         create_mapping(&map);
1171 #endif
1172
1173         /*
1174          * Map the cache flushing regions.
1175          */
1176 #ifdef FLUSH_BASE
1177         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1178         map.virtual = FLUSH_BASE;
1179         map.length = SZ_1M;
1180         map.type = MT_CACHECLEAN;
1181         create_mapping(&map);
1182 #endif
1183 #ifdef FLUSH_BASE_MINICACHE
1184         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1185         map.virtual = FLUSH_BASE_MINICACHE;
1186         map.length = SZ_1M;
1187         map.type = MT_MINICLEAN;
1188         create_mapping(&map);
1189 #endif
1190
1191         /*
1192          * Create a mapping for the machine vectors at the high-vectors
1193          * location (0xffff0000).  If we aren't using high-vectors, also
1194          * create a mapping at the low-vectors virtual address.
1195          */
1196         map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1197         map.virtual = 0xffff0000;
1198         map.length = PAGE_SIZE;
1199         map.type = MT_HIGH_VECTORS;
1200         create_mapping(&map);
1201
1202         if (!vectors_high()) {
1203                 map.virtual = 0;
1204                 map.type = MT_LOW_VECTORS;
1205                 create_mapping(&map);
1206         }
1207
1208         /*
1209          * Ask the machine support to map in the statically mapped devices.
1210          */
1211         if (mdesc->map_io)
1212                 mdesc->map_io();
1213         fill_pmd_gaps();
1214
1215         /* Reserve fixed i/o space in VMALLOC region */
1216         pci_reserve_io();
1217
1218         /*
1219          * Finally flush the caches and tlb to ensure that we're in a
1220          * consistent state wrt the writebuffer.  This also ensures that
1221          * any write-allocated cache lines in the vector page are written
1222          * back.  After this point, we can start to touch devices again.
1223          */
1224         local_flush_tlb_all();
1225         flush_cache_all();
1226 }
1227
1228 static void __init kmap_init(void)
1229 {
1230 #ifdef CONFIG_HIGHMEM
1231         pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1232                 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1233 #endif
1234 }
1235
1236 static void __init map_lowmem(void)
1237 {
1238         struct memblock_region *reg;
1239
1240         /* Map all the lowmem memory banks. */
1241         for_each_memblock(memory, reg) {
1242                 phys_addr_t start = reg->base;
1243                 phys_addr_t end = start + reg->size;
1244                 struct map_desc map;
1245
1246                 if (end > arm_lowmem_limit)
1247                         end = arm_lowmem_limit;
1248                 if (start >= end)
1249                         break;
1250
1251                 map.pfn = __phys_to_pfn(start);
1252                 map.virtual = __phys_to_virt(start);
1253                 map.length = end - start;
1254                 map.type = MT_MEMORY;
1255
1256                 create_mapping(&map);
1257         }
1258 }
1259
1260 /*
1261  * paging_init() sets up the page tables, initialises the zone memory
1262  * maps, and sets up the zero page, bad page and bad page tables.
1263  */
1264 void __init paging_init(struct machine_desc *mdesc)
1265 {
1266         void *zero_page;
1267
1268         memblock_set_current_limit(arm_lowmem_limit);
1269
1270         build_mem_type_table();
1271         prepare_page_table();
1272         map_lowmem();
1273         dma_contiguous_remap();
1274         devicemaps_init(mdesc);
1275         kmap_init();
1276
1277         top_pmd = pmd_off_k(0xffff0000);
1278
1279         /* allocate the zero page. */
1280         zero_page = early_alloc(PAGE_SIZE);
1281
1282         bootmem_init();
1283
1284         empty_zero_page = virt_to_page(zero_page);
1285         __flush_dcache_page(NULL, empty_zero_page);
1286 }