2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sizes.h>
22 #include <asm/cputype.h>
23 #include <asm/sections.h>
24 #include <asm/cachetype.h>
25 #include <asm/setup.h>
26 #include <asm/smp_plat.h>
28 #include <asm/highmem.h>
29 #include <asm/system_info.h>
30 #include <asm/traps.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/map.h>
34 #include <asm/mach/pci.h>
39 * empty_zero_page is a special page that is used for
40 * zero-initialized data and COW.
42 struct page *empty_zero_page;
43 EXPORT_SYMBOL(empty_zero_page);
46 * The pmd table for the upper-most set of pages.
50 #define CPOLICY_UNCACHED 0
51 #define CPOLICY_BUFFERED 1
52 #define CPOLICY_WRITETHROUGH 2
53 #define CPOLICY_WRITEBACK 3
54 #define CPOLICY_WRITEALLOC 4
56 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
57 static unsigned int ecc_mask __initdata = 0;
59 pgprot_t pgprot_kernel;
60 pgprot_t pgprot_hyp_device;
62 pgprot_t pgprot_s2_device;
64 EXPORT_SYMBOL(pgprot_user);
65 EXPORT_SYMBOL(pgprot_kernel);
68 const char policy[16];
75 #ifdef CONFIG_ARM_LPAE
76 #define s2_policy(policy) policy
78 #define s2_policy(policy) 0
81 static struct cachepolicy cache_policies[] __initdata = {
85 .pmd = PMD_SECT_UNCACHED,
86 .pte = L_PTE_MT_UNCACHED,
87 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
91 .pmd = PMD_SECT_BUFFERED,
92 .pte = L_PTE_MT_BUFFERABLE,
93 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
95 .policy = "writethrough",
98 .pte = L_PTE_MT_WRITETHROUGH,
99 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
101 .policy = "writeback",
104 .pte = L_PTE_MT_WRITEBACK,
105 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
107 .policy = "writealloc",
109 .pmd = PMD_SECT_WBWA,
110 .pte = L_PTE_MT_WRITEALLOC,
111 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
115 #ifdef CONFIG_CPU_CP15
117 * These are useful for identifying cache coherency
118 * problems by allowing the cache or the cache and
119 * writebuffer to be turned off. (Note: the write
120 * buffer should not be on and the cache off).
122 static int __init early_cachepolicy(char *p)
126 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
127 int len = strlen(cache_policies[i].policy);
129 if (memcmp(p, cache_policies[i].policy, len) == 0) {
131 cr_alignment &= ~cache_policies[i].cr_mask;
132 cr_no_alignment &= ~cache_policies[i].cr_mask;
136 if (i == ARRAY_SIZE(cache_policies))
137 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
139 * This restriction is partly to do with the way we boot; it is
140 * unpredictable to have memory mapped using two different sets of
141 * memory attributes (shared, type, and cache attribs). We can not
142 * change these attributes once the initial assembly has setup the
145 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
146 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
147 cachepolicy = CPOLICY_WRITEBACK;
150 set_cr(cr_alignment);
153 early_param("cachepolicy", early_cachepolicy);
155 static int __init early_nocache(char *__unused)
157 char *p = "buffered";
158 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
159 early_cachepolicy(p);
162 early_param("nocache", early_nocache);
164 static int __init early_nowrite(char *__unused)
166 char *p = "uncached";
167 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
168 early_cachepolicy(p);
171 early_param("nowb", early_nowrite);
173 #ifndef CONFIG_ARM_LPAE
174 static int __init early_ecc(char *p)
176 if (memcmp(p, "on", 2) == 0)
177 ecc_mask = PMD_PROTECTION;
178 else if (memcmp(p, "off", 3) == 0)
182 early_param("ecc", early_ecc);
185 static int __init noalign_setup(char *__unused)
187 cr_alignment &= ~CR_A;
188 cr_no_alignment &= ~CR_A;
189 set_cr(cr_alignment);
192 __setup("noalign", noalign_setup);
195 void adjust_cr(unsigned long mask, unsigned long set)
203 local_irq_save(flags);
205 cr_no_alignment = (cr_no_alignment & ~mask) | set;
206 cr_alignment = (cr_alignment & ~mask) | set;
208 set_cr((get_cr() & ~mask) | set);
210 local_irq_restore(flags);
214 #else /* ifdef CONFIG_CPU_CP15 */
216 static int __init early_cachepolicy(char *p)
218 pr_warning("cachepolicy kernel parameter not supported without cp15\n");
220 early_param("cachepolicy", early_cachepolicy);
222 static int __init noalign_setup(char *__unused)
224 pr_warning("noalign kernel parameter not supported without cp15\n");
226 __setup("noalign", noalign_setup);
228 #endif /* ifdef CONFIG_CPU_CP15 / else */
230 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
231 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
233 static struct mem_type mem_types[] = {
234 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
235 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
237 .prot_l1 = PMD_TYPE_TABLE,
238 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
241 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
242 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
243 .prot_l1 = PMD_TYPE_TABLE,
244 .prot_sect = PROT_SECT_DEVICE,
247 [MT_DEVICE_CACHED] = { /* ioremap_cached */
248 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
249 .prot_l1 = PMD_TYPE_TABLE,
250 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
253 [MT_DEVICE_WC] = { /* ioremap_wc */
254 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
255 .prot_l1 = PMD_TYPE_TABLE,
256 .prot_sect = PROT_SECT_DEVICE,
260 .prot_pte = PROT_PTE_DEVICE,
261 .prot_l1 = PMD_TYPE_TABLE,
262 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
266 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
267 .domain = DOMAIN_KERNEL,
269 #ifndef CONFIG_ARM_LPAE
271 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
272 .domain = DOMAIN_KERNEL,
276 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
278 .prot_l1 = PMD_TYPE_TABLE,
279 .domain = DOMAIN_USER,
281 [MT_HIGH_VECTORS] = {
282 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
283 L_PTE_USER | L_PTE_RDONLY,
284 .prot_l1 = PMD_TYPE_TABLE,
285 .domain = DOMAIN_USER,
288 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
289 .prot_l1 = PMD_TYPE_TABLE,
290 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
291 .domain = DOMAIN_KERNEL,
294 .prot_sect = PMD_TYPE_SECT,
295 .domain = DOMAIN_KERNEL,
297 [MT_MEMORY_NONCACHED] = {
298 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
300 .prot_l1 = PMD_TYPE_TABLE,
301 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
302 .domain = DOMAIN_KERNEL,
305 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
307 .prot_l1 = PMD_TYPE_TABLE,
308 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
309 .domain = DOMAIN_KERNEL,
312 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
313 .prot_l1 = PMD_TYPE_TABLE,
314 .domain = DOMAIN_KERNEL,
317 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
318 L_PTE_MT_UNCACHED | L_PTE_XN,
319 .prot_l1 = PMD_TYPE_TABLE,
320 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
321 PMD_SECT_UNCACHED | PMD_SECT_XN,
322 .domain = DOMAIN_KERNEL,
324 [MT_MEMORY_DMA_READY] = {
325 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
326 .prot_l1 = PMD_TYPE_TABLE,
327 .domain = DOMAIN_KERNEL,
331 const struct mem_type *get_mem_type(unsigned int type)
333 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
335 EXPORT_SYMBOL(get_mem_type);
338 * Adjust the PMD section entries according to the CPU in use.
340 static void __init build_mem_type_table(void)
342 struct cachepolicy *cp;
343 unsigned int cr = get_cr();
344 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
345 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
346 int cpu_arch = cpu_architecture();
349 if (cpu_arch < CPU_ARCH_ARMv6) {
350 #if defined(CONFIG_CPU_DCACHE_DISABLE)
351 if (cachepolicy > CPOLICY_BUFFERED)
352 cachepolicy = CPOLICY_BUFFERED;
353 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
354 if (cachepolicy > CPOLICY_WRITETHROUGH)
355 cachepolicy = CPOLICY_WRITETHROUGH;
358 if (cpu_arch < CPU_ARCH_ARMv5) {
359 if (cachepolicy >= CPOLICY_WRITEALLOC)
360 cachepolicy = CPOLICY_WRITEBACK;
364 cachepolicy = CPOLICY_WRITEALLOC;
367 * Strip out features not present on earlier architectures.
368 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
369 * without extended page tables don't have the 'Shared' bit.
371 if (cpu_arch < CPU_ARCH_ARMv5)
372 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
373 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
374 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
375 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
376 mem_types[i].prot_sect &= ~PMD_SECT_S;
379 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
380 * "update-able on write" bit on ARM610). However, Xscale and
381 * Xscale3 require this bit to be cleared.
383 if (cpu_is_xscale() || cpu_is_xsc3()) {
384 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
385 mem_types[i].prot_sect &= ~PMD_BIT4;
386 mem_types[i].prot_l1 &= ~PMD_BIT4;
388 } else if (cpu_arch < CPU_ARCH_ARMv6) {
389 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
390 if (mem_types[i].prot_l1)
391 mem_types[i].prot_l1 |= PMD_BIT4;
392 if (mem_types[i].prot_sect)
393 mem_types[i].prot_sect |= PMD_BIT4;
398 * Mark the device areas according to the CPU/architecture.
400 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
401 if (!cpu_is_xsc3()) {
403 * Mark device regions on ARMv6+ as execute-never
404 * to prevent speculative instruction fetches.
406 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
407 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
408 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
409 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
411 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
413 * For ARMv7 with TEX remapping,
414 * - shared device is SXCB=1100
415 * - nonshared device is SXCB=0100
416 * - write combine device mem is SXCB=0001
417 * (Uncached Normal memory)
419 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
420 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
421 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
422 } else if (cpu_is_xsc3()) {
425 * - shared device is TEXCB=00101
426 * - nonshared device is TEXCB=01000
427 * - write combine device mem is TEXCB=00100
428 * (Inner/Outer Uncacheable in xsc3 parlance)
430 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
431 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
432 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
435 * For ARMv6 and ARMv7 without TEX remapping,
436 * - shared device is TEXCB=00001
437 * - nonshared device is TEXCB=01000
438 * - write combine device mem is TEXCB=00100
439 * (Uncached Normal in ARMv6 parlance).
441 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
442 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
443 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
447 * On others, write combining is "Uncached/Buffered"
449 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
453 * Now deal with the memory-type mappings
455 cp = &cache_policies[cachepolicy];
456 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
457 s2_pgprot = cp->pte_s2;
458 hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
461 * ARMv6 and above have extended page tables.
463 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
464 #ifndef CONFIG_ARM_LPAE
466 * Mark cache clean areas and XIP ROM read only
467 * from SVC mode and no access from userspace.
469 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
470 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
471 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
476 * Mark memory with the "shared" attribute
479 user_pgprot |= L_PTE_SHARED;
480 kern_pgprot |= L_PTE_SHARED;
481 vecs_pgprot |= L_PTE_SHARED;
482 s2_pgprot |= L_PTE_SHARED;
483 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
484 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
485 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
486 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
487 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
488 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
489 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
490 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
491 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
496 * Non-cacheable Normal - intended for memory areas that must
497 * not cause dirty cache line writebacks when used
499 if (cpu_arch >= CPU_ARCH_ARMv6) {
500 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
501 /* Non-cacheable Normal is XCB = 001 */
502 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
505 /* For both ARMv6 and non-TEX-remapping ARMv7 */
506 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
510 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
513 #ifdef CONFIG_ARM_LPAE
515 * Do not generate access flag faults for the kernel mappings.
517 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
518 mem_types[i].prot_pte |= PTE_EXT_AF;
519 if (mem_types[i].prot_sect)
520 mem_types[i].prot_sect |= PMD_SECT_AF;
522 kern_pgprot |= PTE_EXT_AF;
523 vecs_pgprot |= PTE_EXT_AF;
526 for (i = 0; i < 16; i++) {
527 pteval_t v = pgprot_val(protection_map[i]);
528 protection_map[i] = __pgprot(v | user_pgprot);
531 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
532 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
534 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
535 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
536 L_PTE_DIRTY | kern_pgprot);
537 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
538 pgprot_s2_device = __pgprot(s2_device_pgprot);
539 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
541 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
542 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
543 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
544 mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
545 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
546 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
547 mem_types[MT_ROM].prot_sect |= cp->pmd;
551 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
555 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
558 printk("Memory policy: ECC %sabled, Data cache %s\n",
559 ecc_mask ? "en" : "dis", cp->policy);
561 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
562 struct mem_type *t = &mem_types[i];
564 t->prot_l1 |= PMD_DOMAIN(t->domain);
566 t->prot_sect |= PMD_DOMAIN(t->domain);
570 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
571 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
572 unsigned long size, pgprot_t vma_prot)
575 return pgprot_noncached(vma_prot);
576 else if (file->f_flags & O_SYNC)
577 return pgprot_writecombine(vma_prot);
580 EXPORT_SYMBOL(phys_mem_access_prot);
583 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
585 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
587 void *ptr = __va(memblock_alloc(sz, align));
592 static void __init *early_alloc(unsigned long sz)
594 return early_alloc_aligned(sz, sz);
597 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
599 if (pmd_none(*pmd)) {
600 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
601 __pmd_populate(pmd, __pa(pte), prot);
603 BUG_ON(pmd_bad(*pmd));
604 return pte_offset_kernel(pmd, addr);
607 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
608 unsigned long end, unsigned long pfn,
609 const struct mem_type *type)
611 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
613 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
615 } while (pte++, addr += PAGE_SIZE, addr != end);
618 static void __init map_init_section(pmd_t *pmd, unsigned long addr,
619 unsigned long end, phys_addr_t phys,
620 const struct mem_type *type)
622 #ifndef CONFIG_ARM_LPAE
624 * In classic MMU format, puds and pmds are folded in to
625 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
626 * group of L1 entries making up one logical pointer to
627 * an L2 table (2MB), where as PMDs refer to the individual
628 * L1 entries (1MB). Hence increment to get the correct
629 * offset for odd 1MB sections.
630 * (See arch/arm/include/asm/pgtable-2level.h)
632 if (addr & SECTION_SIZE)
636 *pmd = __pmd(phys | type->prot_sect);
637 phys += SECTION_SIZE;
638 } while (pmd++, addr += SECTION_SIZE, addr != end);
640 flush_pmd_entry(pmd);
643 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
644 unsigned long end, phys_addr_t phys,
645 const struct mem_type *type)
647 pmd_t *pmd = pmd_offset(pud, addr);
652 * With LPAE, we must loop over to map
653 * all the pmds for the given range.
655 next = pmd_addr_end(addr, end);
658 * Try a section mapping - addr, next and phys must all be
659 * aligned to a section boundary.
661 if (type->prot_sect &&
662 ((addr | next | phys) & ~SECTION_MASK) == 0) {
663 map_init_section(pmd, addr, next, phys, type);
665 alloc_init_pte(pmd, addr, next,
666 __phys_to_pfn(phys), type);
671 } while (pmd++, addr = next, addr != end);
674 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
675 unsigned long end, unsigned long phys, const struct mem_type *type)
677 pud_t *pud = pud_offset(pgd, addr);
681 next = pud_addr_end(addr, end);
682 alloc_init_pmd(pud, addr, next, phys, type);
684 } while (pud++, addr = next, addr != end);
687 #ifndef CONFIG_ARM_LPAE
688 static void __init create_36bit_mapping(struct map_desc *md,
689 const struct mem_type *type)
691 unsigned long addr, length, end;
696 phys = __pfn_to_phys(md->pfn);
697 length = PAGE_ALIGN(md->length);
699 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
700 printk(KERN_ERR "MM: CPU does not support supersection "
701 "mapping for 0x%08llx at 0x%08lx\n",
702 (long long)__pfn_to_phys((u64)md->pfn), addr);
706 /* N.B. ARMv6 supersections are only defined to work with domain 0.
707 * Since domain assignments can in fact be arbitrary, the
708 * 'domain == 0' check below is required to insure that ARMv6
709 * supersections are only allocated for domain 0 regardless
710 * of the actual domain assignments in use.
713 printk(KERN_ERR "MM: invalid domain in supersection "
714 "mapping for 0x%08llx at 0x%08lx\n",
715 (long long)__pfn_to_phys((u64)md->pfn), addr);
719 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
720 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
721 " at 0x%08lx invalid alignment\n",
722 (long long)__pfn_to_phys((u64)md->pfn), addr);
727 * Shift bits [35:32] of address into bits [23:20] of PMD
730 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
732 pgd = pgd_offset_k(addr);
735 pud_t *pud = pud_offset(pgd, addr);
736 pmd_t *pmd = pmd_offset(pud, addr);
739 for (i = 0; i < 16; i++)
740 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
742 addr += SUPERSECTION_SIZE;
743 phys += SUPERSECTION_SIZE;
744 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
745 } while (addr != end);
747 #endif /* !CONFIG_ARM_LPAE */
750 * Create the page directory entries and any necessary
751 * page tables for the mapping specified by `md'. We
752 * are able to cope here with varying sizes and address
753 * offsets, and we take full advantage of sections and
756 static void __init create_mapping(struct map_desc *md)
758 unsigned long addr, length, end;
760 const struct mem_type *type;
763 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
764 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
765 " at 0x%08lx in user region\n",
766 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
770 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
771 md->virtual >= PAGE_OFFSET &&
772 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
773 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
774 " at 0x%08lx out of vmalloc space\n",
775 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
778 type = &mem_types[md->type];
780 #ifndef CONFIG_ARM_LPAE
782 * Catch 36-bit addresses
784 if (md->pfn >= 0x100000) {
785 create_36bit_mapping(md, type);
790 addr = md->virtual & PAGE_MASK;
791 phys = __pfn_to_phys(md->pfn);
792 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
794 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
795 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
796 "be mapped using pages, ignoring.\n",
797 (long long)__pfn_to_phys(md->pfn), addr);
801 pgd = pgd_offset_k(addr);
804 unsigned long next = pgd_addr_end(addr, end);
806 alloc_init_pud(pgd, addr, next, phys, type);
810 } while (pgd++, addr != end);
814 * Create the architecture specific mappings
816 void __init iotable_init(struct map_desc *io_desc, int nr)
819 struct vm_struct *vm;
820 struct static_vm *svm;
825 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
827 for (md = io_desc; nr; md++, nr--) {
831 vm->addr = (void *)(md->virtual & PAGE_MASK);
832 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
833 vm->phys_addr = __pfn_to_phys(md->pfn);
834 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
835 vm->flags |= VM_ARM_MTYPE(md->type);
836 vm->caller = iotable_init;
837 add_static_vm_early(svm++);
841 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
844 struct vm_struct *vm;
845 struct static_vm *svm;
847 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
850 vm->addr = (void *)addr;
852 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
854 add_static_vm_early(svm);
857 #ifndef CONFIG_ARM_LPAE
860 * The Linux PMD is made of two consecutive section entries covering 2MB
861 * (see definition in include/asm/pgtable-2level.h). However a call to
862 * create_mapping() may optimize static mappings by using individual
863 * 1MB section mappings. This leaves the actual PMD potentially half
864 * initialized if the top or bottom section entry isn't used, leaving it
865 * open to problems if a subsequent ioremap() or vmalloc() tries to use
866 * the virtual space left free by that unused section entry.
868 * Let's avoid the issue by inserting dummy vm entries covering the unused
869 * PMD halves once the static mappings are in place.
872 static void __init pmd_empty_section_gap(unsigned long addr)
874 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
877 static void __init fill_pmd_gaps(void)
879 struct static_vm *svm;
880 struct vm_struct *vm;
881 unsigned long addr, next = 0;
884 list_for_each_entry(svm, &static_vmlist, list) {
886 addr = (unsigned long)vm->addr;
891 * Check if this vm starts on an odd section boundary.
892 * If so and the first section entry for this PMD is free
893 * then we block the corresponding virtual address.
895 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
896 pmd = pmd_off_k(addr);
898 pmd_empty_section_gap(addr & PMD_MASK);
902 * Then check if this vm ends on an odd section boundary.
903 * If so and the second section entry for this PMD is empty
904 * then we block the corresponding virtual address.
907 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
908 pmd = pmd_off_k(addr) + 1;
910 pmd_empty_section_gap(addr);
913 /* no need to look at any vm entry until we hit the next PMD */
914 next = (addr + PMD_SIZE - 1) & PMD_MASK;
919 #define fill_pmd_gaps() do { } while (0)
922 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
923 static void __init pci_reserve_io(void)
925 struct static_vm *svm;
927 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
931 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
934 #define pci_reserve_io() do { } while (0)
937 #ifdef CONFIG_DEBUG_LL
938 void __init debug_ll_io_init(void)
942 debug_ll_addr(&map.pfn, &map.virtual);
943 if (!map.pfn || !map.virtual)
945 map.pfn = __phys_to_pfn(map.pfn);
946 map.virtual &= PAGE_MASK;
947 map.length = PAGE_SIZE;
948 map.type = MT_DEVICE;
949 create_mapping(&map);
953 static void * __initdata vmalloc_min =
954 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
957 * vmalloc=size forces the vmalloc area to be exactly 'size'
958 * bytes. This can be used to increase (or decrease) the vmalloc
959 * area - the default is 240m.
961 static int __init early_vmalloc(char *arg)
963 unsigned long vmalloc_reserve = memparse(arg, NULL);
965 if (vmalloc_reserve < SZ_16M) {
966 vmalloc_reserve = SZ_16M;
968 "vmalloc area too small, limiting to %luMB\n",
969 vmalloc_reserve >> 20);
972 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
973 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
975 "vmalloc area is too big, limiting to %luMB\n",
976 vmalloc_reserve >> 20);
979 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
982 early_param("vmalloc", early_vmalloc);
984 phys_addr_t arm_lowmem_limit __initdata = 0;
986 void __init sanity_check_meminfo(void)
988 int i, j, highmem = 0;
990 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
991 struct membank *bank = &meminfo.bank[j];
992 *bank = meminfo.bank[i];
994 if (bank->start > ULONG_MAX)
997 #ifdef CONFIG_HIGHMEM
998 if (__va(bank->start) >= vmalloc_min ||
999 __va(bank->start) < (void *)PAGE_OFFSET)
1002 bank->highmem = highmem;
1005 * Split those memory banks which are partially overlapping
1006 * the vmalloc area greatly simplifying things later.
1008 if (!highmem && __va(bank->start) < vmalloc_min &&
1009 bank->size > vmalloc_min - __va(bank->start)) {
1010 if (meminfo.nr_banks >= NR_BANKS) {
1011 printk(KERN_CRIT "NR_BANKS too low, "
1012 "ignoring high memory\n");
1014 memmove(bank + 1, bank,
1015 (meminfo.nr_banks - i) * sizeof(*bank));
1018 bank[1].size -= vmalloc_min - __va(bank->start);
1019 bank[1].start = __pa(vmalloc_min - 1) + 1;
1020 bank[1].highmem = highmem = 1;
1023 bank->size = vmalloc_min - __va(bank->start);
1026 bank->highmem = highmem;
1029 * Highmem banks not allowed with !CONFIG_HIGHMEM.
1032 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1033 "(!CONFIG_HIGHMEM).\n",
1034 (unsigned long long)bank->start,
1035 (unsigned long long)bank->start + bank->size - 1);
1040 * Check whether this memory bank would entirely overlap
1043 if (__va(bank->start) >= vmalloc_min ||
1044 __va(bank->start) < (void *)PAGE_OFFSET) {
1045 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1046 "(vmalloc region overlap).\n",
1047 (unsigned long long)bank->start,
1048 (unsigned long long)bank->start + bank->size - 1);
1053 * Check whether this memory bank would partially overlap
1056 if (__va(bank->start + bank->size - 1) >= vmalloc_min ||
1057 __va(bank->start + bank->size - 1) <= __va(bank->start)) {
1058 unsigned long newsize = vmalloc_min - __va(bank->start);
1059 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
1060 "to -%.8llx (vmalloc region overlap).\n",
1061 (unsigned long long)bank->start,
1062 (unsigned long long)bank->start + bank->size - 1,
1063 (unsigned long long)bank->start + newsize - 1);
1064 bank->size = newsize;
1067 if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
1068 arm_lowmem_limit = bank->start + bank->size;
1072 #ifdef CONFIG_HIGHMEM
1074 const char *reason = NULL;
1076 if (cache_is_vipt_aliasing()) {
1078 * Interactions between kmap and other mappings
1079 * make highmem support with aliasing VIPT caches
1082 reason = "with VIPT aliasing cache";
1085 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1087 while (j > 0 && meminfo.bank[j - 1].highmem)
1092 meminfo.nr_banks = j;
1093 high_memory = __va(arm_lowmem_limit - 1) + 1;
1094 memblock_set_current_limit(arm_lowmem_limit);
1097 static inline void prepare_page_table(void)
1103 * Clear out all the mappings below the kernel image.
1105 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1106 pmd_clear(pmd_off_k(addr));
1108 #ifdef CONFIG_XIP_KERNEL
1109 /* The XIP kernel is mapped in the module area -- skip over it */
1110 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1112 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1113 pmd_clear(pmd_off_k(addr));
1116 * Find the end of the first block of lowmem.
1118 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1119 if (end >= arm_lowmem_limit)
1120 end = arm_lowmem_limit;
1123 * Clear out all the kernel space mappings, except for the first
1124 * memory bank, up to the vmalloc region.
1126 for (addr = __phys_to_virt(end);
1127 addr < VMALLOC_START; addr += PMD_SIZE)
1128 pmd_clear(pmd_off_k(addr));
1131 #ifdef CONFIG_ARM_LPAE
1132 /* the first page is reserved for pgd */
1133 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1134 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1136 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1140 * Reserve the special regions of memory
1142 void __init arm_mm_memblock_reserve(void)
1145 * Reserve the page tables. These are already in use,
1146 * and can only be in node 0.
1148 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1150 #ifdef CONFIG_SA1111
1152 * Because of the SA1111 DMA bug, we want to preserve our
1153 * precious DMA-able memory...
1155 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1160 * Set up the device mappings. Since we clear out the page tables for all
1161 * mappings above VMALLOC_START, we will remove any debug device mappings.
1162 * This means you have to be careful how you debug this function, or any
1163 * called function. This means you can't use any function or debugging
1164 * method which may touch any device, otherwise the kernel _will_ crash.
1166 static void __init devicemaps_init(struct machine_desc *mdesc)
1168 struct map_desc map;
1173 * Allocate the vector page early.
1175 vectors = early_alloc(PAGE_SIZE);
1177 early_trap_init(vectors);
1179 for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1180 pmd_clear(pmd_off_k(addr));
1183 * Map the kernel if it is XIP.
1184 * It is always first in the modulearea.
1186 #ifdef CONFIG_XIP_KERNEL
1187 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1188 map.virtual = MODULES_VADDR;
1189 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1191 create_mapping(&map);
1195 * Map the cache flushing regions.
1198 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1199 map.virtual = FLUSH_BASE;
1201 map.type = MT_CACHECLEAN;
1202 create_mapping(&map);
1204 #ifdef FLUSH_BASE_MINICACHE
1205 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1206 map.virtual = FLUSH_BASE_MINICACHE;
1208 map.type = MT_MINICLEAN;
1209 create_mapping(&map);
1213 * Create a mapping for the machine vectors at the high-vectors
1214 * location (0xffff0000). If we aren't using high-vectors, also
1215 * create a mapping at the low-vectors virtual address.
1217 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1218 map.virtual = 0xffff0000;
1219 map.length = PAGE_SIZE;
1220 map.type = MT_HIGH_VECTORS;
1221 create_mapping(&map);
1223 if (!vectors_high()) {
1225 map.type = MT_LOW_VECTORS;
1226 create_mapping(&map);
1230 * Ask the machine support to map in the statically mapped devices.
1236 /* Reserve fixed i/o space in VMALLOC region */
1240 * Finally flush the caches and tlb to ensure that we're in a
1241 * consistent state wrt the writebuffer. This also ensures that
1242 * any write-allocated cache lines in the vector page are written
1243 * back. After this point, we can start to touch devices again.
1245 local_flush_tlb_all();
1249 static void __init kmap_init(void)
1251 #ifdef CONFIG_HIGHMEM
1252 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1253 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1257 static void __init map_lowmem(void)
1259 struct memblock_region *reg;
1261 /* Map all the lowmem memory banks. */
1262 for_each_memblock(memory, reg) {
1263 phys_addr_t start = reg->base;
1264 phys_addr_t end = start + reg->size;
1265 struct map_desc map;
1267 if (end > arm_lowmem_limit)
1268 end = arm_lowmem_limit;
1272 map.pfn = __phys_to_pfn(start);
1273 map.virtual = __phys_to_virt(start);
1274 map.length = end - start;
1275 map.type = MT_MEMORY;
1277 create_mapping(&map);
1282 * paging_init() sets up the page tables, initialises the zone memory
1283 * maps, and sets up the zero page, bad page and bad page tables.
1285 void __init paging_init(struct machine_desc *mdesc)
1289 memblock_set_current_limit(arm_lowmem_limit);
1291 build_mem_type_table();
1292 prepare_page_table();
1294 dma_contiguous_remap();
1295 devicemaps_init(mdesc);
1298 top_pmd = pmd_off_k(0xffff0000);
1300 /* allocate the zero page. */
1301 zero_page = early_alloc(PAGE_SIZE);
1305 empty_zero_page = virt_to_page(zero_page);
1306 __flush_dcache_page(NULL, empty_zero_page);