2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
15 #include <linux/mman.h>
16 #include <linux/nodemask.h>
18 #include <asm/mach-types.h>
19 #include <asm/setup.h>
20 #include <asm/sizes.h>
23 #include <asm/mach/arch.h>
24 #include <asm/mach/map.h>
28 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
30 extern void _stext, _etext, __data_start, _end;
31 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
34 * empty_zero_page is a special page that is used for
35 * zero-initialized data and COW.
37 struct page *empty_zero_page;
40 * The pmd table for the upper-most set of pages.
44 #define CPOLICY_UNCACHED 0
45 #define CPOLICY_BUFFERED 1
46 #define CPOLICY_WRITETHROUGH 2
47 #define CPOLICY_WRITEBACK 3
48 #define CPOLICY_WRITEALLOC 4
50 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
51 static unsigned int ecc_mask __initdata = 0;
53 pgprot_t pgprot_kernel;
55 EXPORT_SYMBOL(pgprot_user);
56 EXPORT_SYMBOL(pgprot_kernel);
59 const char policy[16];
65 static struct cachepolicy cache_policies[] __initdata = {
69 .pmd = PMD_SECT_UNCACHED,
74 .pmd = PMD_SECT_BUFFERED,
75 .pte = PTE_BUFFERABLE,
77 .policy = "writethrough",
82 .policy = "writeback",
85 .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
87 .policy = "writealloc",
90 .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
95 * These are useful for identifing cache coherency
96 * problems by allowing the cache or the cache and
97 * writebuffer to be turned off. (Note: the write
98 * buffer should not be on and the cache off).
100 static void __init early_cachepolicy(char **p)
104 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
105 int len = strlen(cache_policies[i].policy);
107 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
109 cr_alignment &= ~cache_policies[i].cr_mask;
110 cr_no_alignment &= ~cache_policies[i].cr_mask;
115 if (i == ARRAY_SIZE(cache_policies))
116 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
118 set_cr(cr_alignment);
120 __early_param("cachepolicy=", early_cachepolicy);
122 static void __init early_nocache(char **__unused)
124 char *p = "buffered";
125 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
126 early_cachepolicy(&p);
128 __early_param("nocache", early_nocache);
130 static void __init early_nowrite(char **__unused)
132 char *p = "uncached";
133 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
134 early_cachepolicy(&p);
136 __early_param("nowb", early_nowrite);
138 static void __init early_ecc(char **p)
140 if (memcmp(*p, "on", 2) == 0) {
141 ecc_mask = PMD_PROTECTION;
143 } else if (memcmp(*p, "off", 3) == 0) {
148 __early_param("ecc=", early_ecc);
150 static int __init noalign_setup(char *__unused)
152 cr_alignment &= ~CR_A;
153 cr_no_alignment &= ~CR_A;
154 set_cr(cr_alignment);
157 __setup("noalign", noalign_setup);
160 void adjust_cr(unsigned long mask, unsigned long set)
168 local_irq_save(flags);
170 cr_no_alignment = (cr_no_alignment & ~mask) | set;
171 cr_alignment = (cr_alignment & ~mask) | set;
173 set_cr((get_cr() & ~mask) | set);
175 local_irq_restore(flags);
179 static struct mem_type mem_types[] = {
181 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
183 .prot_l1 = PMD_TYPE_TABLE,
184 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_UNCACHED |
189 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
190 .domain = DOMAIN_KERNEL,
193 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
194 .domain = DOMAIN_KERNEL,
197 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
199 .prot_l1 = PMD_TYPE_TABLE,
200 .domain = DOMAIN_USER,
202 [MT_HIGH_VECTORS] = {
203 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
204 L_PTE_USER | L_PTE_EXEC,
205 .prot_l1 = PMD_TYPE_TABLE,
206 .domain = DOMAIN_USER,
209 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
210 .domain = DOMAIN_KERNEL,
213 .prot_sect = PMD_TYPE_SECT,
214 .domain = DOMAIN_KERNEL,
216 [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
217 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
219 .prot_l1 = PMD_TYPE_TABLE,
220 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_UNCACHED |
221 PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
225 [MT_NONSHARED_DEVICE] = {
226 .prot_l1 = PMD_TYPE_TABLE,
227 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_NONSHARED_DEV |
233 const struct mem_type *get_mem_type(unsigned int type)
235 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
239 * Adjust the PMD section entries according to the CPU in use.
241 static void __init build_mem_type_table(void)
243 struct cachepolicy *cp;
244 unsigned int cr = get_cr();
245 unsigned int user_pgprot, kern_pgprot;
246 int cpu_arch = cpu_architecture();
249 #if defined(CONFIG_CPU_DCACHE_DISABLE)
250 if (cachepolicy > CPOLICY_BUFFERED)
251 cachepolicy = CPOLICY_BUFFERED;
252 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
253 if (cachepolicy > CPOLICY_WRITETHROUGH)
254 cachepolicy = CPOLICY_WRITETHROUGH;
256 if (cpu_arch < CPU_ARCH_ARMv5) {
257 if (cachepolicy >= CPOLICY_WRITEALLOC)
258 cachepolicy = CPOLICY_WRITEBACK;
263 * ARMv5 and lower, bit 4 must be set for page tables.
264 * (was: cache "update-able on write" bit on ARM610)
265 * However, Xscale cores require this bit to be cleared.
267 if (cpu_is_xscale()) {
268 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
269 mem_types[i].prot_sect &= ~PMD_BIT4;
270 mem_types[i].prot_l1 &= ~PMD_BIT4;
272 } else if (cpu_arch < CPU_ARCH_ARMv6) {
273 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
274 if (mem_types[i].prot_l1)
275 mem_types[i].prot_l1 |= PMD_BIT4;
276 if (mem_types[i].prot_sect)
277 mem_types[i].prot_sect |= PMD_BIT4;
281 cp = &cache_policies[cachepolicy];
282 kern_pgprot = user_pgprot = cp->pte;
285 * Enable CPU-specific coherency if supported.
286 * (Only available on XSC3 at the moment.)
288 if (arch_is_coherent()) {
290 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
291 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
296 * ARMv6 and above have extended page tables.
298 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
300 * Mark cache clean areas and XIP ROM read only
301 * from SVC mode and no access from userspace.
303 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
304 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
305 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
308 * Mark the device area as "shared device"
310 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
311 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
315 * Mark memory with the "shared" attribute for SMP systems
317 user_pgprot |= L_PTE_SHARED;
318 kern_pgprot |= L_PTE_SHARED;
319 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
323 for (i = 0; i < 16; i++) {
324 unsigned long v = pgprot_val(protection_map[i]);
325 v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot;
326 protection_map[i] = __pgprot(v);
329 mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot;
330 mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot;
332 if (cpu_arch >= CPU_ARCH_ARMv5) {
335 * Only use write-through for non-SMP systems
337 mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
338 mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
341 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
344 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
345 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
346 L_PTE_DIRTY | L_PTE_WRITE |
347 L_PTE_EXEC | kern_pgprot);
349 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
350 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
351 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
352 mem_types[MT_ROM].prot_sect |= cp->pmd;
356 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
360 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
363 printk("Memory policy: ECC %sabled, Data cache %s\n",
364 ecc_mask ? "en" : "dis", cp->policy);
366 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
367 struct mem_type *t = &mem_types[i];
369 t->prot_l1 |= PMD_DOMAIN(t->domain);
371 t->prot_sect |= PMD_DOMAIN(t->domain);
375 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
377 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
378 unsigned long end, unsigned long pfn,
379 const struct mem_type *type)
383 if (pmd_none(*pmd)) {
384 pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
385 __pmd_populate(pmd, __pa(pte) | type->prot_l1);
388 pte = pte_offset_kernel(pmd, addr);
390 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
393 } while (pte++, addr += PAGE_SIZE, addr != end);
396 static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
397 unsigned long end, unsigned long phys,
398 const struct mem_type *type)
400 pmd_t *pmd = pmd_offset(pgd, addr);
403 * Try a section mapping - end, addr and phys must all be aligned
404 * to a section boundary. Note that PMDs refer to the individual
405 * L1 entries, whereas PGDs refer to a group of L1 entries making
406 * up one logical pointer to an L2 table.
408 if (((addr | end | phys) & ~SECTION_MASK) == 0) {
411 if (addr & SECTION_SIZE)
415 *pmd = __pmd(phys | type->prot_sect);
416 phys += SECTION_SIZE;
417 } while (pmd++, addr += SECTION_SIZE, addr != end);
422 * No need to loop; pte's aren't interested in the
423 * individual L1 entries.
425 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
429 static void __init create_36bit_mapping(struct map_desc *md,
430 const struct mem_type *type)
432 unsigned long phys, addr, length, end;
436 phys = (unsigned long)__pfn_to_phys(md->pfn);
437 length = PAGE_ALIGN(md->length);
439 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
440 printk(KERN_ERR "MM: CPU does not support supersection "
441 "mapping for 0x%08llx at 0x%08lx\n",
442 __pfn_to_phys((u64)md->pfn), addr);
446 /* N.B. ARMv6 supersections are only defined to work with domain 0.
447 * Since domain assignments can in fact be arbitrary, the
448 * 'domain == 0' check below is required to insure that ARMv6
449 * supersections are only allocated for domain 0 regardless
450 * of the actual domain assignments in use.
453 printk(KERN_ERR "MM: invalid domain in supersection "
454 "mapping for 0x%08llx at 0x%08lx\n",
455 __pfn_to_phys((u64)md->pfn), addr);
459 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
460 printk(KERN_ERR "MM: cannot create mapping for "
461 "0x%08llx at 0x%08lx invalid alignment\n",
462 __pfn_to_phys((u64)md->pfn), addr);
467 * Shift bits [35:32] of address into bits [23:20] of PMD
470 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
472 pgd = pgd_offset_k(addr);
475 pmd_t *pmd = pmd_offset(pgd, addr);
478 for (i = 0; i < 16; i++)
479 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
481 addr += SUPERSECTION_SIZE;
482 phys += SUPERSECTION_SIZE;
483 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
484 } while (addr != end);
488 * Create the page directory entries and any necessary
489 * page tables for the mapping specified by `md'. We
490 * are able to cope here with varying sizes and address
491 * offsets, and we take full advantage of sections and
494 void __init create_mapping(struct map_desc *md)
496 unsigned long phys, addr, length, end;
497 const struct mem_type *type;
500 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
501 printk(KERN_WARNING "BUG: not creating mapping for "
502 "0x%08llx at 0x%08lx in user region\n",
503 __pfn_to_phys((u64)md->pfn), md->virtual);
507 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
508 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
509 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
510 "overlaps vmalloc space\n",
511 __pfn_to_phys((u64)md->pfn), md->virtual);
514 type = &mem_types[md->type];
517 * Catch 36-bit addresses
519 if (md->pfn >= 0x100000) {
520 create_36bit_mapping(md, type);
525 phys = (unsigned long)__pfn_to_phys(md->pfn);
526 length = PAGE_ALIGN(md->length);
528 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
529 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
530 "be mapped using pages, ignoring.\n",
531 __pfn_to_phys(md->pfn), addr);
535 pgd = pgd_offset_k(addr);
538 unsigned long next = pgd_addr_end(addr, end);
540 alloc_init_section(pgd, addr, next, phys, type);
544 } while (pgd++, addr != end);
548 * Create the architecture specific mappings
550 void __init iotable_init(struct map_desc *io_desc, int nr)
554 for (i = 0; i < nr; i++)
555 create_mapping(io_desc + i);
558 static inline void prepare_page_table(struct meminfo *mi)
563 * Clear out all the mappings below the kernel image.
565 for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE)
566 pmd_clear(pmd_off_k(addr));
568 #ifdef CONFIG_XIP_KERNEL
569 /* The XIP kernel is mapped in the module area -- skip over it */
570 addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
572 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
573 pmd_clear(pmd_off_k(addr));
576 * Clear out all the kernel space mappings, except for the first
577 * memory bank, up to the end of the vmalloc region.
579 for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size);
580 addr < VMALLOC_END; addr += PGDIR_SIZE)
581 pmd_clear(pmd_off_k(addr));
585 * Reserve the various regions of node 0
587 void __init reserve_node_zero(pg_data_t *pgdat)
589 unsigned long res_size = 0;
592 * Register the kernel text and data with bootmem.
593 * Note that this can only be in node 0.
595 #ifdef CONFIG_XIP_KERNEL
596 reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start);
598 reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext);
602 * Reserve the page tables. These are already in use,
603 * and can only be in node 0.
605 reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
606 PTRS_PER_PGD * sizeof(pgd_t));
609 * Hmm... This should go elsewhere, but we really really need to
610 * stop things allocating the low memory; ideally we need a better
611 * implementation of GFP_DMA which does not assume that DMA-able
612 * memory starts at zero.
614 if (machine_is_integrator() || machine_is_cintegrator())
615 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
618 * These should likewise go elsewhere. They pre-reserve the
619 * screen memory region at the start of main system memory.
621 if (machine_is_edb7211())
622 res_size = 0x00020000;
623 if (machine_is_p720t())
624 res_size = 0x00014000;
626 /* H1940 and RX3715 need to reserve this for suspend */
628 if (machine_is_h1940() || machine_is_rx3715()) {
629 reserve_bootmem_node(pgdat, 0x30003000, 0x1000);
630 reserve_bootmem_node(pgdat, 0x30081000, 0x1000);
635 * Because of the SA1111 DMA bug, we want to preserve our
636 * precious DMA-able memory...
638 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
641 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size);
645 * Set up device the mappings. Since we clear out the page tables for all
646 * mappings above VMALLOC_END, we will remove any debug device mappings.
647 * This means you have to be careful how you debug this function, or any
648 * called function. This means you can't use any function or debugging
649 * method which may touch any device, otherwise the kernel _will_ crash.
651 static void __init devicemaps_init(struct machine_desc *mdesc)
658 * Allocate the vector page early.
660 vectors = alloc_bootmem_low_pages(PAGE_SIZE);
663 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
664 pmd_clear(pmd_off_k(addr));
667 * Map the kernel if it is XIP.
668 * It is always first in the modulearea.
670 #ifdef CONFIG_XIP_KERNEL
671 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
672 map.virtual = MODULE_START;
673 map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
675 create_mapping(&map);
679 * Map the cache flushing regions.
682 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
683 map.virtual = FLUSH_BASE;
685 map.type = MT_CACHECLEAN;
686 create_mapping(&map);
688 #ifdef FLUSH_BASE_MINICACHE
689 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
690 map.virtual = FLUSH_BASE_MINICACHE;
692 map.type = MT_MINICLEAN;
693 create_mapping(&map);
697 * Create a mapping for the machine vectors at the high-vectors
698 * location (0xffff0000). If we aren't using high-vectors, also
699 * create a mapping at the low-vectors virtual address.
701 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
702 map.virtual = 0xffff0000;
703 map.length = PAGE_SIZE;
704 map.type = MT_HIGH_VECTORS;
705 create_mapping(&map);
707 if (!vectors_high()) {
709 map.type = MT_LOW_VECTORS;
710 create_mapping(&map);
714 * Ask the machine support to map in the statically mapped devices.
720 * Finally flush the caches and tlb to ensure that we're in a
721 * consistent state wrt the writebuffer. This also ensures that
722 * any write-allocated cache lines in the vector page are written
723 * back. After this point, we can start to touch devices again.
725 local_flush_tlb_all();
730 * paging_init() sets up the page tables, initialises the zone memory
731 * maps, and sets up the zero page, bad page and bad page tables.
733 void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
737 build_mem_type_table();
738 prepare_page_table(mi);
740 devicemaps_init(mdesc);
742 top_pmd = pmd_off_k(0xffff0000);
745 * allocate the zero page. Note that we count on this going ok.
747 zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
748 memzero(zero_page, PAGE_SIZE);
749 empty_zero_page = virt_to_page(zero_page);
750 flush_dcache_page(empty_zero_page);
754 * In order to soft-boot, we need to insert a 1:1 mapping in place of
755 * the user-mode pages. This will then ensure that we have predictable
756 * results when turning the mmu off
758 void setup_mm_for_reboot(char mode)
760 unsigned long base_pmdval;
764 if (current->mm && current->mm->pgd)
765 pgd = current->mm->pgd;
769 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
770 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
771 base_pmdval |= PMD_BIT4;
773 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
774 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
777 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
778 pmd[0] = __pmd(pmdval);
779 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
780 flush_pmd_entry(pmd);