2 * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm1020e.
26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
28 #include <linux/linkage.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/hwcap.h>
33 #include <asm/pgtable-hwdef.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
37 #include "proc-macros.S"
40 * This is the maximum size of an area which will be invalidated
41 * using the single invalidate entry instructions. Anything larger
42 * than this, and we go for the whole cache.
44 * This value should be chosen such that we choose the cheapest
47 #define MAX_AREA_SIZE 32768
50 * The size of one data cache line.
52 #define CACHE_DLINESIZE 32
55 * The number of data cache segments.
57 #define CACHE_DSEGMENTS 16
60 * The number of lines in a cache segment.
62 #define CACHE_DENTRIES 64
65 * This is the size at which it becomes more efficient to
66 * clean the whole cache, rather than using the individual
67 * cache line maintainence instructions.
69 #define CACHE_DLIMIT 32768
73 * cpu_arm1020e_proc_init()
75 ENTRY(cpu_arm1020e_proc_init)
79 * cpu_arm1020e_proc_fin()
81 ENTRY(cpu_arm1020e_proc_fin)
82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
83 bic r0, r0, #0x1000 @ ...i............
84 bic r0, r0, #0x000e @ ............wca.
85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
89 * cpu_arm1020e_reset(loc)
91 * Perform a soft reset of the system. Put the CPU into the
92 * same state as it would be if it had been reset, and branch
93 * to what would be the reset vector.
95 * loc: location to jump to for soft reset
98 ENTRY(cpu_arm1020e_reset)
100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c7, c10, 4 @ drain WB
103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
105 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
106 bic ip, ip, #0x000f @ ............wcam
107 bic ip, ip, #0x1100 @ ...i...s........
108 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
112 * cpu_arm1020e_do_idle()
115 ENTRY(cpu_arm1020e_do_idle)
116 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
119 /* ================================= CACHE ================================ */
123 * flush_user_cache_all()
125 * Invalidate all cache entries in a particular address
128 ENTRY(arm1020e_flush_user_cache_all)
131 * flush_kern_cache_all()
133 * Clean and invalidate the entire cache.
135 ENTRY(arm1020e_flush_kern_cache_all)
139 #ifndef CONFIG_CPU_DCACHE_DISABLE
140 mcr p15, 0, ip, c7, c10, 4 @ drain WB
141 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
142 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
144 subs r3, r3, #1 << 26
145 bcs 2b @ entries 63 to 0
147 bcs 1b @ segments 15 to 0
150 #ifndef CONFIG_CPU_ICACHE_DISABLE
151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
157 * flush_user_cache_range(start, end, flags)
159 * Invalidate a range of cache entries in the specified
162 * - start - start address (inclusive)
163 * - end - end address (exclusive)
164 * - flags - vm_flags for this space
166 ENTRY(arm1020e_flush_user_cache_range)
168 sub r3, r1, r0 @ calculate total size
169 cmp r3, #CACHE_DLIMIT
170 bhs __flush_whole_cache
172 #ifndef CONFIG_CPU_DCACHE_DISABLE
173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
174 add r0, r0, #CACHE_DLINESIZE
179 #ifndef CONFIG_CPU_ICACHE_DISABLE
180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
182 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
186 * coherent_kern_range(start, end)
188 * Ensure coherency between the Icache and the Dcache in the
189 * region described by start. If you have non-snooping
190 * Harvard caches, you need to implement this function.
192 * - start - virtual start address
193 * - end - virtual end address
195 ENTRY(arm1020e_coherent_kern_range)
198 * coherent_user_range(start, end)
200 * Ensure coherency between the Icache and the Dcache in the
201 * region described by start. If you have non-snooping
202 * Harvard caches, you need to implement this function.
204 * - start - virtual start address
205 * - end - virtual end address
207 ENTRY(arm1020e_coherent_user_range)
209 bic r0, r0, #CACHE_DLINESIZE - 1
211 #ifndef CONFIG_CPU_DCACHE_DISABLE
212 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
214 #ifndef CONFIG_CPU_ICACHE_DISABLE
215 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
217 add r0, r0, #CACHE_DLINESIZE
220 mcr p15, 0, ip, c7, c10, 4 @ drain WB
224 * flush_kern_dcache_area(void *addr, size_t size)
226 * Ensure no D cache aliasing occurs, either with itself or
229 * - addr - kernel address
230 * - size - region size
232 ENTRY(arm1020e_flush_kern_dcache_area)
234 #ifndef CONFIG_CPU_DCACHE_DISABLE
236 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
237 add r0, r0, #CACHE_DLINESIZE
241 mcr p15, 0, ip, c7, c10, 4 @ drain WB
245 * dma_inv_range(start, end)
247 * Invalidate (discard) the specified virtual address range.
248 * May not write back any entries. If 'start' or 'end'
249 * are not cache line aligned, those lines must be written
252 * - start - virtual start address
253 * - end - virtual end address
257 arm1020e_dma_inv_range:
259 #ifndef CONFIG_CPU_DCACHE_DISABLE
260 tst r0, #CACHE_DLINESIZE - 1
261 bic r0, r0, #CACHE_DLINESIZE - 1
262 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
263 tst r1, #CACHE_DLINESIZE - 1
264 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
265 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
266 add r0, r0, #CACHE_DLINESIZE
270 mcr p15, 0, ip, c7, c10, 4 @ drain WB
274 * dma_clean_range(start, end)
276 * Clean the specified virtual address range.
278 * - start - virtual start address
279 * - end - virtual end address
283 arm1020e_dma_clean_range:
285 #ifndef CONFIG_CPU_DCACHE_DISABLE
286 bic r0, r0, #CACHE_DLINESIZE - 1
287 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
288 add r0, r0, #CACHE_DLINESIZE
292 mcr p15, 0, ip, c7, c10, 4 @ drain WB
296 * dma_flush_range(start, end)
298 * Clean and invalidate the specified virtual address range.
300 * - start - virtual start address
301 * - end - virtual end address
303 ENTRY(arm1020e_dma_flush_range)
305 #ifndef CONFIG_CPU_DCACHE_DISABLE
306 bic r0, r0, #CACHE_DLINESIZE - 1
307 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
308 add r0, r0, #CACHE_DLINESIZE
312 mcr p15, 0, ip, c7, c10, 4 @ drain WB
316 * dma_map_area(start, size, dir)
317 * - start - kernel virtual start address
318 * - size - size of region
319 * - dir - DMA direction
321 ENTRY(arm1020e_dma_map_area)
323 cmp r2, #DMA_TO_DEVICE
324 beq arm1020e_dma_clean_range
325 bcs arm1020e_dma_inv_range
326 b arm1020e_dma_flush_range
327 ENDPROC(arm1020e_dma_map_area)
330 * dma_unmap_area(start, size, dir)
331 * - start - kernel virtual start address
332 * - size - size of region
333 * - dir - DMA direction
335 ENTRY(arm1020e_dma_unmap_area)
337 ENDPROC(arm1020e_dma_unmap_area)
339 ENTRY(arm1020e_cache_fns)
340 .long arm1020e_flush_kern_cache_all
341 .long arm1020e_flush_user_cache_all
342 .long arm1020e_flush_user_cache_range
343 .long arm1020e_coherent_kern_range
344 .long arm1020e_coherent_user_range
345 .long arm1020e_flush_kern_dcache_area
346 .long arm1020e_dma_map_area
347 .long arm1020e_dma_unmap_area
348 .long arm1020e_dma_flush_range
351 ENTRY(cpu_arm1020e_dcache_clean_area)
352 #ifndef CONFIG_CPU_DCACHE_DISABLE
354 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
355 add r0, r0, #CACHE_DLINESIZE
356 subs r1, r1, #CACHE_DLINESIZE
361 /* =============================== PageTable ============================== */
364 * cpu_arm1020e_switch_mm(pgd)
366 * Set the translation base pointer to be as described by pgd.
368 * pgd: new page tables
371 ENTRY(cpu_arm1020e_switch_mm)
373 #ifndef CONFIG_CPU_DCACHE_DISABLE
374 mcr p15, 0, r3, c7, c10, 4
375 mov r1, #0xF @ 16 segments
376 1: mov r3, #0x3F @ 64 entries
377 2: mov ip, r3, LSL #26 @ shift up entry
378 orr ip, ip, r1, LSL #5 @ shift in/up index
379 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
383 bge 2b @ entries 3F to 0
386 bge 1b @ segments 15 to 0
390 #ifndef CONFIG_CPU_ICACHE_DISABLE
391 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
393 mcr p15, 0, r1, c7, c10, 4 @ drain WB
394 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
395 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
400 * cpu_arm1020e_set_pte(ptep, pte)
402 * Set a PTE and flush it out
405 ENTRY(cpu_arm1020e_set_pte_ext)
409 #ifndef CONFIG_CPU_DCACHE_DISABLE
410 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
412 #endif /* CONFIG_MMU */
417 .type __arm1020e_setup, #function
420 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
421 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
423 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
425 adr r5, arm1020e_crval
427 mrc p15, 0, r0, c1, c0 @ get control register v4
430 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
431 orr r0, r0, #0x4000 @ .R.. .... .... ....
434 .size __arm1020e_setup, . - __arm1020e_setup
438 * .RVI ZFRS BLDP WCAM
439 * .011 1001 ..11 0101
441 .type arm1020e_crval, #object
443 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
448 * Purpose : Function pointers used to access above functions - all calls
451 .type arm1020e_processor_functions, #object
452 arm1020e_processor_functions:
453 .word v4t_early_abort
455 .word cpu_arm1020e_proc_init
456 .word cpu_arm1020e_proc_fin
457 .word cpu_arm1020e_reset
458 .word cpu_arm1020e_do_idle
459 .word cpu_arm1020e_dcache_clean_area
460 .word cpu_arm1020e_switch_mm
461 .word cpu_arm1020e_set_pte_ext
462 .size arm1020e_processor_functions, . - arm1020e_processor_functions
466 .type cpu_arch_name, #object
469 .size cpu_arch_name, . - cpu_arch_name
471 .type cpu_elf_name, #object
474 .size cpu_elf_name, . - cpu_elf_name
476 .type cpu_arm1020e_name, #object
479 .size cpu_arm1020e_name, . - cpu_arm1020e_name
483 .section ".proc.info.init", #alloc, #execinstr
485 .type __arm1020e_proc_info,#object
486 __arm1020e_proc_info:
487 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
489 .long PMD_TYPE_SECT | \
491 PMD_SECT_AP_WRITE | \
493 .long PMD_TYPE_SECT | \
495 PMD_SECT_AP_WRITE | \
500 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
501 .long cpu_arm1020e_name
502 .long arm1020e_processor_functions
505 .long arm1020e_cache_fns
506 .size __arm1020e_proc_info, . - __arm1020e_proc_info