2 * linux/arch/arm/mm/proc-arm1026.S: MMU functions for ARM1026EJ-S
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 * These are the low level assembler for performing cache and TLB
15 * functions on the ARM1026EJ-S.
17 #include <linux/linkage.h>
18 #include <linux/config.h>
19 #include <linux/init.h>
20 #include <asm/assembler.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/pgtable-hwdef.h>
23 #include <asm/pgtable.h>
24 #include <asm/procinfo.h>
25 #include <asm/ptrace.h>
28 * This is the maximum size of an area which will be invalidated
29 * using the single invalidate entry instructions. Anything larger
30 * than this, and we go for the whole cache.
32 * This value should be chosen such that we choose the cheapest
35 #define MAX_AREA_SIZE 32768
38 * The size of one data cache line.
40 #define CACHE_DLINESIZE 32
43 * The number of data cache segments.
45 #define CACHE_DSEGMENTS 16
48 * The number of lines in a cache segment.
50 #define CACHE_DENTRIES 64
53 * This is the size at which it becomes more efficient to
54 * clean the whole cache, rather than using the individual
55 * cache line maintainence instructions.
57 #define CACHE_DLIMIT 32768
61 * cpu_arm1026_proc_init()
63 ENTRY(cpu_arm1026_proc_init)
67 * cpu_arm1026_proc_fin()
69 ENTRY(cpu_arm1026_proc_fin)
71 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
73 bl arm1026_flush_kern_cache_all
74 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
75 bic r0, r0, #0x1000 @ ...i............
76 bic r0, r0, #0x000e @ ............wca.
77 mcr p15, 0, r0, c1, c0, 0 @ disable caches
81 * cpu_arm1026_reset(loc)
83 * Perform a soft reset of the system. Put the CPU into the
84 * same state as it would be if it had been reset, and branch
85 * to what would be the reset vector.
87 * loc: location to jump to for soft reset
90 ENTRY(cpu_arm1026_reset)
92 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
93 mcr p15, 0, ip, c7, c10, 4 @ drain WB
95 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
97 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
98 bic ip, ip, #0x000f @ ............wcam
99 bic ip, ip, #0x1100 @ ...i...s........
100 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
104 * cpu_arm1026_do_idle()
107 ENTRY(cpu_arm1026_do_idle)
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
111 /* ================================= CACHE ================================ */
115 * flush_user_cache_all()
117 * Invalidate all cache entries in a particular address
120 ENTRY(arm1026_flush_user_cache_all)
123 * flush_kern_cache_all()
125 * Clean and invalidate the entire cache.
127 ENTRY(arm1026_flush_kern_cache_all)
131 #ifndef CONFIG_CPU_DCACHE_DISABLE
132 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
136 #ifndef CONFIG_CPU_ICACHE_DISABLE
137 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
143 * flush_user_cache_range(start, end, flags)
145 * Invalidate a range of cache entries in the specified
148 * - start - start address (inclusive)
149 * - end - end address (exclusive)
150 * - flags - vm_flags for this space
152 ENTRY(arm1026_flush_user_cache_range)
154 sub r3, r1, r0 @ calculate total size
155 cmp r3, #CACHE_DLIMIT
156 bhs __flush_whole_cache
158 #ifndef CONFIG_CPU_DCACHE_DISABLE
159 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
160 add r0, r0, #CACHE_DLINESIZE
165 #ifndef CONFIG_CPU_ICACHE_DISABLE
166 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
168 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
172 * coherent_kern_range(start, end)
174 * Ensure coherency between the Icache and the Dcache in the
175 * region described by start. If you have non-snooping
176 * Harvard caches, you need to implement this function.
178 * - start - virtual start address
179 * - end - virtual end address
181 ENTRY(arm1026_coherent_kern_range)
184 * coherent_user_range(start, end)
186 * Ensure coherency between the Icache and the Dcache in the
187 * region described by start. If you have non-snooping
188 * Harvard caches, you need to implement this function.
190 * - start - virtual start address
191 * - end - virtual end address
193 ENTRY(arm1026_coherent_user_range)
195 bic r0, r0, #CACHE_DLINESIZE - 1
197 #ifndef CONFIG_CPU_DCACHE_DISABLE
198 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
200 #ifndef CONFIG_CPU_ICACHE_DISABLE
201 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
203 add r0, r0, #CACHE_DLINESIZE
206 mcr p15, 0, ip, c7, c10, 4 @ drain WB
210 * flush_kern_dcache_page(void *page)
212 * Ensure no D cache aliasing occurs, either with itself or
215 * - page - page aligned address
217 ENTRY(arm1026_flush_kern_dcache_page)
219 #ifndef CONFIG_CPU_DCACHE_DISABLE
221 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
222 add r0, r0, #CACHE_DLINESIZE
226 mcr p15, 0, ip, c7, c10, 4 @ drain WB
230 * dma_inv_range(start, end)
232 * Invalidate (discard) the specified virtual address range.
233 * May not write back any entries. If 'start' or 'end'
234 * are not cache line aligned, those lines must be written
237 * - start - virtual start address
238 * - end - virtual end address
242 ENTRY(arm1026_dma_inv_range)
244 #ifndef CONFIG_CPU_DCACHE_DISABLE
245 tst r0, #CACHE_DLINESIZE - 1
246 bic r0, r0, #CACHE_DLINESIZE - 1
247 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
248 tst r1, #CACHE_DLINESIZE - 1
249 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
250 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
251 add r0, r0, #CACHE_DLINESIZE
255 mcr p15, 0, ip, c7, c10, 4 @ drain WB
259 * dma_clean_range(start, end)
261 * Clean the specified virtual address range.
263 * - start - virtual start address
264 * - end - virtual end address
268 ENTRY(arm1026_dma_clean_range)
270 #ifndef CONFIG_CPU_DCACHE_DISABLE
271 bic r0, r0, #CACHE_DLINESIZE - 1
272 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
273 add r0, r0, #CACHE_DLINESIZE
277 mcr p15, 0, ip, c7, c10, 4 @ drain WB
281 * dma_flush_range(start, end)
283 * Clean and invalidate the specified virtual address range.
285 * - start - virtual start address
286 * - end - virtual end address
288 ENTRY(arm1026_dma_flush_range)
290 #ifndef CONFIG_CPU_DCACHE_DISABLE
291 bic r0, r0, #CACHE_DLINESIZE - 1
292 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
293 add r0, r0, #CACHE_DLINESIZE
297 mcr p15, 0, ip, c7, c10, 4 @ drain WB
300 ENTRY(arm1026_cache_fns)
301 .long arm1026_flush_kern_cache_all
302 .long arm1026_flush_user_cache_all
303 .long arm1026_flush_user_cache_range
304 .long arm1026_coherent_kern_range
305 .long arm1026_coherent_user_range
306 .long arm1026_flush_kern_dcache_page
307 .long arm1026_dma_inv_range
308 .long arm1026_dma_clean_range
309 .long arm1026_dma_flush_range
312 ENTRY(cpu_arm1026_dcache_clean_area)
313 #ifndef CONFIG_CPU_DCACHE_DISABLE
315 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
316 add r0, r0, #CACHE_DLINESIZE
317 subs r1, r1, #CACHE_DLINESIZE
322 /* =============================== PageTable ============================== */
325 * cpu_arm1026_switch_mm(pgd)
327 * Set the translation base pointer to be as described by pgd.
329 * pgd: new page tables
332 ENTRY(cpu_arm1026_switch_mm)
335 #ifndef CONFIG_CPU_DCACHE_DISABLE
336 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
339 #ifndef CONFIG_CPU_ICACHE_DISABLE
340 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
342 mcr p15, 0, r1, c7, c10, 4 @ drain WB
343 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
344 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
349 * cpu_arm1026_set_pte(ptep, pte)
351 * Set a PTE and flush it out
354 ENTRY(cpu_arm1026_set_pte)
356 str r1, [r0], #-2048 @ linux version
358 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
360 bic r2, r1, #PTE_SMALL_AP_MASK
361 bic r2, r2, #PTE_TYPE_MASK
362 orr r2, r2, #PTE_TYPE_SMALL
364 tst r1, #L_PTE_USER @ User?
365 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
367 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
368 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
370 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
373 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
374 eor r3, r1, #0x0a @ C & small page?
378 str r2, [r0] @ hardware version
380 #ifndef CONFIG_CPU_DCACHE_DISABLE
381 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
383 #endif /* CONFIG_MMU */
389 .type __arm1026_setup, #function
392 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
393 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
395 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
396 mcr p15, 0, r4, c2, c0 @ load page table pointer
398 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
399 mov r0, #4 @ explicitly disable writeback
400 mcr p15, 7, r0, c15, c0, 0
402 mrc p15, 0, r0, c1, c0 @ get control register v4
403 ldr r5, arm1026_cr1_clear
405 ldr r5, arm1026_cr1_set
407 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
408 orr r0, r0, #0x4000 @ .R.. .... .... ....
411 .size __arm1026_setup, . - __arm1026_setup
415 * .RVI ZFRS BLDP WCAM
416 * .011 1001 ..11 0101
419 .type arm1026_cr1_clear, #object
420 .type arm1026_cr1_set, #object
429 * Purpose : Function pointers used to access above functions - all calls
432 .type arm1026_processor_functions, #object
433 arm1026_processor_functions:
434 .word v5t_early_abort
435 .word cpu_arm1026_proc_init
436 .word cpu_arm1026_proc_fin
437 .word cpu_arm1026_reset
438 .word cpu_arm1026_do_idle
439 .word cpu_arm1026_dcache_clean_area
440 .word cpu_arm1026_switch_mm
441 .word cpu_arm1026_set_pte
442 .size arm1026_processor_functions, . - arm1026_processor_functions
446 .type cpu_arch_name, #object
449 .size cpu_arch_name, . - cpu_arch_name
451 .type cpu_elf_name, #object
454 .size cpu_elf_name, . - cpu_elf_name
457 .type cpu_arm1026_name, #object
460 #ifndef CONFIG_CPU_ICACHE_DISABLE
463 #ifndef CONFIG_CPU_DCACHE_DISABLE
465 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
471 #ifndef CONFIG_CPU_BPREDICT_DISABLE
474 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
478 .size cpu_arm1026_name, . - cpu_arm1026_name
482 .section ".proc.info.init", #alloc, #execinstr
484 .type __arm1026_proc_info,#object
486 .long 0x4106a260 @ ARM 1026EJ-S (v5TEJ)
488 .long PMD_TYPE_SECT | \
490 PMD_SECT_AP_WRITE | \
495 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
496 .long cpu_arm1026_name
497 .long arm1026_processor_functions
500 .long arm1026_cache_fns
501 .size __arm1026_proc_info, . - __arm1026_proc_info