2 * linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920
4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm920.
26 * CONFIG_CPU_ARM920_CPU_IDLE -> nohlt
28 #include <linux/linkage.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/hwcap.h>
32 #include <asm/pgtable-hwdef.h>
33 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
36 #include "proc-macros.S"
39 * The size of one data cache line.
41 #define CACHE_DLINESIZE 32
44 * The number of data cache segments.
46 #define CACHE_DSEGMENTS 8
49 * The number of lines in a cache segment.
51 #define CACHE_DENTRIES 64
54 * This is the size at which it becomes more efficient to
55 * clean the whole cache, rather than using the individual
56 * cache line maintainence instructions.
58 #define CACHE_DLIMIT 65536
63 * cpu_arm920_proc_init()
65 ENTRY(cpu_arm920_proc_init)
69 * cpu_arm920_proc_fin()
71 ENTRY(cpu_arm920_proc_fin)
72 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
73 bic r0, r0, #0x1000 @ ...i............
74 bic r0, r0, #0x000e @ ............wca.
75 mcr p15, 0, r0, c1, c0, 0 @ disable caches
79 * cpu_arm920_reset(loc)
81 * Perform a soft reset of the system. Put the CPU into the
82 * same state as it would be if it had been reset, and branch
83 * to what would be the reset vector.
85 * loc: location to jump to for soft reset
88 ENTRY(cpu_arm920_reset)
90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c7, c10, 4 @ drain WB
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
95 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
96 bic ip, ip, #0x000f @ ............wcam
97 bic ip, ip, #0x1100 @ ...i...s........
98 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
102 * cpu_arm920_do_idle()
105 ENTRY(cpu_arm920_do_idle)
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
110 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
113 * flush_user_cache_all()
115 * Invalidate all cache entries in a particular address
118 ENTRY(arm920_flush_user_cache_all)
122 * flush_kern_cache_all()
124 * Clean and invalidate the entire cache.
126 ENTRY(arm920_flush_kern_cache_all)
130 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
131 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
133 subs r3, r3, #1 << 26
134 bcs 2b @ entries 63 to 0
136 bcs 1b @ segments 7 to 0
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
143 * flush_user_cache_range(start, end, flags)
145 * Invalidate a range of cache entries in the specified
148 * - start - start address (inclusive)
149 * - end - end address (exclusive)
150 * - flags - vm_flags for address space
152 ENTRY(arm920_flush_user_cache_range)
154 sub r3, r1, r0 @ calculate total size
155 cmp r3, #CACHE_DLIMIT
156 bhs __flush_whole_cache
158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
161 add r0, r0, #CACHE_DLINESIZE
165 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
169 * coherent_kern_range(start, end)
171 * Ensure coherency between the Icache and the Dcache in the
172 * region described by start, end. If you have non-snooping
173 * Harvard caches, you need to implement this function.
175 * - start - virtual start address
176 * - end - virtual end address
178 ENTRY(arm920_coherent_kern_range)
182 * coherent_user_range(start, end)
184 * Ensure coherency between the Icache and the Dcache in the
185 * region described by start, end. If you have non-snooping
186 * Harvard caches, you need to implement this function.
188 * - start - virtual start address
189 * - end - virtual end address
191 ENTRY(arm920_coherent_user_range)
192 bic r0, r0, #CACHE_DLINESIZE - 1
193 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
194 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
195 add r0, r0, #CACHE_DLINESIZE
198 mcr p15, 0, r0, c7, c10, 4 @ drain WB
202 * flush_kern_dcache_area(void *addr, size_t size)
204 * Ensure no D cache aliasing occurs, either with itself or
207 * - addr - kernel address
208 * - size - region size
210 ENTRY(arm920_flush_kern_dcache_area)
212 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
213 add r0, r0, #CACHE_DLINESIZE
217 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
218 mcr p15, 0, r0, c7, c10, 4 @ drain WB
222 * dma_inv_range(start, end)
224 * Invalidate (discard) the specified virtual address range.
225 * May not write back any entries. If 'start' or 'end'
226 * are not cache line aligned, those lines must be written
229 * - start - virtual start address
230 * - end - virtual end address
234 arm920_dma_inv_range:
235 tst r0, #CACHE_DLINESIZE - 1
236 bic r0, r0, #CACHE_DLINESIZE - 1
237 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
238 tst r1, #CACHE_DLINESIZE - 1
239 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
240 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
241 add r0, r0, #CACHE_DLINESIZE
244 mcr p15, 0, r0, c7, c10, 4 @ drain WB
248 * dma_clean_range(start, end)
250 * Clean the specified virtual address range.
252 * - start - virtual start address
253 * - end - virtual end address
257 arm920_dma_clean_range:
258 bic r0, r0, #CACHE_DLINESIZE - 1
259 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
260 add r0, r0, #CACHE_DLINESIZE
263 mcr p15, 0, r0, c7, c10, 4 @ drain WB
267 * dma_flush_range(start, end)
269 * Clean and invalidate the specified virtual address range.
271 * - start - virtual start address
272 * - end - virtual end address
274 ENTRY(arm920_dma_flush_range)
275 bic r0, r0, #CACHE_DLINESIZE - 1
276 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
277 add r0, r0, #CACHE_DLINESIZE
280 mcr p15, 0, r0, c7, c10, 4 @ drain WB
284 * dma_map_area(start, size, dir)
285 * - start - kernel virtual start address
286 * - size - size of region
287 * - dir - DMA direction
289 ENTRY(arm920_dma_map_area)
291 cmp r2, #DMA_TO_DEVICE
292 beq arm920_dma_clean_range
293 bcs arm920_dma_inv_range
294 b arm920_dma_flush_range
295 ENDPROC(arm920_dma_map_area)
298 * dma_unmap_area(start, size, dir)
299 * - start - kernel virtual start address
300 * - size - size of region
301 * - dir - DMA direction
303 ENTRY(arm920_dma_unmap_area)
305 ENDPROC(arm920_dma_unmap_area)
307 ENTRY(arm920_cache_fns)
308 .long arm920_flush_kern_cache_all
309 .long arm920_flush_user_cache_all
310 .long arm920_flush_user_cache_range
311 .long arm920_coherent_kern_range
312 .long arm920_coherent_user_range
313 .long arm920_flush_kern_dcache_area
314 .long arm920_dma_map_area
315 .long arm920_dma_unmap_area
316 .long arm920_dma_flush_range
321 ENTRY(cpu_arm920_dcache_clean_area)
322 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
323 add r0, r0, #CACHE_DLINESIZE
324 subs r1, r1, #CACHE_DLINESIZE
328 /* =============================== PageTable ============================== */
331 * cpu_arm920_switch_mm(pgd)
333 * Set the translation base pointer to be as described by pgd.
335 * pgd: new page tables
338 ENTRY(cpu_arm920_switch_mm)
341 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
342 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
344 @ && 'Clean & Invalidate whole DCache'
345 @ && Re-written to use Index Ops.
346 @ && Uses registers r1, r3 and ip
348 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
349 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
350 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
351 subs r3, r3, #1 << 26
352 bcs 2b @ entries 63 to 0
354 bcs 1b @ segments 7 to 0
356 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
357 mcr p15, 0, ip, c7, c10, 4 @ drain WB
358 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
359 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
364 * cpu_arm920_set_pte(ptep, pte, ext)
366 * Set a PTE and flush it out
369 ENTRY(cpu_arm920_set_pte_ext)
373 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
374 mcr p15, 0, r0, c7, c10, 4 @ drain WB
380 .type __arm920_setup, #function
383 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
384 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
386 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
390 mrc p15, 0, r0, c1, c0 @ get control register v4
394 .size __arm920_setup, . - __arm920_setup
398 * .RVI ZFRS BLDP WCAM
399 * ..11 0001 ..11 0101
402 .type arm920_crval, #object
404 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
409 * Purpose : Function pointers used to access above functions - all calls
412 .type arm920_processor_functions, #object
413 arm920_processor_functions:
414 .word v4t_early_abort
416 .word cpu_arm920_proc_init
417 .word cpu_arm920_proc_fin
418 .word cpu_arm920_reset
419 .word cpu_arm920_do_idle
420 .word cpu_arm920_dcache_clean_area
421 .word cpu_arm920_switch_mm
422 .word cpu_arm920_set_pte_ext
423 .size arm920_processor_functions, . - arm920_processor_functions
427 .type cpu_arch_name, #object
430 .size cpu_arch_name, . - cpu_arch_name
432 .type cpu_elf_name, #object
435 .size cpu_elf_name, . - cpu_elf_name
437 .type cpu_arm920_name, #object
440 .size cpu_arm920_name, . - cpu_arm920_name
444 .section ".proc.info.init", #alloc, #execinstr
446 .type __arm920_proc_info,#object
450 .long PMD_TYPE_SECT | \
451 PMD_SECT_BUFFERABLE | \
452 PMD_SECT_CACHEABLE | \
454 PMD_SECT_AP_WRITE | \
456 .long PMD_TYPE_SECT | \
458 PMD_SECT_AP_WRITE | \
463 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
464 .long cpu_arm920_name
465 .long arm920_processor_functions
468 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
469 .long arm920_cache_fns
473 .size __arm920_proc_info, . - __arm920_proc_info