2 * linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * Copyright (C) 2001 Altera Corporation
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * These are the low level assembler for performing cache and TLB
25 * functions on the arm922.
27 * CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
29 #include <linux/linkage.h>
30 #include <linux/init.h>
31 #include <asm/assembler.h>
32 #include <asm/hwcap.h>
33 #include <asm/pgtable-hwdef.h>
34 #include <asm/pgtable.h>
36 #include <asm/ptrace.h>
37 #include "proc-macros.S"
40 * The size of one data cache line.
42 #define CACHE_DLINESIZE 32
45 * The number of data cache segments.
47 #define CACHE_DSEGMENTS 4
50 * The number of lines in a cache segment.
52 #define CACHE_DENTRIES 64
55 * This is the size at which it becomes more efficient to
56 * clean the whole cache, rather than using the individual
57 * cache line maintainence instructions. (I think this should
60 #define CACHE_DLIMIT 8192
65 * cpu_arm922_proc_init()
67 ENTRY(cpu_arm922_proc_init)
71 * cpu_arm922_proc_fin()
73 ENTRY(cpu_arm922_proc_fin)
74 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
75 bic r0, r0, #0x1000 @ ...i............
76 bic r0, r0, #0x000e @ ............wca.
77 mcr p15, 0, r0, c1, c0, 0 @ disable caches
81 * cpu_arm922_reset(loc)
83 * Perform a soft reset of the system. Put the CPU into the
84 * same state as it would be if it had been reset, and branch
85 * to what would be the reset vector.
87 * loc: location to jump to for soft reset
90 ENTRY(cpu_arm922_reset)
92 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
93 mcr p15, 0, ip, c7, c10, 4 @ drain WB
95 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
97 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
98 bic ip, ip, #0x000f @ ............wcam
99 bic ip, ip, #0x1100 @ ...i...s........
100 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
104 * cpu_arm922_do_idle()
107 ENTRY(cpu_arm922_do_idle)
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
112 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
115 * flush_user_cache_all()
117 * Clean and invalidate all cache entries in a particular
120 ENTRY(arm922_flush_user_cache_all)
124 * flush_kern_cache_all()
126 * Clean and invalidate the entire cache.
128 ENTRY(arm922_flush_kern_cache_all)
132 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
133 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
135 subs r3, r3, #1 << 26
136 bcs 2b @ entries 63 to 0
138 bcs 1b @ segments 7 to 0
140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
141 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
145 * flush_user_cache_range(start, end, flags)
147 * Clean and invalidate a range of cache entries in the
148 * specified address range.
150 * - start - start address (inclusive)
151 * - end - end address (exclusive)
152 * - flags - vm_flags describing address space
154 ENTRY(arm922_flush_user_cache_range)
156 sub r3, r1, r0 @ calculate total size
157 cmp r3, #CACHE_DLIMIT
158 bhs __flush_whole_cache
160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
162 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
163 add r0, r0, #CACHE_DLINESIZE
167 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
171 * coherent_kern_range(start, end)
173 * Ensure coherency between the Icache and the Dcache in the
174 * region described by start, end. If you have non-snooping
175 * Harvard caches, you need to implement this function.
177 * - start - virtual start address
178 * - end - virtual end address
180 ENTRY(arm922_coherent_kern_range)
184 * coherent_user_range(start, end)
186 * Ensure coherency between the Icache and the Dcache in the
187 * region described by start, end. If you have non-snooping
188 * Harvard caches, you need to implement this function.
190 * - start - virtual start address
191 * - end - virtual end address
193 ENTRY(arm922_coherent_user_range)
194 bic r0, r0, #CACHE_DLINESIZE - 1
195 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
196 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
197 add r0, r0, #CACHE_DLINESIZE
200 mcr p15, 0, r0, c7, c10, 4 @ drain WB
204 * flush_kern_dcache_area(void *addr, size_t size)
206 * Ensure no D cache aliasing occurs, either with itself or
209 * - addr - kernel address
210 * - size - region size
212 ENTRY(arm922_flush_kern_dcache_area)
214 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
215 add r0, r0, #CACHE_DLINESIZE
219 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
220 mcr p15, 0, r0, c7, c10, 4 @ drain WB
224 * dma_inv_range(start, end)
226 * Invalidate (discard) the specified virtual address range.
227 * May not write back any entries. If 'start' or 'end'
228 * are not cache line aligned, those lines must be written
231 * - start - virtual start address
232 * - end - virtual end address
236 arm922_dma_inv_range:
237 tst r0, #CACHE_DLINESIZE - 1
238 bic r0, r0, #CACHE_DLINESIZE - 1
239 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
240 tst r1, #CACHE_DLINESIZE - 1
241 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
242 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
243 add r0, r0, #CACHE_DLINESIZE
246 mcr p15, 0, r0, c7, c10, 4 @ drain WB
250 * dma_clean_range(start, end)
252 * Clean the specified virtual address range.
254 * - start - virtual start address
255 * - end - virtual end address
259 arm922_dma_clean_range:
260 bic r0, r0, #CACHE_DLINESIZE - 1
261 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
262 add r0, r0, #CACHE_DLINESIZE
265 mcr p15, 0, r0, c7, c10, 4 @ drain WB
269 * dma_flush_range(start, end)
271 * Clean and invalidate the specified virtual address range.
273 * - start - virtual start address
274 * - end - virtual end address
276 ENTRY(arm922_dma_flush_range)
277 bic r0, r0, #CACHE_DLINESIZE - 1
278 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
279 add r0, r0, #CACHE_DLINESIZE
282 mcr p15, 0, r0, c7, c10, 4 @ drain WB
286 * dma_map_area(start, size, dir)
287 * - start - kernel virtual start address
288 * - size - size of region
289 * - dir - DMA direction
291 ENTRY(arm922_dma_map_area)
293 cmp r2, #DMA_TO_DEVICE
294 beq arm922_dma_clean_range
295 bcs arm922_dma_inv_range
296 b arm922_dma_flush_range
297 ENDPROC(arm922_dma_map_area)
300 * dma_unmap_area(start, size, dir)
301 * - start - kernel virtual start address
302 * - size - size of region
303 * - dir - DMA direction
305 ENTRY(arm922_dma_unmap_area)
307 ENDPROC(arm922_dma_unmap_area)
309 ENTRY(arm922_cache_fns)
310 .long arm922_flush_kern_cache_all
311 .long arm922_flush_user_cache_all
312 .long arm922_flush_user_cache_range
313 .long arm922_coherent_kern_range
314 .long arm922_coherent_user_range
315 .long arm922_flush_kern_dcache_area
316 .long arm922_dma_map_area
317 .long arm922_dma_unmap_area
318 .long arm922_dma_flush_range
323 ENTRY(cpu_arm922_dcache_clean_area)
324 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
325 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
326 add r0, r0, #CACHE_DLINESIZE
327 subs r1, r1, #CACHE_DLINESIZE
332 /* =============================== PageTable ============================== */
335 * cpu_arm922_switch_mm(pgd)
337 * Set the translation base pointer to be as described by pgd.
339 * pgd: new page tables
342 ENTRY(cpu_arm922_switch_mm)
345 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
346 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
348 @ && 'Clean & Invalidate whole DCache'
349 @ && Re-written to use Index Ops.
350 @ && Uses registers r1, r3 and ip
352 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 4 segments
353 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
354 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
355 subs r3, r3, #1 << 26
356 bcs 2b @ entries 63 to 0
358 bcs 1b @ segments 7 to 0
360 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
361 mcr p15, 0, ip, c7, c10, 4 @ drain WB
362 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
363 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
368 * cpu_arm922_set_pte_ext(ptep, pte, ext)
370 * Set a PTE and flush it out
373 ENTRY(cpu_arm922_set_pte_ext)
377 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
378 mcr p15, 0, r0, c7, c10, 4 @ drain WB
379 #endif /* CONFIG_MMU */
384 .type __arm922_setup, #function
387 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
388 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
390 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
394 mrc p15, 0, r0, c1, c0 @ get control register v4
398 .size __arm922_setup, . - __arm922_setup
402 * .RVI ZFRS BLDP WCAM
403 * ..11 0001 ..11 0101
406 .type arm922_crval, #object
408 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
413 * Purpose : Function pointers used to access above functions - all calls
416 .type arm922_processor_functions, #object
417 arm922_processor_functions:
418 .word v4t_early_abort
420 .word cpu_arm922_proc_init
421 .word cpu_arm922_proc_fin
422 .word cpu_arm922_reset
423 .word cpu_arm922_do_idle
424 .word cpu_arm922_dcache_clean_area
425 .word cpu_arm922_switch_mm
426 .word cpu_arm922_set_pte_ext
427 .size arm922_processor_functions, . - arm922_processor_functions
431 .type cpu_arch_name, #object
434 .size cpu_arch_name, . - cpu_arch_name
436 .type cpu_elf_name, #object
439 .size cpu_elf_name, . - cpu_elf_name
441 .type cpu_arm922_name, #object
444 .size cpu_arm922_name, . - cpu_arm922_name
448 .section ".proc.info.init", #alloc, #execinstr
450 .type __arm922_proc_info,#object
454 .long PMD_TYPE_SECT | \
455 PMD_SECT_BUFFERABLE | \
456 PMD_SECT_CACHEABLE | \
458 PMD_SECT_AP_WRITE | \
460 .long PMD_TYPE_SECT | \
462 PMD_SECT_AP_WRITE | \
467 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
468 .long cpu_arm922_name
469 .long arm922_processor_functions
472 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
473 .long arm922_cache_fns
477 .size __arm922_proc_info, . - __arm922_proc_info