2 * linux/arch/arm/mm/arm925.S: MMU functions for ARM925
4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Copyright (C) 2002-2003 MontaVista Software, Inc.
9 * Update for Linux-2.6 and cache flush improvements
10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
12 * hacked for non-paged-MM by Hyok S. Choi, 2004.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 * These are the low level assembler for performing cache and TLB
30 * functions on the arm925.
32 * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
34 * Some additional notes based on deciphering the TI TRM on OMAP-5910:
36 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
37 * entry mode" must be 0 to flush the entries in both segments
38 * at once. This is the default value. See TRM 2-20 and 2-24 for
41 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
42 * like the "Transparent mode" must be on for partial cache flushes
43 * to work in this mode. This mode only works with 16-bit external
44 * memory. See TRM 2-24 for more information.
46 * NOTE3: Write-back cache flushing seems to be flakey with devices using
47 * direct memory access, such as USB OHCI. The workaround is to use
48 * write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
49 * the default for OMAP-1510).
52 #include <linux/linkage.h>
53 #include <linux/config.h>
54 #include <linux/init.h>
55 #include <asm/assembler.h>
56 #include <asm/pgtable-hwdef.h>
57 #include <asm/pgtable.h>
58 #include <asm/procinfo.h>
60 #include <asm/ptrace.h>
61 #include "proc-macros.S"
64 * The size of one data cache line.
66 #define CACHE_DLINESIZE 16
69 * The number of data cache segments.
71 #define CACHE_DSEGMENTS 2
74 * The number of lines in a cache segment.
76 #define CACHE_DENTRIES 256
79 * This is the size at which it becomes more efficient to
80 * clean the whole cache, rather than using the individual
81 * cache line maintainence instructions.
83 #define CACHE_DLIMIT 8192
87 * cpu_arm925_proc_init()
89 ENTRY(cpu_arm925_proc_init)
93 * cpu_arm925_proc_fin()
95 ENTRY(cpu_arm925_proc_fin)
97 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
99 bl arm925_flush_kern_cache_all
100 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
101 bic r0, r0, #0x1000 @ ...i............
102 bic r0, r0, #0x000e @ ............wca.
103 mcr p15, 0, r0, c1, c0, 0 @ disable caches
107 * cpu_arm925_reset(loc)
109 * Perform a soft reset of the system. Put the CPU into the
110 * same state as it would be if it had been reset, and branch
111 * to what would be the reset vector.
113 * loc: location to jump to for soft reset
116 ENTRY(cpu_arm925_reset)
117 /* Send software reset to MPU and DSP */
119 orr ip, ip, #0x00fe0000
120 orr ip, ip, #0x0000ce00
125 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
126 mcr p15, 0, ip, c7, c10, 4 @ drain WB
128 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
130 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
131 bic ip, ip, #0x000f @ ............wcam
132 bic ip, ip, #0x1100 @ ...i...s........
133 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
137 * cpu_arm925_do_idle()
139 * Called with IRQs disabled
142 ENTRY(cpu_arm925_do_idle)
144 mrc p15, 0, r1, c1, c0, 0 @ Read control register
145 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
147 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
148 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
149 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
153 * flush_user_cache_all()
155 * Clean and invalidate all cache entries in a particular
158 ENTRY(arm925_flush_user_cache_all)
162 * flush_kern_cache_all()
164 * Clean and invalidate the entire cache.
166 ENTRY(arm925_flush_kern_cache_all)
170 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
171 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
173 /* Flush entries in both segments at once, see NOTE1 above */
174 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
175 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
177 bcs 2b @ entries 255 to 0
180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
181 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
185 * flush_user_cache_range(start, end, flags)
187 * Clean and invalidate a range of cache entries in the
188 * specified address range.
190 * - start - start address (inclusive)
191 * - end - end address (exclusive)
192 * - flags - vm_flags describing address space
194 ENTRY(arm925_flush_user_cache_range)
196 sub r3, r1, r0 @ calculate total size
197 cmp r3, #CACHE_DLIMIT
198 bgt __flush_whole_cache
200 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
201 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
202 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
203 add r0, r0, #CACHE_DLINESIZE
204 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
205 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
206 add r0, r0, #CACHE_DLINESIZE
208 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
209 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
210 add r0, r0, #CACHE_DLINESIZE
211 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
212 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
213 add r0, r0, #CACHE_DLINESIZE
218 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
222 * coherent_kern_range(start, end)
224 * Ensure coherency between the Icache and the Dcache in the
225 * region described by start, end. If you have non-snooping
226 * Harvard caches, you need to implement this function.
228 * - start - virtual start address
229 * - end - virtual end address
231 ENTRY(arm925_coherent_kern_range)
235 * coherent_user_range(start, end)
237 * Ensure coherency between the Icache and the Dcache in the
238 * region described by start, end. If you have non-snooping
239 * Harvard caches, you need to implement this function.
241 * - start - virtual start address
242 * - end - virtual end address
244 ENTRY(arm925_coherent_user_range)
245 bic r0, r0, #CACHE_DLINESIZE - 1
246 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
247 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
248 add r0, r0, #CACHE_DLINESIZE
251 mcr p15, 0, r0, c7, c10, 4 @ drain WB
255 * flush_kern_dcache_page(void *page)
257 * Ensure no D cache aliasing occurs, either with itself or
260 * - addr - page aligned address
262 ENTRY(arm925_flush_kern_dcache_page)
264 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
265 add r0, r0, #CACHE_DLINESIZE
269 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
270 mcr p15, 0, r0, c7, c10, 4 @ drain WB
274 * dma_inv_range(start, end)
276 * Invalidate (discard) the specified virtual address range.
277 * May not write back any entries. If 'start' or 'end'
278 * are not cache line aligned, those lines must be written
281 * - start - virtual start address
282 * - end - virtual end address
286 ENTRY(arm925_dma_inv_range)
287 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
288 tst r0, #CACHE_DLINESIZE - 1
289 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
290 tst r1, #CACHE_DLINESIZE - 1
291 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
293 bic r0, r0, #CACHE_DLINESIZE - 1
294 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
295 add r0, r0, #CACHE_DLINESIZE
298 mcr p15, 0, r0, c7, c10, 4 @ drain WB
302 * dma_clean_range(start, end)
304 * Clean the specified virtual address range.
306 * - start - virtual start address
307 * - end - virtual end address
311 ENTRY(arm925_dma_clean_range)
312 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
313 bic r0, r0, #CACHE_DLINESIZE - 1
314 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
315 add r0, r0, #CACHE_DLINESIZE
319 mcr p15, 0, r0, c7, c10, 4 @ drain WB
323 * dma_flush_range(start, end)
325 * Clean and invalidate the specified virtual address range.
327 * - start - virtual start address
328 * - end - virtual end address
330 ENTRY(arm925_dma_flush_range)
331 bic r0, r0, #CACHE_DLINESIZE - 1
333 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
334 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
336 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
338 add r0, r0, #CACHE_DLINESIZE
341 mcr p15, 0, r0, c7, c10, 4 @ drain WB
344 ENTRY(arm925_cache_fns)
345 .long arm925_flush_kern_cache_all
346 .long arm925_flush_user_cache_all
347 .long arm925_flush_user_cache_range
348 .long arm925_coherent_kern_range
349 .long arm925_coherent_user_range
350 .long arm925_flush_kern_dcache_page
351 .long arm925_dma_inv_range
352 .long arm925_dma_clean_range
353 .long arm925_dma_flush_range
355 ENTRY(cpu_arm925_dcache_clean_area)
356 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
357 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
358 add r0, r0, #CACHE_DLINESIZE
359 subs r1, r1, #CACHE_DLINESIZE
362 mcr p15, 0, r0, c7, c10, 4 @ drain WB
365 /* =============================== PageTable ============================== */
368 * cpu_arm925_switch_mm(pgd)
370 * Set the translation base pointer to be as described by pgd.
372 * pgd: new page tables
375 ENTRY(cpu_arm925_switch_mm)
378 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
379 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
381 /* Flush entries in bothe segments at once, see NOTE1 above */
382 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
383 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
385 bcs 2b @ entries 255 to 0
387 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
388 mcr p15, 0, ip, c7, c10, 4 @ drain WB
389 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
390 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
395 * cpu_arm925_set_pte(ptep, pte)
397 * Set a PTE and flush it out
400 ENTRY(cpu_arm925_set_pte)
402 str r1, [r0], #-2048 @ linux version
404 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
406 bic r2, r1, #PTE_SMALL_AP_MASK
407 bic r2, r2, #PTE_TYPE_MASK
408 orr r2, r2, #PTE_TYPE_SMALL
410 tst r1, #L_PTE_USER @ User?
411 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
413 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
414 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
416 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
419 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
420 eor r3, r2, #0x0a @ C & small page?
424 str r2, [r0] @ hardware version
426 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
427 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
429 mcr p15, 0, r0, c7, c10, 4 @ drain WB
430 #endif /* CONFIG_MMU */
435 .type __arm925_setup, #function
438 #if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE)
442 /* Transparent on, D-cache clean & flush mode. See NOTE2 above */
443 orr r0,r0,#1 << 1 @ transparent mode on
444 mcr p15, 0, r0, c15, c1, 0 @ write TI config register
447 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
448 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
450 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
453 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
454 mov r0, #4 @ disable write-back on caches explicitly
455 mcr p15, 7, r0, c15, c0, 0
459 mrc p15, 0, r0, c1, c0 @ get control register v4
462 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
463 orr r0, r0, #0x4000 @ .1.. .... .... ....
466 .size __arm925_setup, . - __arm925_setup
470 * .RVI ZFRS BLDP WCAM
471 * .011 0001 ..11 1101
474 .type arm925_crval, #object
476 crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
481 * Purpose : Function pointers used to access above functions - all calls
484 .type arm925_processor_functions, #object
485 arm925_processor_functions:
486 .word v4t_early_abort
487 .word cpu_arm925_proc_init
488 .word cpu_arm925_proc_fin
489 .word cpu_arm925_reset
490 .word cpu_arm925_do_idle
491 .word cpu_arm925_dcache_clean_area
492 .word cpu_arm925_switch_mm
493 .word cpu_arm925_set_pte
494 .size arm925_processor_functions, . - arm925_processor_functions
498 .type cpu_arch_name, #object
501 .size cpu_arch_name, . - cpu_arch_name
503 .type cpu_elf_name, #object
506 .size cpu_elf_name, . - cpu_elf_name
508 .type cpu_arm925_name, #object
511 .size cpu_arm925_name, . - cpu_arm925_name
515 .section ".proc.info.init", #alloc, #execinstr
517 .type __arm925_proc_info,#object
521 .long PMD_TYPE_SECT | \
523 PMD_SECT_AP_WRITE | \
528 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
529 .long cpu_arm925_name
530 .long arm925_processor_functions
533 .long arm925_cache_fns
534 .size __arm925_proc_info, . - __arm925_proc_info
536 .type __arm915_proc_info,#object
540 .long PMD_TYPE_SECT | \
542 PMD_SECT_AP_WRITE | \
547 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
548 .long cpu_arm925_name
549 .long arm925_processor_functions
552 .long arm925_cache_fns
553 .size __arm925_proc_info, . - __arm925_proc_info