2 * linux/arch/arm/mm/arm925.S: MMU functions for ARM925
4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Copyright (C) 2002-2003 MontaVista Software, Inc.
9 * Update for Linux-2.6 and cache flush improvements
10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
12 * hacked for non-paged-MM by Hyok S. Choi, 2004.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 * These are the low level assembler for performing cache and TLB
30 * functions on the arm925.
32 * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
34 * Some additional notes based on deciphering the TI TRM on OMAP-5910:
36 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
37 * entry mode" must be 0 to flush the entries in both segments
38 * at once. This is the default value. See TRM 2-20 and 2-24 for
41 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
42 * like the "Transparent mode" must be on for partial cache flushes
43 * to work in this mode. This mode only works with 16-bit external
44 * memory. See TRM 2-24 for more information.
46 * NOTE3: Write-back cache flushing seems to be flakey with devices using
47 * direct memory access, such as USB OHCI. The workaround is to use
48 * write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
49 * the default for OMAP-1510).
52 #include <linux/linkage.h>
53 #include <linux/init.h>
54 #include <asm/assembler.h>
55 #include <asm/hwcap.h>
56 #include <asm/pgtable-hwdef.h>
57 #include <asm/pgtable.h>
59 #include <asm/ptrace.h>
60 #include "proc-macros.S"
63 * The size of one data cache line.
65 #define CACHE_DLINESIZE 16
68 * The number of data cache segments.
70 #define CACHE_DSEGMENTS 2
73 * The number of lines in a cache segment.
75 #define CACHE_DENTRIES 256
78 * This is the size at which it becomes more efficient to
79 * clean the whole cache, rather than using the individual
80 * cache line maintainence instructions.
82 #define CACHE_DLIMIT 8192
86 * cpu_arm925_proc_init()
88 ENTRY(cpu_arm925_proc_init)
92 * cpu_arm925_proc_fin()
94 ENTRY(cpu_arm925_proc_fin)
95 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
96 bic r0, r0, #0x1000 @ ...i............
97 bic r0, r0, #0x000e @ ............wca.
98 mcr p15, 0, r0, c1, c0, 0 @ disable caches
102 * cpu_arm925_reset(loc)
104 * Perform a soft reset of the system. Put the CPU into the
105 * same state as it would be if it had been reset, and branch
106 * to what would be the reset vector.
108 * loc: location to jump to for soft reset
111 ENTRY(cpu_arm925_reset)
112 /* Send software reset to MPU and DSP */
114 orr ip, ip, #0x00fe0000
115 orr ip, ip, #0x0000ce00
120 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
121 mcr p15, 0, ip, c7, c10, 4 @ drain WB
123 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
125 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
126 bic ip, ip, #0x000f @ ............wcam
127 bic ip, ip, #0x1100 @ ...i...s........
128 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
132 * cpu_arm925_do_idle()
134 * Called with IRQs disabled
137 ENTRY(cpu_arm925_do_idle)
139 mrc p15, 0, r1, c1, c0, 0 @ Read control register
140 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
142 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
143 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
144 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
148 * flush_user_cache_all()
150 * Clean and invalidate all cache entries in a particular
153 ENTRY(arm925_flush_user_cache_all)
157 * flush_kern_cache_all()
159 * Clean and invalidate the entire cache.
161 ENTRY(arm925_flush_kern_cache_all)
165 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
166 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
168 /* Flush entries in both segments at once, see NOTE1 above */
169 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
170 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
172 bcs 2b @ entries 255 to 0
175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
176 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
180 * flush_user_cache_range(start, end, flags)
182 * Clean and invalidate a range of cache entries in the
183 * specified address range.
185 * - start - start address (inclusive)
186 * - end - end address (exclusive)
187 * - flags - vm_flags describing address space
189 ENTRY(arm925_flush_user_cache_range)
191 sub r3, r1, r0 @ calculate total size
192 cmp r3, #CACHE_DLIMIT
193 bgt __flush_whole_cache
195 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
196 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
197 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
198 add r0, r0, #CACHE_DLINESIZE
199 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
201 add r0, r0, #CACHE_DLINESIZE
203 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
204 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
205 add r0, r0, #CACHE_DLINESIZE
206 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
207 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
208 add r0, r0, #CACHE_DLINESIZE
213 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
217 * coherent_kern_range(start, end)
219 * Ensure coherency between the Icache and the Dcache in the
220 * region described by start, end. If you have non-snooping
221 * Harvard caches, you need to implement this function.
223 * - start - virtual start address
224 * - end - virtual end address
226 ENTRY(arm925_coherent_kern_range)
230 * coherent_user_range(start, end)
232 * Ensure coherency between the Icache and the Dcache in the
233 * region described by start, end. If you have non-snooping
234 * Harvard caches, you need to implement this function.
236 * - start - virtual start address
237 * - end - virtual end address
239 ENTRY(arm925_coherent_user_range)
240 bic r0, r0, #CACHE_DLINESIZE - 1
241 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
242 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
243 add r0, r0, #CACHE_DLINESIZE
246 mcr p15, 0, r0, c7, c10, 4 @ drain WB
250 * flush_kern_dcache_area(void *addr, size_t size)
252 * Ensure no D cache aliasing occurs, either with itself or
255 * - addr - kernel address
256 * - size - region size
258 ENTRY(arm925_flush_kern_dcache_area)
260 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
261 add r0, r0, #CACHE_DLINESIZE
265 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
266 mcr p15, 0, r0, c7, c10, 4 @ drain WB
270 * dma_inv_range(start, end)
272 * Invalidate (discard) the specified virtual address range.
273 * May not write back any entries. If 'start' or 'end'
274 * are not cache line aligned, those lines must be written
277 * - start - virtual start address
278 * - end - virtual end address
282 arm925_dma_inv_range:
283 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
284 tst r0, #CACHE_DLINESIZE - 1
285 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
286 tst r1, #CACHE_DLINESIZE - 1
287 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
289 bic r0, r0, #CACHE_DLINESIZE - 1
290 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
291 add r0, r0, #CACHE_DLINESIZE
294 mcr p15, 0, r0, c7, c10, 4 @ drain WB
298 * dma_clean_range(start, end)
300 * Clean the specified virtual address range.
302 * - start - virtual start address
303 * - end - virtual end address
307 arm925_dma_clean_range:
308 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
309 bic r0, r0, #CACHE_DLINESIZE - 1
310 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
311 add r0, r0, #CACHE_DLINESIZE
315 mcr p15, 0, r0, c7, c10, 4 @ drain WB
319 * dma_flush_range(start, end)
321 * Clean and invalidate the specified virtual address range.
323 * - start - virtual start address
324 * - end - virtual end address
326 ENTRY(arm925_dma_flush_range)
327 bic r0, r0, #CACHE_DLINESIZE - 1
329 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
330 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
332 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
334 add r0, r0, #CACHE_DLINESIZE
337 mcr p15, 0, r0, c7, c10, 4 @ drain WB
341 * dma_map_area(start, size, dir)
342 * - start - kernel virtual start address
343 * - size - size of region
344 * - dir - DMA direction
346 ENTRY(arm925_dma_map_area)
348 cmp r2, #DMA_TO_DEVICE
349 beq arm925_dma_clean_range
350 bcs arm925_dma_inv_range
351 b arm925_dma_flush_range
352 ENDPROC(arm925_dma_map_area)
355 * dma_unmap_area(start, size, dir)
356 * - start - kernel virtual start address
357 * - size - size of region
358 * - dir - DMA direction
360 ENTRY(arm925_dma_unmap_area)
362 ENDPROC(arm925_dma_unmap_area)
364 ENTRY(arm925_cache_fns)
365 .long arm925_flush_kern_cache_all
366 .long arm925_flush_user_cache_all
367 .long arm925_flush_user_cache_range
368 .long arm925_coherent_kern_range
369 .long arm925_coherent_user_range
370 .long arm925_flush_kern_dcache_area
371 .long arm925_dma_map_area
372 .long arm925_dma_unmap_area
373 .long arm925_dma_flush_range
375 ENTRY(cpu_arm925_dcache_clean_area)
376 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
377 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
378 add r0, r0, #CACHE_DLINESIZE
379 subs r1, r1, #CACHE_DLINESIZE
382 mcr p15, 0, r0, c7, c10, 4 @ drain WB
385 /* =============================== PageTable ============================== */
388 * cpu_arm925_switch_mm(pgd)
390 * Set the translation base pointer to be as described by pgd.
392 * pgd: new page tables
395 ENTRY(cpu_arm925_switch_mm)
398 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
399 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
401 /* Flush entries in bothe segments at once, see NOTE1 above */
402 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
403 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
405 bcs 2b @ entries 255 to 0
407 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
408 mcr p15, 0, ip, c7, c10, 4 @ drain WB
409 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
410 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
415 * cpu_arm925_set_pte_ext(ptep, pte, ext)
417 * Set a PTE and flush it out
420 ENTRY(cpu_arm925_set_pte_ext)
424 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
425 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
427 mcr p15, 0, r0, c7, c10, 4 @ drain WB
428 #endif /* CONFIG_MMU */
433 .type __arm925_setup, #function
436 #if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE)
440 /* Transparent on, D-cache clean & flush mode. See NOTE2 above */
441 orr r0,r0,#1 << 1 @ transparent mode on
442 mcr p15, 0, r0, c15, c1, 0 @ write TI config register
445 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
446 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
448 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
451 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
452 mov r0, #4 @ disable write-back on caches explicitly
453 mcr p15, 7, r0, c15, c0, 0
458 mrc p15, 0, r0, c1, c0 @ get control register v4
461 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
462 orr r0, r0, #0x4000 @ .1.. .... .... ....
465 .size __arm925_setup, . - __arm925_setup
469 * .RVI ZFRS BLDP WCAM
470 * .011 0001 ..11 1101
473 .type arm925_crval, #object
475 crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
480 * Purpose : Function pointers used to access above functions - all calls
483 .type arm925_processor_functions, #object
484 arm925_processor_functions:
485 .word v4t_early_abort
487 .word cpu_arm925_proc_init
488 .word cpu_arm925_proc_fin
489 .word cpu_arm925_reset
490 .word cpu_arm925_do_idle
491 .word cpu_arm925_dcache_clean_area
492 .word cpu_arm925_switch_mm
493 .word cpu_arm925_set_pte_ext
494 .size arm925_processor_functions, . - arm925_processor_functions
498 .type cpu_arch_name, #object
501 .size cpu_arch_name, . - cpu_arch_name
503 .type cpu_elf_name, #object
506 .size cpu_elf_name, . - cpu_elf_name
508 .type cpu_arm925_name, #object
511 .size cpu_arm925_name, . - cpu_arm925_name
515 .section ".proc.info.init", #alloc, #execinstr
517 .type __arm925_proc_info,#object
521 .long PMD_TYPE_SECT | \
523 PMD_SECT_AP_WRITE | \
525 .long PMD_TYPE_SECT | \
527 PMD_SECT_AP_WRITE | \
532 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
533 .long cpu_arm925_name
534 .long arm925_processor_functions
537 .long arm925_cache_fns
538 .size __arm925_proc_info, . - __arm925_proc_info
540 .type __arm915_proc_info,#object
544 .long PMD_TYPE_SECT | \
546 PMD_SECT_AP_WRITE | \
548 .long PMD_TYPE_SECT | \
550 PMD_SECT_AP_WRITE | \
555 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
556 .long cpu_arm925_name
557 .long arm925_processor_functions
560 .long arm925_cache_fns
561 .size __arm925_proc_info, . - __arm925_proc_info