2 * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
4 * Copyright (C) 1999-2001 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm926.
26 * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
28 #include <linux/linkage.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/hwcap.h>
32 #include <asm/pgtable-hwdef.h>
33 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
36 #include "proc-macros.S"
39 * This is the maximum size of an area which will be invalidated
40 * using the single invalidate entry instructions. Anything larger
41 * than this, and we go for the whole cache.
43 * This value should be chosen such that we choose the cheapest
46 #define CACHE_DLIMIT 16384
49 * the cache line size of the I and D cache
51 #define CACHE_DLINESIZE 32
55 * cpu_arm926_proc_init()
57 ENTRY(cpu_arm926_proc_init)
61 * cpu_arm926_proc_fin()
63 ENTRY(cpu_arm926_proc_fin)
64 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
65 bic r0, r0, #0x1000 @ ...i............
66 bic r0, r0, #0x000e @ ............wca.
67 mcr p15, 0, r0, c1, c0, 0 @ disable caches
71 * cpu_arm926_reset(loc)
73 * Perform a soft reset of the system. Put the CPU into the
74 * same state as it would be if it had been reset, and branch
75 * to what would be the reset vector.
77 * loc: location to jump to for soft reset
80 ENTRY(cpu_arm926_reset)
82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
83 mcr p15, 0, ip, c7, c10, 4 @ drain WB
85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
87 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
88 bic ip, ip, #0x000f @ ............wcam
89 bic ip, ip, #0x1100 @ ...i...s........
90 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
94 * cpu_arm926_do_idle()
96 * Called with IRQs disabled
99 ENTRY(cpu_arm926_do_idle)
101 mrc p15, 0, r1, c1, c0, 0 @ Read control register
102 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
104 mrs r3, cpsr @ Disable FIQs while Icache
105 orr ip, r3, #PSR_F_BIT @ is disabled
107 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
109 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
110 msr cpsr_c, r3 @ Restore FIQ state
114 * flush_user_cache_all()
116 * Clean and invalidate all cache entries in a particular
119 ENTRY(arm926_flush_user_cache_all)
123 * flush_kern_cache_all()
125 * Clean and invalidate the entire cache.
127 ENTRY(arm926_flush_kern_cache_all)
131 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
134 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
143 * flush_user_cache_range(start, end, flags)
145 * Clean and invalidate a range of cache entries in the
146 * specified address range.
148 * - start - start address (inclusive)
149 * - end - end address (exclusive)
150 * - flags - vm_flags describing address space
152 ENTRY(arm926_flush_user_cache_range)
154 sub r3, r1, r0 @ calculate total size
155 cmp r3, #CACHE_DLIMIT
156 bgt __flush_whole_cache
158 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
159 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
161 add r0, r0, #CACHE_DLINESIZE
162 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
163 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
164 add r0, r0, #CACHE_DLINESIZE
166 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
168 add r0, r0, #CACHE_DLINESIZE
169 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
170 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
171 add r0, r0, #CACHE_DLINESIZE
176 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
180 * coherent_kern_range(start, end)
182 * Ensure coherency between the Icache and the Dcache in the
183 * region described by start, end. If you have non-snooping
184 * Harvard caches, you need to implement this function.
186 * - start - virtual start address
187 * - end - virtual end address
189 ENTRY(arm926_coherent_kern_range)
193 * coherent_user_range(start, end)
195 * Ensure coherency between the Icache and the Dcache in the
196 * region described by start, end. If you have non-snooping
197 * Harvard caches, you need to implement this function.
199 * - start - virtual start address
200 * - end - virtual end address
202 ENTRY(arm926_coherent_user_range)
203 bic r0, r0, #CACHE_DLINESIZE - 1
204 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
205 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
206 add r0, r0, #CACHE_DLINESIZE
209 mcr p15, 0, r0, c7, c10, 4 @ drain WB
213 * flush_kern_dcache_area(void *addr, size_t size)
215 * Ensure no D cache aliasing occurs, either with itself or
218 * - addr - kernel address
219 * - size - region size
221 ENTRY(arm926_flush_kern_dcache_area)
223 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
224 add r0, r0, #CACHE_DLINESIZE
228 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
229 mcr p15, 0, r0, c7, c10, 4 @ drain WB
233 * dma_inv_range(start, end)
235 * Invalidate (discard) the specified virtual address range.
236 * May not write back any entries. If 'start' or 'end'
237 * are not cache line aligned, those lines must be written
240 * - start - virtual start address
241 * - end - virtual end address
245 arm926_dma_inv_range:
246 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
247 tst r0, #CACHE_DLINESIZE - 1
248 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
249 tst r1, #CACHE_DLINESIZE - 1
250 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
252 bic r0, r0, #CACHE_DLINESIZE - 1
253 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
254 add r0, r0, #CACHE_DLINESIZE
257 mcr p15, 0, r0, c7, c10, 4 @ drain WB
261 * dma_clean_range(start, end)
263 * Clean the specified virtual address range.
265 * - start - virtual start address
266 * - end - virtual end address
270 arm926_dma_clean_range:
271 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
272 bic r0, r0, #CACHE_DLINESIZE - 1
273 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
274 add r0, r0, #CACHE_DLINESIZE
278 mcr p15, 0, r0, c7, c10, 4 @ drain WB
282 * dma_flush_range(start, end)
284 * Clean and invalidate the specified virtual address range.
286 * - start - virtual start address
287 * - end - virtual end address
289 ENTRY(arm926_dma_flush_range)
290 bic r0, r0, #CACHE_DLINESIZE - 1
292 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
293 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
295 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
297 add r0, r0, #CACHE_DLINESIZE
300 mcr p15, 0, r0, c7, c10, 4 @ drain WB
304 * dma_map_area(start, size, dir)
305 * - start - kernel virtual start address
306 * - size - size of region
307 * - dir - DMA direction
309 ENTRY(arm926_dma_map_area)
311 cmp r2, #DMA_TO_DEVICE
312 beq arm926_dma_clean_range
313 bcs arm926_dma_inv_range
314 b arm926_dma_flush_range
315 ENDPROC(arm926_dma_map_area)
318 * dma_unmap_area(start, size, dir)
319 * - start - kernel virtual start address
320 * - size - size of region
321 * - dir - DMA direction
323 ENTRY(arm926_dma_unmap_area)
325 ENDPROC(arm926_dma_unmap_area)
327 ENTRY(arm926_cache_fns)
328 .long arm926_flush_kern_cache_all
329 .long arm926_flush_user_cache_all
330 .long arm926_flush_user_cache_range
331 .long arm926_coherent_kern_range
332 .long arm926_coherent_user_range
333 .long arm926_flush_kern_dcache_area
334 .long arm926_dma_map_area
335 .long arm926_dma_unmap_area
336 .long arm926_dma_flush_range
338 ENTRY(cpu_arm926_dcache_clean_area)
339 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
340 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
341 add r0, r0, #CACHE_DLINESIZE
342 subs r1, r1, #CACHE_DLINESIZE
345 mcr p15, 0, r0, c7, c10, 4 @ drain WB
348 /* =============================== PageTable ============================== */
351 * cpu_arm926_switch_mm(pgd)
353 * Set the translation base pointer to be as described by pgd.
355 * pgd: new page tables
358 ENTRY(cpu_arm926_switch_mm)
361 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
362 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
364 @ && 'Clean & Invalidate whole DCache'
365 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
368 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
369 mcr p15, 0, ip, c7, c10, 4 @ drain WB
370 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
371 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
376 * cpu_arm926_set_pte_ext(ptep, pte, ext)
378 * Set a PTE and flush it out
381 ENTRY(cpu_arm926_set_pte_ext)
385 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
386 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
388 mcr p15, 0, r0, c7, c10, 4 @ drain WB
394 .type __arm926_setup, #function
397 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
398 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
400 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
404 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
405 mov r0, #4 @ disable write-back on caches explicitly
406 mcr p15, 7, r0, c15, c0, 0
411 mrc p15, 0, r0, c1, c0 @ get control register v4
414 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
415 orr r0, r0, #0x4000 @ .1.. .... .... ....
418 .size __arm926_setup, . - __arm926_setup
422 * .RVI ZFRS BLDP WCAM
423 * .011 0001 ..11 0101
426 .type arm926_crval, #object
428 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
433 * Purpose : Function pointers used to access above functions - all calls
436 .type arm926_processor_functions, #object
437 arm926_processor_functions:
438 .word v5tj_early_abort
440 .word cpu_arm926_proc_init
441 .word cpu_arm926_proc_fin
442 .word cpu_arm926_reset
443 .word cpu_arm926_do_idle
444 .word cpu_arm926_dcache_clean_area
445 .word cpu_arm926_switch_mm
446 .word cpu_arm926_set_pte_ext
447 .size arm926_processor_functions, . - arm926_processor_functions
451 .type cpu_arch_name, #object
454 .size cpu_arch_name, . - cpu_arch_name
456 .type cpu_elf_name, #object
459 .size cpu_elf_name, . - cpu_elf_name
461 .type cpu_arm926_name, #object
464 .size cpu_arm926_name, . - cpu_arm926_name
468 .section ".proc.info.init", #alloc, #execinstr
470 .type __arm926_proc_info,#object
472 .long 0x41069260 @ ARM926EJ-S (v5TEJ)
474 .long PMD_TYPE_SECT | \
475 PMD_SECT_BUFFERABLE | \
476 PMD_SECT_CACHEABLE | \
478 PMD_SECT_AP_WRITE | \
480 .long PMD_TYPE_SECT | \
482 PMD_SECT_AP_WRITE | \
487 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
488 .long cpu_arm926_name
489 .long arm926_processor_functions
492 .long arm926_cache_fns
493 .size __arm926_proc_info, . - __arm926_proc_info