2 * linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
4 * Heavily based on proc-arm926.S
5 * Maintainer: Assaf Hoffman <hoffman@marvell.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/linkage.h>
23 #include <linux/init.h>
24 #include <asm/assembler.h>
25 #include <asm/hwcap.h>
26 #include <asm/pgtable-hwdef.h>
27 #include <asm/pgtable.h>
29 #include <asm/ptrace.h>
30 #include "proc-macros.S"
33 * This is the maximum size of an area which will be invalidated
34 * using the single invalidate entry instructions. Anything larger
35 * than this, and we go for the whole cache.
37 * This value should be chosen such that we choose the cheapest
40 #define CACHE_DLIMIT 16384
43 * the cache line size of the I and D cache
45 #define CACHE_DLINESIZE 32
54 .word __cache_params_loc
57 * cpu_feroceon_proc_init()
59 ENTRY(cpu_feroceon_proc_init)
60 mrc p15, 0, r0, c0, c0, 1 @ read cache type register
61 ldr r1, __cache_params
63 tst r0, #(1 << 16) @ get way
64 mov r0, r0, lsr #18 @ get cache size order
65 movne r3, #((4 - 1) << 30) @ 4-way
68 mov r2, r2, lsl r0 @ actual cache size
69 movne r2, r2, lsr #2 @ turned into # of sets
75 * cpu_feroceon_proc_fin()
77 ENTRY(cpu_feroceon_proc_fin)
79 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
81 bl feroceon_flush_kern_cache_all
83 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
84 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
86 mcr p15, 1, r0, c15, c9, 0 @ clean L2
87 mcr p15, 0, r0, c7, c10, 4 @ drain WB
90 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
91 bic r0, r0, #0x1000 @ ...i............
92 bic r0, r0, #0x000e @ ............wca.
93 mcr p15, 0, r0, c1, c0, 0 @ disable caches
97 * cpu_feroceon_reset(loc)
99 * Perform a soft reset of the system. Put the CPU into the
100 * same state as it would be if it had been reset, and branch
101 * to what would be the reset vector.
103 * loc: location to jump to for soft reset
106 ENTRY(cpu_feroceon_reset)
108 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
109 mcr p15, 0, ip, c7, c10, 4 @ drain WB
111 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
113 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
114 bic ip, ip, #0x000f @ ............wcam
115 bic ip, ip, #0x1100 @ ...i...s........
116 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
120 * cpu_feroceon_do_idle()
122 * Called with IRQs disabled
125 ENTRY(cpu_feroceon_do_idle)
127 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
128 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
132 * flush_user_cache_all()
134 * Clean and invalidate all cache entries in a particular
138 ENTRY(feroceon_flush_user_cache_all)
142 * flush_kern_cache_all()
144 * Clean and invalidate the entire cache.
146 ENTRY(feroceon_flush_kern_cache_all)
150 ldr r1, __cache_params
153 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
154 subs ip, ip, #(1 << 30) @ next way
156 subs r1, r1, #(1 << 5) @ next set
161 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
162 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
166 * flush_user_cache_range(start, end, flags)
168 * Clean and invalidate a range of cache entries in the
169 * specified address range.
171 * - start - start address (inclusive)
172 * - end - end address (exclusive)
173 * - flags - vm_flags describing address space
176 ENTRY(feroceon_flush_user_cache_range)
177 sub r3, r1, r0 @ calculate total size
178 cmp r3, #CACHE_DLIMIT
179 bgt __flush_whole_cache
181 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
182 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
183 add r0, r0, #CACHE_DLINESIZE
184 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
185 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
186 add r0, r0, #CACHE_DLINESIZE
191 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
195 * coherent_kern_range(start, end)
197 * Ensure coherency between the Icache and the Dcache in the
198 * region described by start, end. If you have non-snooping
199 * Harvard caches, you need to implement this function.
201 * - start - virtual start address
202 * - end - virtual end address
205 ENTRY(feroceon_coherent_kern_range)
209 * coherent_user_range(start, end)
211 * Ensure coherency between the Icache and the Dcache in the
212 * region described by start, end. If you have non-snooping
213 * Harvard caches, you need to implement this function.
215 * - start - virtual start address
216 * - end - virtual end address
218 ENTRY(feroceon_coherent_user_range)
219 bic r0, r0, #CACHE_DLINESIZE - 1
220 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
221 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
222 add r0, r0, #CACHE_DLINESIZE
225 mcr p15, 0, r0, c7, c10, 4 @ drain WB
229 * flush_kern_dcache_area(void *addr, size_t size)
231 * Ensure no D cache aliasing occurs, either with itself or
234 * - addr - kernel address
235 * - size - region size
238 ENTRY(feroceon_flush_kern_dcache_area)
240 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
241 add r0, r0, #CACHE_DLINESIZE
245 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
246 mcr p15, 0, r0, c7, c10, 4 @ drain WB
250 ENTRY(feroceon_range_flush_kern_dcache_area)
252 add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
253 orr r3, r2, #PSR_I_BIT
254 msr cpsr_c, r3 @ disable interrupts
255 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
256 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
257 msr cpsr_c, r2 @ restore interrupts
259 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
260 mcr p15, 0, r0, c7, c10, 4 @ drain WB
264 * dma_inv_range(start, end)
266 * Invalidate (discard) the specified virtual address range.
267 * May not write back any entries. If 'start' or 'end'
268 * are not cache line aligned, those lines must be written
271 * - start - virtual start address
272 * - end - virtual end address
277 feroceon_dma_inv_range:
278 tst r0, #CACHE_DLINESIZE - 1
279 bic r0, r0, #CACHE_DLINESIZE - 1
280 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
281 tst r1, #CACHE_DLINESIZE - 1
282 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
283 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
284 add r0, r0, #CACHE_DLINESIZE
287 mcr p15, 0, r0, c7, c10, 4 @ drain WB
291 feroceon_range_dma_inv_range:
293 tst r0, #CACHE_DLINESIZE - 1
294 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
295 tst r1, #CACHE_DLINESIZE - 1
296 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
298 subne r1, r1, #1 @ top address is inclusive
299 orr r3, r2, #PSR_I_BIT
300 msr cpsr_c, r3 @ disable interrupts
301 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
302 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
303 msr cpsr_c, r2 @ restore interrupts
307 * dma_clean_range(start, end)
309 * Clean the specified virtual address range.
311 * - start - virtual start address
312 * - end - virtual end address
317 feroceon_dma_clean_range:
318 bic r0, r0, #CACHE_DLINESIZE - 1
319 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
320 add r0, r0, #CACHE_DLINESIZE
323 mcr p15, 0, r0, c7, c10, 4 @ drain WB
327 feroceon_range_dma_clean_range:
330 subne r1, r1, #1 @ top address is inclusive
331 orr r3, r2, #PSR_I_BIT
332 msr cpsr_c, r3 @ disable interrupts
333 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
334 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
335 msr cpsr_c, r2 @ restore interrupts
336 mcr p15, 0, r0, c7, c10, 4 @ drain WB
340 * dma_flush_range(start, end)
342 * Clean and invalidate the specified virtual address range.
344 * - start - virtual start address
345 * - end - virtual end address
348 ENTRY(feroceon_dma_flush_range)
349 bic r0, r0, #CACHE_DLINESIZE - 1
350 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
351 add r0, r0, #CACHE_DLINESIZE
354 mcr p15, 0, r0, c7, c10, 4 @ drain WB
358 ENTRY(feroceon_range_dma_flush_range)
361 subne r1, r1, #1 @ top address is inclusive
362 orr r3, r2, #PSR_I_BIT
363 msr cpsr_c, r3 @ disable interrupts
364 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
365 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
366 msr cpsr_c, r2 @ restore interrupts
367 mcr p15, 0, r0, c7, c10, 4 @ drain WB
371 * dma_map_area(start, size, dir)
372 * - start - kernel virtual start address
373 * - size - size of region
374 * - dir - DMA direction
376 ENTRY(feroceon_dma_map_area)
378 cmp r2, #DMA_TO_DEVICE
379 beq feroceon_dma_clean_range
380 bcs feroceon_dma_inv_range
381 b feroceon_dma_flush_range
382 ENDPROC(feroceon_dma_map_area)
385 * dma_map_area(start, size, dir)
386 * - start - kernel virtual start address
387 * - size - size of region
388 * - dir - DMA direction
390 ENTRY(feroceon_range_dma_map_area)
392 cmp r2, #DMA_TO_DEVICE
393 beq feroceon_range_dma_clean_range
394 bcs feroceon_range_dma_inv_range
395 b feroceon_range_dma_flush_range
396 ENDPROC(feroceon_range_dma_map_area)
399 * dma_unmap_area(start, size, dir)
400 * - start - kernel virtual start address
401 * - size - size of region
402 * - dir - DMA direction
404 ENTRY(feroceon_dma_unmap_area)
406 ENDPROC(feroceon_dma_unmap_area)
408 ENTRY(feroceon_cache_fns)
409 .long feroceon_flush_kern_cache_all
410 .long feroceon_flush_user_cache_all
411 .long feroceon_flush_user_cache_range
412 .long feroceon_coherent_kern_range
413 .long feroceon_coherent_user_range
414 .long feroceon_flush_kern_dcache_area
415 .long feroceon_dma_map_area
416 .long feroceon_dma_unmap_area
417 .long feroceon_dma_flush_range
419 ENTRY(feroceon_range_cache_fns)
420 .long feroceon_flush_kern_cache_all
421 .long feroceon_flush_user_cache_all
422 .long feroceon_flush_user_cache_range
423 .long feroceon_coherent_kern_range
424 .long feroceon_coherent_user_range
425 .long feroceon_range_flush_kern_dcache_area
426 .long feroceon_range_dma_map_area
427 .long feroceon_dma_unmap_area
428 .long feroceon_range_dma_flush_range
431 ENTRY(cpu_feroceon_dcache_clean_area)
432 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
433 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
437 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
438 add r0, r0, #CACHE_DLINESIZE
439 subs r1, r1, #CACHE_DLINESIZE
441 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
442 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
443 1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
444 add r2, r2, #CACHE_DLINESIZE
445 subs r3, r3, #CACHE_DLINESIZE
448 mcr p15, 0, r0, c7, c10, 4 @ drain WB
451 /* =============================== PageTable ============================== */
454 * cpu_feroceon_switch_mm(pgd)
456 * Set the translation base pointer to be as described by pgd.
458 * pgd: new page tables
461 ENTRY(cpu_feroceon_switch_mm)
464 * Note: we wish to call __flush_whole_cache but we need to preserve
465 * lr to do so. The only way without touching main memory is to
466 * use r2 which is normally used to test the VM_EXEC flag, and
467 * compensate locally for the skipped ops if it is not set.
469 mov r2, lr @ abuse r2 to preserve lr
470 bl __flush_whole_cache
471 @ if r2 contains the VM_EXEC bit then the next 2 ops are done already
473 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
474 mcreq p15, 0, ip, c7, c10, 4 @ drain WB
476 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
477 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
484 * cpu_feroceon_set_pte_ext(ptep, pte, ext)
486 * Set a PTE and flush it out
489 ENTRY(cpu_feroceon_set_pte_ext)
491 armv3_set_pte_ext wc_disable=0
493 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
494 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
495 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
496 mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry
498 mcr p15, 0, r0, c7, c10, 4 @ drain WB
504 .type __feroceon_setup, #function
507 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
508 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
510 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
513 adr r5, feroceon_crval
515 mrc p15, 0, r0, c1, c0 @ get control register v4
519 .size __feroceon_setup, . - __feroceon_setup
524 * .RVI UFRS BLDP WCAM
525 * .011 .001 ..11 0101
528 .type feroceon_crval, #object
530 crval clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134
535 * Purpose : Function pointers used to access above functions - all calls
538 .type feroceon_processor_functions, #object
539 feroceon_processor_functions:
540 .word v5t_early_abort
542 .word cpu_feroceon_proc_init
543 .word cpu_feroceon_proc_fin
544 .word cpu_feroceon_reset
545 .word cpu_feroceon_do_idle
546 .word cpu_feroceon_dcache_clean_area
547 .word cpu_feroceon_switch_mm
548 .word cpu_feroceon_set_pte_ext
549 .size feroceon_processor_functions, . - feroceon_processor_functions
553 .type cpu_arch_name, #object
556 .size cpu_arch_name, . - cpu_arch_name
558 .type cpu_elf_name, #object
561 .size cpu_elf_name, . - cpu_elf_name
563 .type cpu_feroceon_name, #object
566 .size cpu_feroceon_name, . - cpu_feroceon_name
568 .type cpu_88fr531_name, #object
570 .asciz "Feroceon 88FR531-vd"
571 .size cpu_88fr531_name, . - cpu_88fr531_name
573 .type cpu_88fr571_name, #object
575 .asciz "Feroceon 88FR571-vd"
576 .size cpu_88fr571_name, . - cpu_88fr571_name
578 .type cpu_88fr131_name, #object
580 .asciz "Feroceon 88FR131"
581 .size cpu_88fr131_name, . - cpu_88fr131_name
585 .section ".proc.info.init", #alloc, #execinstr
587 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
588 .type __feroceon_old_id_proc_info,#object
589 __feroceon_old_id_proc_info:
592 .long PMD_TYPE_SECT | \
593 PMD_SECT_BUFFERABLE | \
594 PMD_SECT_CACHEABLE | \
596 PMD_SECT_AP_WRITE | \
598 .long PMD_TYPE_SECT | \
600 PMD_SECT_AP_WRITE | \
605 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
606 .long cpu_feroceon_name
607 .long feroceon_processor_functions
609 .long feroceon_user_fns
610 .long feroceon_cache_fns
611 .size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
614 .type __88fr531_proc_info,#object
618 .long PMD_TYPE_SECT | \
619 PMD_SECT_BUFFERABLE | \
620 PMD_SECT_CACHEABLE | \
622 PMD_SECT_AP_WRITE | \
624 .long PMD_TYPE_SECT | \
626 PMD_SECT_AP_WRITE | \
631 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
632 .long cpu_88fr531_name
633 .long feroceon_processor_functions
635 .long feroceon_user_fns
636 .long feroceon_cache_fns
637 .size __88fr531_proc_info, . - __88fr531_proc_info
639 .type __88fr571_proc_info,#object
643 .long PMD_TYPE_SECT | \
644 PMD_SECT_BUFFERABLE | \
645 PMD_SECT_CACHEABLE | \
647 PMD_SECT_AP_WRITE | \
649 .long PMD_TYPE_SECT | \
651 PMD_SECT_AP_WRITE | \
656 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
657 .long cpu_88fr571_name
658 .long feroceon_processor_functions
660 .long feroceon_user_fns
661 .long feroceon_range_cache_fns
662 .size __88fr571_proc_info, . - __88fr571_proc_info
664 .type __88fr131_proc_info,#object
668 .long PMD_TYPE_SECT | \
669 PMD_SECT_BUFFERABLE | \
670 PMD_SECT_CACHEABLE | \
672 PMD_SECT_AP_WRITE | \
674 .long PMD_TYPE_SECT | \
676 PMD_SECT_AP_WRITE | \
681 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
682 .long cpu_88fr131_name
683 .long feroceon_processor_functions
685 .long feroceon_user_fns
686 .long feroceon_range_cache_fns
687 .size __88fr131_proc_info, . - __88fr131_proc_info