2 * We need constants.h for:
7 #include <asm/asm-offsets.h>
8 #include <asm/thread_info.h>
11 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
13 .macro vma_vm_mm, rd, rn
14 ldr \rd, [\rn, #VMA_VM_MM]
18 * vma_vm_flags - get vma->vm_flags
20 .macro vma_vm_flags, rd, rn
21 ldr \rd, [\rn, #VMA_VM_FLAGS]
25 ldr \rd, [\rn, #TI_TASK]
26 ldr \rd, [\rd, #TSK_ACTIVE_MM]
30 * act_mm - get current->active_mm
35 ldr \rd, [\rd, #TI_TASK]
36 ldr \rd, [\rd, #TSK_ACTIVE_MM]
40 * mmid - get context id from mm pointer (mm->context.id)
43 ldr \rd, [\rn, #MM_CONTEXT_ID]
47 * mask_asid - mask the ASID from the context ID
53 .macro crval, clear, mmuset, ucset
64 * cache_line_size - get the cache line size from the CSIDR register
65 * (available on ARMv7+). It assumes that the CSSR register was configured
66 * to access the L1 data cache CSIDR.
68 .macro dcache_line_size, reg, tmp
69 mrc p15, 1, \tmp, c0, c0, 0 @ read CSIDR
70 and \tmp, \tmp, #7 @ cache line size encoding
71 mov \reg, #16 @ size offset
72 mov \reg, \reg, lsl \tmp @ actual cache line size
77 * Sanity check the PTE configuration for the code below - which makes
78 * certain assumptions about how these bits are layed out.
81 #if L_PTE_SHARED != PTE_EXT_SHARED
82 #error PTE shared bit mismatch
84 #if L_PTE_BUFFERABLE != PTE_BUFFERABLE
85 #error PTE bufferable bit mismatch
87 #if L_PTE_CACHEABLE != PTE_CACHEABLE
88 #error PTE cacheable bit mismatch
90 #if (L_PTE_EXEC+L_PTE_USER+L_PTE_WRITE+L_PTE_DIRTY+L_PTE_YOUNG+\
91 L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
92 #error Invalid Linux PTE bit settings
94 #endif /* CONFIG_MMU */
97 * The ARMv6 and ARMv7 set_pte_ext translation function.
99 * Permission translation:
100 * YUWD APX AP1 AP0 SVC User
101 * 0xxx 0 0 0 no acc no acc
102 * 100x 1 0 1 r/o no acc
103 * 10x0 1 0 1 r/o no acc
104 * 1011 0 0 1 r/w no acc
109 .macro armv6_mt_table pfx
111 .long 0x00 @ L_PTE_MT_UNCACHED
112 .long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
113 .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
114 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
115 .long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
117 .long 0x00 @ L_PTE_MT_MINICACHE (not present)
118 .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
120 .long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
122 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
123 .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
129 .macro armv6_set_pte_ext pfx
130 str r1, [r0], #-2048 @ linux version
132 bic r3, r1, #0x000003fc
133 bic r3, r3, #PTE_TYPE_MASK
135 orr r3, r3, #PTE_EXT_AP0 | 2
137 adr ip, \pfx\()_mt_table
138 and r2, r1, #L_PTE_MT_MASK
142 tstne r1, #L_PTE_DIRTY
143 orreq r3, r3, #PTE_EXT_APX
146 orrne r3, r3, #PTE_EXT_AP1
147 tstne r3, #PTE_EXT_APX
148 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
151 orreq r3, r3, #PTE_EXT_XN
156 tstne r1, #L_PTE_PRESENT
160 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
165 * The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
166 * covering most CPUs except Xscale and Xscale 3.
168 * Permission translation:
170 * 0xxx 0x00 no acc no acc
171 * 100x 0x00 r/o no acc
172 * 10x0 0x00 r/o no acc
173 * 1011 0x55 r/w no acc
178 .macro armv3_set_pte_ext wc_disable=1
179 str r1, [r0], #-2048 @ linux version
181 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
183 bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
184 bic r2, r2, #PTE_TYPE_MASK
185 orr r2, r2, #PTE_TYPE_SMALL
187 tst r3, #L_PTE_USER @ user?
188 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
190 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty?
191 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
193 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
197 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
198 tst r2, #PTE_CACHEABLE
199 bicne r2, r2, #PTE_BUFFERABLE
202 str r2, [r0] @ hardware version
207 * Xscale set_pte_ext translation, split into two halves to cope
208 * with work-arounds. r3 must be preserved by code between these
211 * Permission translation:
213 * 0xxx 00 no acc no acc
221 .macro xscale_set_pte_ext_prologue
222 str r1, [r0], #-2048 @ linux version
224 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
226 bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
227 orr r2, r2, #PTE_TYPE_EXT @ extended page
229 tst r3, #L_PTE_USER @ user?
230 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
232 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty?
233 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
234 @ combined with user -> user r/w
237 .macro xscale_set_pte_ext_epilogue
238 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
239 movne r2, #0 @ no -> fault
241 str r2, [r0] @ hardware version
243 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
244 mcr p15, 0, ip, c7, c10, 4 @ data write barrier