2 * linux/arch/arm/mm/proc-v6.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Modified by Catalin Marinas for noMMU support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This is the "shell" of the ARMv6 processor support.
13 #include <linux/init.h>
14 #include <linux/linkage.h>
15 #include <asm/assembler.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/hwcap.h>
18 #include <asm/pgtable-hwdef.h>
19 #include <asm/pgtable.h>
21 #include "proc-macros.S"
23 #define D_CACHE_LINE_SIZE 32
25 #define TTB_C (1 << 0)
26 #define TTB_S (1 << 1)
27 #define TTB_IMP (1 << 2)
28 #define TTB_RGN_NC (0 << 3)
29 #define TTB_RGN_WBWA (1 << 3)
30 #define TTB_RGN_WT (2 << 3)
31 #define TTB_RGN_WB (3 << 3)
34 #define TTB_FLAGS TTB_RGN_WBWA
35 #define PMD_FLAGS PMD_SECT_WB
37 #define TTB_FLAGS TTB_RGN_WBWA|TTB_S
38 #define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
41 ENTRY(cpu_v6_proc_init)
44 ENTRY(cpu_v6_proc_fin)
45 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
46 bic r0, r0, #0x1000 @ ...i............
47 bic r0, r0, #0x0006 @ .............ca.
48 mcr p15, 0, r0, c1, c0, 0 @ disable caches
54 * Perform a soft reset of the system. Put the CPU into the
55 * same state as it would be if it had been reset, and branch
56 * to what would be the reset vector.
58 * - loc - location to jump to for soft reset
67 * Idle the processor (eg, wait for interrupt).
69 * IRQs are already disabled.
73 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
74 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
77 ENTRY(cpu_v6_dcache_clean_area)
78 #ifndef TLB_CAN_READ_FROM_L1_CACHE
79 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
80 add r0, r0, #D_CACHE_LINE_SIZE
81 subs r1, r1, #D_CACHE_LINE_SIZE
87 * cpu_arm926_switch_mm(pgd_phys, tsk)
89 * Set the translation table base pointer to be pgd_phys
91 * - pgd_phys - physical address of new TTB
94 * - we are not using split page tables
96 ENTRY(cpu_v6_switch_mm)
99 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
100 orr r0, r0, #TTB_FLAGS
101 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
102 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
103 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
104 mcr p15, 0, r1, c13, c0, 1 @ set context ID
109 * cpu_v6_set_pte_ext(ptep, pte, ext)
111 * Set a level 2 translation table entry.
113 * - ptep - pointer to level 2 translation table entry
114 * (hardware version is stored at -1024 bytes)
115 * - pte - PTE value to store
116 * - ext - value for extended PTE bits
118 armv6_mt_table cpu_v6
120 ENTRY(cpu_v6_set_pte_ext)
122 armv6_set_pte_ext cpu_v6
128 .type cpu_v6_name, #object
130 .asciz "ARMv6-compatible processor"
131 .size cpu_v6_name, . - cpu_v6_name
133 .type cpu_pj4_name, #object
135 .asciz "Marvell PJ4 processor"
136 .size cpu_pj4_name, . - cpu_pj4_name
145 * Initialise TLB, Caches, and MMU state ready to switch the MMU
146 * on. Return in r0 the new CP15 C1 control register setting.
148 * We automatically detect if we have a Harvard cache, and use the
149 * Harvard cache control instructions insead of the unified cache
150 * control instructions.
152 * This should be able to cover all ARMv6 cores.
154 * It is assumed that:
155 * - cache type register is implemented
159 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
161 mcr p15, 0, r0, c1, c0, 1
165 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
166 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
167 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
168 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
170 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
171 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
172 orr r4, r4, #TTB_FLAGS
173 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
174 #endif /* CONFIG_MMU */
177 #ifdef CONFIG_CPU_ENDIAN_BE8
178 orr r6, r6, #1 << 25 @ big-endian page tables
180 mrc p15, 0, r0, c1, c0, 0 @ read control register
181 bic r0, r0, r5 @ clear bits them
182 orr r0, r0, r6 @ set them
183 mov pc, lr @ return to head.S:__ret
187 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
188 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
189 * 0 110 0011 1.00 .111 1101 < we want
191 .type v6_crval, #object
193 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
195 .type v6_processor_functions, #object
196 ENTRY(v6_processor_functions)
199 .word cpu_v6_proc_init
200 .word cpu_v6_proc_fin
203 .word cpu_v6_dcache_clean_area
204 .word cpu_v6_switch_mm
205 .word cpu_v6_set_pte_ext
206 .size v6_processor_functions, . - v6_processor_functions
208 .type cpu_arch_name, #object
211 .size cpu_arch_name, . - cpu_arch_name
213 .type cpu_elf_name, #object
216 .size cpu_elf_name, . - cpu_elf_name
219 .section ".proc.info.init", #alloc, #execinstr
222 * Match any ARMv6 processor core.
224 .type __v6_proc_info, #object
228 .long PMD_TYPE_SECT | \
229 PMD_SECT_AP_WRITE | \
232 .long PMD_TYPE_SECT | \
234 PMD_SECT_AP_WRITE | \
239 /* See also feat_v6_fixup() for HWCAP_TLS */
240 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
242 .long v6_processor_functions
246 .size __v6_proc_info, . - __v6_proc_info
248 .type __pj4_v6_proc_info, #object
252 .long PMD_TYPE_SECT | \
253 PMD_SECT_AP_WRITE | \
256 .long PMD_TYPE_SECT | \
258 PMD_SECT_AP_WRITE | \
263 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
265 .long v6_processor_functions
269 .size __pj4_v6_proc_info, . - __pj4_v6_proc_info