2 * linux/arch/arm/mm/proc-v6.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Modified by Catalin Marinas for noMMU support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This is the "shell" of the ARMv6 processor support.
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #define D_CACHE_LINE_SIZE 32
24 #define TTB_C (1 << 0)
25 #define TTB_S (1 << 1)
26 #define TTB_IMP (1 << 2)
27 #define TTB_RGN_NC (0 << 3)
28 #define TTB_RGN_WBWA (1 << 3)
29 #define TTB_RGN_WT (2 << 3)
30 #define TTB_RGN_WB (3 << 3)
33 #define TTB_FLAGS TTB_RGN_WBWA
35 #define TTB_FLAGS TTB_RGN_WBWA|TTB_S
38 ENTRY(cpu_v6_proc_init)
41 ENTRY(cpu_v6_proc_fin)
43 cpsid if @ disable interrupts
44 bl v6_flush_kern_cache_all
45 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
46 bic r0, r0, #0x1000 @ ...i............
47 bic r0, r0, #0x0006 @ .............ca.
48 mcr p15, 0, r0, c1, c0, 0 @ disable caches
54 * Perform a soft reset of the system. Put the CPU into the
55 * same state as it would be if it had been reset, and branch
56 * to what would be the reset vector.
58 * - loc - location to jump to for soft reset
69 * Idle the processor (eg, wait for interrupt).
71 * IRQs are already disabled.
74 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
77 ENTRY(cpu_v6_dcache_clean_area)
78 #ifndef TLB_CAN_READ_FROM_L1_CACHE
79 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
80 add r0, r0, #D_CACHE_LINE_SIZE
81 subs r1, r1, #D_CACHE_LINE_SIZE
87 * cpu_arm926_switch_mm(pgd_phys, tsk)
89 * Set the translation table base pointer to be pgd_phys
91 * - pgd_phys - physical address of new TTB
94 * - we are not using split page tables
96 ENTRY(cpu_v6_switch_mm)
99 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
100 orr r0, r0, #TTB_FLAGS
101 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
102 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
103 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
104 mcr p15, 0, r1, c13, c0, 1 @ set context ID
109 * cpu_v6_set_pte_ext(ptep, pte, ext)
111 * Set a level 2 translation table entry.
113 * - ptep - pointer to level 2 translation table entry
114 * (hardware version is stored at -1024 bytes)
115 * - pte - PTE value to store
116 * - ext - value for extended PTE bits
118 armv6_mt_table cpu_v6
120 ENTRY(cpu_v6_set_pte_ext)
122 armv6_set_pte_ext cpu_v6
130 .asciz "ARMv6-compatible processor"
133 .section ".text.init", #alloc, #execinstr
138 * Initialise TLB, Caches, and MMU state ready to switch the MMU
139 * on. Return in r0 the new CP15 C1 control register setting.
141 * We automatically detect if we have a Harvard cache, and use the
142 * Harvard cache control instructions insead of the unified cache
143 * control instructions.
145 * This should be able to cover all ARMv6 cores.
147 * It is assumed that:
148 * - cache type register is implemented
152 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
154 mcr p15, 0, r0, c1, c0, 1
158 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
159 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
160 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
161 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
163 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
164 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
165 orr r4, r4, #TTB_FLAGS
166 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
167 #endif /* CONFIG_MMU */
170 mrc p15, 0, r0, c1, c0, 0 @ read control register
171 bic r0, r0, r5 @ clear bits them
172 orr r0, r0, r6 @ set them
173 mov pc, lr @ return to head.S:__ret
177 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
178 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
179 * 0 110 0011 1.00 .111 1101 < we want
181 .type v6_crval, #object
183 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
185 .type v6_processor_functions, #object
186 ENTRY(v6_processor_functions)
189 .word cpu_v6_proc_init
190 .word cpu_v6_proc_fin
193 .word cpu_v6_dcache_clean_area
194 .word cpu_v6_switch_mm
195 .word cpu_v6_set_pte_ext
196 .size v6_processor_functions, . - v6_processor_functions
198 .type cpu_arch_name, #object
201 .size cpu_arch_name, . - cpu_arch_name
203 .type cpu_elf_name, #object
206 .size cpu_elf_name, . - cpu_elf_name
209 .section ".proc.info.init", #alloc, #execinstr
212 * Match any ARMv6 processor core.
214 .type __v6_proc_info, #object
218 .long PMD_TYPE_SECT | \
219 PMD_SECT_BUFFERABLE | \
220 PMD_SECT_CACHEABLE | \
221 PMD_SECT_AP_WRITE | \
223 .long PMD_TYPE_SECT | \
225 PMD_SECT_AP_WRITE | \
230 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
232 .long v6_processor_functions
236 .size __v6_proc_info, . - __v6_proc_info