2 * linux/arch/arm/mm/proc-v7.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv7 processor support.
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #define TTB_S (1 << 1)
23 #define TTB_RGN_NC (0 << 3)
24 #define TTB_RGN_OC_WBWA (1 << 3)
25 #define TTB_RGN_OC_WT (2 << 3)
26 #define TTB_RGN_OC_WB (3 << 3)
27 #define TTB_NOS (1 << 5)
28 #define TTB_IRGN_NC ((0 << 0) | (0 << 6))
29 #define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
30 #define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31 #define TTB_IRGN_WB ((1 << 0) | (1 << 6))
34 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
35 #define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB
36 #define PMD_FLAGS PMD_SECT_WB
38 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
39 #define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
40 #define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
43 ENTRY(cpu_v7_proc_init)
45 ENDPROC(cpu_v7_proc_init)
47 ENTRY(cpu_v7_proc_fin)
48 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
49 bic r0, r0, #0x1000 @ ...i............
50 bic r0, r0, #0x0006 @ .............ca.
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
53 ENDPROC(cpu_v7_proc_fin)
58 * Perform a soft reset of the system. Put the CPU into the
59 * same state as it would be if it had been reset, and branch
60 * to what would be the reset vector.
62 * - loc - location to jump to for soft reset
72 * Idle the processor (eg, wait for interrupt).
74 * IRQs are already disabled.
77 dsb @ WFI may enter a low-power mode
80 ENDPROC(cpu_v7_do_idle)
82 ENTRY(cpu_v7_dcache_clean_area)
83 #ifndef TLB_CAN_READ_FROM_L1_CACHE
84 dcache_line_size r2, r3
85 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
92 ENDPROC(cpu_v7_dcache_clean_area)
95 * cpu_v7_switch_mm(pgd_phys, tsk)
97 * Set the translation table base pointer to be pgd_phys
99 * - pgd_phys - physical address of new TTB
101 * It is assumed that:
102 * - we are not using split page tables
104 ENTRY(cpu_v7_switch_mm)
107 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
108 orr r0, r0, #TTB_FLAGS
109 #ifdef CONFIG_ARM_ERRATA_430973
110 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
112 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
114 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
116 mcr p15, 0, r1, c13, c0, 1 @ set context ID
120 ENDPROC(cpu_v7_switch_mm)
123 * cpu_v7_set_pte_ext(ptep, pte)
125 * Set a level 2 translation table entry.
127 * - ptep - pointer to level 2 translation table entry
128 * (hardware version is stored at -1024 bytes)
129 * - pte - PTE value to store
130 * - ext - value for extended PTE bits
132 ENTRY(cpu_v7_set_pte_ext)
134 ARM( str r1, [r0], #-2048 ) @ linux version
135 THUMB( str r1, [r0] ) @ linux version
136 THUMB( sub r0, r0, #2048 )
138 bic r3, r1, #0x000003f0
139 bic r3, r3, #PTE_TYPE_MASK
141 orr r3, r3, #PTE_EXT_AP0 | 2
144 orrne r3, r3, #PTE_EXT_TEX(1)
147 tstne r1, #L_PTE_DIRTY
148 orreq r3, r3, #PTE_EXT_APX
151 orrne r3, r3, #PTE_EXT_AP1
152 tstne r3, #PTE_EXT_APX
153 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
156 orreq r3, r3, #PTE_EXT_XN
159 tstne r1, #L_PTE_PRESENT
163 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
166 ENDPROC(cpu_v7_set_pte_ext)
169 .ascii "ARMv7 Processor"
177 * Initialise TLB, Caches, and MMU state ready to switch the MMU
178 * on. Return in r0 the new CP15 C1 control register setting.
180 * We automatically detect if we have a Harvard cache, and use the
181 * Harvard cache control instructions insead of the unified cache
182 * control instructions.
184 * This should be able to cover all ARMv7 cores.
186 * It is assumed that:
187 * - cache type register is implemented
191 mrc p15, 0, r0, c1, c0, 1
192 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
193 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
194 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
197 adr r12, __v7_setup_stack @ the local stack
198 stmia r12, {r0-r5, r7, r9, r11, lr}
199 bl v7_flush_dcache_all
200 ldmia r12, {r0-r5, r7, r9, r11, lr}
202 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
203 and r10, r0, #0xff000000 @ ARM?
206 and r5, r0, #0x00f00000 @ variant
207 and r6, r0, #0x0000000f @ revision
208 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
209 ubfx r0, r0, #4, #12 @ primary part number
211 /* Cortex-A8 Errata */
212 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
215 #ifdef CONFIG_ARM_ERRATA_430973
216 teq r5, #0x00100000 @ only present in r1p*
217 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
218 orreq r10, r10, #(1 << 6) @ set IBE to 1
219 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
221 #ifdef CONFIG_ARM_ERRATA_458693
222 teq r6, #0x20 @ only present in r2p0
223 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
224 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
225 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
226 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
228 #ifdef CONFIG_ARM_ERRATA_460075
229 teq r6, #0x20 @ only present in r2p0
230 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
232 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
233 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
237 /* Cortex-A9 Errata */
238 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
241 #ifdef CONFIG_ARM_ERRATA_742230
242 cmp r6, #0x22 @ only present up to r2p2
243 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
244 orrle r10, r10, #1 << 4 @ set bit #4
245 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
247 #ifdef CONFIG_ARM_ERRATA_742231
248 teq r6, #0x20 @ present in r2p0
249 teqne r6, #0x21 @ present in r2p1
250 teqne r6, #0x22 @ present in r2p2
251 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
252 orreq r10, r10, #1 << 12 @ set bit #12
253 orreq r10, r10, #1 << 22 @ set bit #22
254 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
259 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
263 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
264 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
265 orr r4, r4, #TTB_FLAGS
266 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
267 mov r10, #0x1f @ domains 0, 1 = manager
268 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
270 * Memory region attributes with SCTLR.TRE=1
273 * TR = PRRR[2n+1:2n] - memory type
274 * IR = NMRR[2n+1:2n] - inner cacheable property
275 * OR = NMRR[2n+17:2n+16] - outer cacheable property
279 * BUFFERABLE 001 10 00 00
280 * WRITETHROUGH 010 10 10 10
281 * WRITEBACK 011 10 11 11
283 * WRITEALLOC 111 10 01 01
285 * DEV_NONSHARED 100 01
291 * DS0 = PRRR[16] = 0 - device shareable property
292 * DS1 = PRRR[17] = 1 - device shareable property
293 * NS0 = PRRR[18] = 0 - normal shareable property
294 * NS1 = PRRR[19] = 1 - normal shareable property
295 * NOS = PRRR[24+n] = 1 - not outer shareable
297 ldr r5, =0xff0a81a8 @ PRRR
298 ldr r6, =0x40e040e0 @ NMRR
299 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
300 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
304 #ifdef CONFIG_CPU_ENDIAN_BE8
305 orr r6, r6, #1 << 25 @ big-endian page tables
307 mrc p15, 0, r0, c1, c0, 0 @ read control register
308 bic r0, r0, r5 @ clear bits them
309 orr r0, r0, r6 @ set them
310 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
311 mov pc, lr @ return to head.S:__ret
315 * TFR EV X F I D LR S
316 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
317 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
318 * 1 0 110 0011 1100 .111 1101 < we want
320 .type v7_crval, #object
322 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
325 .space 4 * 11 @ 11 registers
327 .type v7_processor_functions, #object
328 ENTRY(v7_processor_functions)
331 .word cpu_v7_proc_init
332 .word cpu_v7_proc_fin
335 .word cpu_v7_dcache_clean_area
336 .word cpu_v7_switch_mm
337 .word cpu_v7_set_pte_ext
338 .size v7_processor_functions, . - v7_processor_functions
340 .type cpu_arch_name, #object
343 .size cpu_arch_name, . - cpu_arch_name
345 .type cpu_elf_name, #object
348 .size cpu_elf_name, . - cpu_elf_name
351 .section ".proc.info.init", #alloc, #execinstr
353 .type __v7_ca9mp_proc_info, #object
354 __v7_ca9mp_proc_info:
355 .long 0x410fc090 @ Required ID value
356 .long 0xff0ffff0 @ Mask for ID
357 .long PMD_TYPE_SECT | \
358 PMD_SECT_AP_WRITE | \
361 .long PMD_TYPE_SECT | \
363 PMD_SECT_AP_WRITE | \
368 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
370 .long v7_processor_functions
374 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
377 * Match any ARMv7 processor core.
379 .type __v7_proc_info, #object
381 .long 0x000f0000 @ Required ID value
382 .long 0x000f0000 @ Mask for ID
383 .long PMD_TYPE_SECT | \
384 PMD_SECT_AP_WRITE | \
387 .long PMD_TYPE_SECT | \
389 PMD_SECT_AP_WRITE | \
394 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
396 .long v7_processor_functions
400 .size __v7_proc_info, . - __v7_proc_info