2 * linux/arch/arm/mm/proc-v7.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv7 processor support.
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #define TTB_S (1 << 1)
23 #define TTB_RGN_NC (0 << 3)
24 #define TTB_RGN_OC_WBWA (1 << 3)
25 #define TTB_RGN_OC_WT (2 << 3)
26 #define TTB_RGN_OC_WB (3 << 3)
27 #define TTB_NOS (1 << 5)
28 #define TTB_IRGN_NC ((0 << 0) | (0 << 6))
29 #define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
30 #define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31 #define TTB_IRGN_WB ((1 << 0) | (1 << 6))
33 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
34 #define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
35 #define PMD_FLAGS_UP PMD_SECT_WB
37 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
38 #define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
39 #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
41 ENTRY(cpu_v7_proc_init)
43 ENDPROC(cpu_v7_proc_init)
45 ENTRY(cpu_v7_proc_fin)
46 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
47 bic r0, r0, #0x1000 @ ...i............
48 bic r0, r0, #0x0006 @ .............ca.
49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 ENDPROC(cpu_v7_proc_fin)
56 * Perform a soft reset of the system. Put the CPU into the
57 * same state as it would be if it had been reset, and branch
58 * to what would be the reset vector.
60 * - loc - location to jump to for soft reset
70 * Idle the processor (eg, wait for interrupt).
72 * IRQs are already disabled.
75 dsb @ WFI may enter a low-power mode
78 ENDPROC(cpu_v7_do_idle)
80 ENTRY(cpu_v7_dcache_clean_area)
81 #ifndef TLB_CAN_READ_FROM_L1_CACHE
82 dcache_line_size r2, r3
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
90 ENDPROC(cpu_v7_dcache_clean_area)
93 * cpu_v7_switch_mm(pgd_phys, tsk)
95 * Set the translation table base pointer to be pgd_phys
97 * - pgd_phys - physical address of new TTB
100 * - we are not using split page tables
102 ENTRY(cpu_v7_switch_mm)
105 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
106 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
107 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
108 #ifdef CONFIG_ARM_ERRATA_430973
109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
111 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
113 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
115 mcr p15, 0, r1, c13, c0, 1 @ set context ID
119 ENDPROC(cpu_v7_switch_mm)
122 * cpu_v7_set_pte_ext(ptep, pte)
124 * Set a level 2 translation table entry.
126 * - ptep - pointer to level 2 translation table entry
127 * (hardware version is stored at +2048 bytes)
128 * - pte - PTE value to store
129 * - ext - value for extended PTE bits
131 ENTRY(cpu_v7_set_pte_ext)
133 str r1, [r0] @ linux version
135 bic r3, r1, #0x000003f0
136 bic r3, r3, #PTE_TYPE_MASK
138 orr r3, r3, #PTE_EXT_AP0 | 2
141 orrne r3, r3, #PTE_EXT_TEX(1)
143 eor r1, r1, #L_PTE_DIRTY
144 tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
145 orrne r3, r3, #PTE_EXT_APX
148 orrne r3, r3, #PTE_EXT_AP1
149 #ifdef CONFIG_CPU_USE_DOMAINS
150 @ allow kernel read/write access to read-only user pages
151 tstne r3, #PTE_EXT_APX
152 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
156 orrne r3, r3, #PTE_EXT_XN
159 tstne r1, #L_PTE_PRESENT
162 ARM( str r3, [r0, #2048]! )
163 THUMB( add r0, r0, #2048 )
164 THUMB( str r3, [r0] )
165 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
168 ENDPROC(cpu_v7_set_pte_ext)
171 .ascii "ARMv7 Processor"
179 * Initialise TLB, Caches, and MMU state ready to switch the MMU
180 * on. Return in r0 the new CP15 C1 control register setting.
182 * We automatically detect if we have a Harvard cache, and use the
183 * Harvard cache control instructions insead of the unified cache
184 * control instructions.
186 * This should be able to cover all ARMv7 cores.
188 * It is assumed that:
189 * - cache type register is implemented
193 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
194 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
195 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
196 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
197 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
200 adr r12, __v7_setup_stack @ the local stack
201 stmia r12, {r0-r5, r7, r9, r11, lr}
202 bl v7_flush_dcache_all
203 ldmia r12, {r0-r5, r7, r9, r11, lr}
205 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
206 and r10, r0, #0xff000000 @ ARM?
209 and r5, r0, #0x00f00000 @ variant
210 and r6, r0, #0x0000000f @ revision
211 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
212 ubfx r0, r0, #4, #12 @ primary part number
214 /* Cortex-A8 Errata */
215 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
218 #ifdef CONFIG_ARM_ERRATA_430973
219 teq r5, #0x00100000 @ only present in r1p*
220 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
221 orreq r10, r10, #(1 << 6) @ set IBE to 1
222 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
224 #ifdef CONFIG_ARM_ERRATA_458693
225 teq r6, #0x20 @ only present in r2p0
226 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
227 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
228 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
229 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
231 #ifdef CONFIG_ARM_ERRATA_460075
232 teq r6, #0x20 @ only present in r2p0
233 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
235 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
236 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
240 /* Cortex-A9 Errata */
241 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
244 #ifdef CONFIG_ARM_ERRATA_742230
245 cmp r6, #0x22 @ only present up to r2p2
246 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
247 orrle r10, r10, #1 << 4 @ set bit #4
248 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
250 #ifdef CONFIG_ARM_ERRATA_742231
251 teq r6, #0x20 @ present in r2p0
252 teqne r6, #0x21 @ present in r2p1
253 teqne r6, #0x22 @ present in r2p2
254 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
255 orreq r10, r10, #1 << 12 @ set bit #12
256 orreq r10, r10, #1 << 22 @ set bit #22
257 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
259 #ifdef CONFIG_ARM_ERRATA_743622
260 teq r6, #0x20 @ present in r2p0
261 teqne r6, #0x21 @ present in r2p1
262 teqne r6, #0x22 @ present in r2p2
263 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
264 orreq r10, r10, #1 << 6 @ set bit #6
265 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
267 #ifdef CONFIG_ARM_ERRATA_751472
268 cmp r6, #0x30 @ present prior to r3p0
269 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
270 orrlt r10, r10, #1 << 11 @ set bit #11
271 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
276 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
280 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
281 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
282 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
283 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
284 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
286 * Memory region attributes with SCTLR.TRE=1
289 * TR = PRRR[2n+1:2n] - memory type
290 * IR = NMRR[2n+1:2n] - inner cacheable property
291 * OR = NMRR[2n+17:2n+16] - outer cacheable property
295 * BUFFERABLE 001 10 00 00
296 * WRITETHROUGH 010 10 10 10
297 * WRITEBACK 011 10 11 11
299 * WRITEALLOC 111 10 01 01
301 * DEV_NONSHARED 100 01
307 * DS0 = PRRR[16] = 0 - device shareable property
308 * DS1 = PRRR[17] = 1 - device shareable property
309 * NS0 = PRRR[18] = 0 - normal shareable property
310 * NS1 = PRRR[19] = 1 - normal shareable property
311 * NOS = PRRR[24+n] = 1 - not outer shareable
313 ldr r5, =0xff0a81a8 @ PRRR
314 ldr r6, =0x40e040e0 @ NMRR
315 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
316 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
320 #ifdef CONFIG_CPU_ENDIAN_BE8
321 orr r6, r6, #1 << 25 @ big-endian page tables
323 #ifdef CONFIG_SWP_EMULATE
324 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
325 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
327 mrc p15, 0, r0, c1, c0, 0 @ read control register
328 bic r0, r0, r5 @ clear bits them
329 orr r0, r0, r6 @ set them
330 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
331 mov pc, lr @ return to head.S:__ret
335 * TFR EV X F I D LR S
336 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
337 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
338 * 1 0 110 0011 1100 .111 1101 < we want
340 .type v7_crval, #object
342 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
345 .space 4 * 11 @ 11 registers
349 .type v7_processor_functions, #object
350 ENTRY(v7_processor_functions)
353 .word cpu_v7_proc_init
354 .word cpu_v7_proc_fin
357 .word cpu_v7_dcache_clean_area
358 .word cpu_v7_switch_mm
359 .word cpu_v7_set_pte_ext
360 .size v7_processor_functions, . - v7_processor_functions
364 .type cpu_arch_name, #object
367 .size cpu_arch_name, . - cpu_arch_name
369 .type cpu_elf_name, #object
372 .size cpu_elf_name, . - cpu_elf_name
375 .section ".proc.info.init", #alloc, #execinstr
377 .type __v7_ca9mp_proc_info, #object
378 __v7_ca9mp_proc_info:
379 .long 0x410fc090 @ Required ID value
380 .long 0xff0ffff0 @ Mask for ID
383 PMD_SECT_AP_WRITE | \
388 PMD_SECT_AP_WRITE | \
391 .long PMD_TYPE_SECT | \
393 PMD_SECT_AP_WRITE | \
395 W(b) __v7_ca9mp_setup
398 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
400 .long v7_processor_functions
404 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
407 * Match any ARMv7 processor core.
409 .type __v7_proc_info, #object
411 .long 0x000f0000 @ Required ID value
412 .long 0x000f0000 @ Mask for ID
415 PMD_SECT_AP_WRITE | \
420 PMD_SECT_AP_WRITE | \
423 .long PMD_TYPE_SECT | \
425 PMD_SECT_AP_WRITE | \
430 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
432 .long v7_processor_functions
436 .size __v7_proc_info, . - __v7_proc_info