2 * linux/arch/arm/mm/proc-xscale.S
4 * Author: Nicolas Pitre
5 * Created: November 2000
6 * Copyright: (C) 2000, 2001 MontaVista Software Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * MMU functions for the Intel XScale CPUs
15 * some contributions by Brett Gaines <brett.w.gaines@intel.com>
16 * Copyright 2001 by Intel Corp.
19 * Completely revisited, many important fixes
20 * Nicolas Pitre <nico@fluxnic.net>
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <asm/assembler.h>
26 #include <asm/hwcap.h>
27 #include <asm/pgtable.h>
28 #include <asm/pgtable-hwdef.h>
30 #include <asm/ptrace.h>
31 #include "proc-macros.S"
34 * This is the maximum size of an area which will be flushed. If the area
35 * is larger than this, then we flush the whole cache
37 #define MAX_AREA_SIZE 32768
40 * the cache line size of the I and D cache
42 #define CACHELINESIZE 32
45 * the size of the data cache
47 #define CACHESIZE 32768
50 * Virtual address used to allocate the cache when flushed
52 * This must be an address range which is _never_ used. It should
53 * apparently have a mapping in the corresponding page table for
54 * compatibility with future CPUs that _could_ require it. For instance we
57 * This must be aligned on a 2*CACHESIZE boundary. The code selects one of
58 * the 2 areas in alternance each time the clean_d_cache macro is used.
59 * Without this the XScale core exhibits cache eviction problems and no one
62 * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
64 #define CLEAN_ADDR 0xfffe0000
67 * This macro is used to wait for a CP15 write and is needed
68 * when we have to ensure that the last operation to the co-pro
69 * was completed before continuing with operation.
72 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
73 mov \rd, \rd @ wait for completion
74 sub pc, pc, #4 @ flush instruction pipeline
77 .macro cpwait_ret, lr, rd
78 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
79 sub pc, \lr, \rd, LSR #32 @ wait for completion and
80 @ flush instruction pipeline
84 * This macro cleans the entire dcache using line allocate.
85 * The main loop has been unrolled to reduce loop overhead.
86 * rd and rs are two scratch registers.
88 .macro clean_d_cache, rd, rs
91 eor \rd, \rd, #CACHESIZE
93 add \rs, \rd, #CACHESIZE
94 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
95 add \rd, \rd, #CACHELINESIZE
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
97 add \rd, \rd, #CACHELINESIZE
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
99 add \rd, \rd, #CACHELINESIZE
100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
101 add \rd, \rd, #CACHELINESIZE
107 clean_addr: .word CLEAN_ADDR
112 * cpu_xscale_proc_init()
114 * Nothing too exciting at the moment
116 ENTRY(cpu_xscale_proc_init)
117 @ enable write buffer coalescing. Some bootloader disable it
118 mrc p15, 0, r1, c1, c0, 1
120 mcr p15, 0, r1, c1, c0, 1
124 * cpu_xscale_proc_fin()
126 ENTRY(cpu_xscale_proc_fin)
128 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
130 bl xscale_flush_kern_cache_all @ clean caches
131 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
132 bic r0, r0, #0x1800 @ ...IZ...........
133 bic r0, r0, #0x0006 @ .............CA.
134 mcr p15, 0, r0, c1, c0, 0 @ disable caches
138 * cpu_xscale_reset(loc)
140 * Perform a soft reset of the system. Put the CPU into the
141 * same state as it would be if it had been reset, and branch
142 * to what would be the reset vector.
144 * loc: location to jump to for soft reset
146 * Beware PXA270 erratum E7.
149 ENTRY(cpu_xscale_reset)
150 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
151 msr cpsr_c, r1 @ reset CPSR
152 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
153 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
154 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
155 bic r1, r1, #0x0086 @ ........B....CA.
156 bic r1, r1, #0x3900 @ ..VIZ..S........
157 sub pc, pc, #4 @ flush pipeline
158 @ *** cache line aligned ***
159 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
160 bic r1, r1, #0x0001 @ ...............M
161 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
162 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
163 @ CAUTION: MMU turned off from this point. We count on the pipeline
164 @ already containing those two last instructions to survive.
165 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
169 * cpu_xscale_do_idle()
171 * Cause the processor to idle
173 * For now we do nothing but go to idle mode for every case
175 * XScale supports clock switching, but using idle mode support
176 * allows external hardware to react to system state changes.
180 ENTRY(cpu_xscale_do_idle)
182 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
185 /* ================================= CACHE ================================ */
188 * flush_user_cache_all()
190 * Invalidate all cache entries in a particular address
193 ENTRY(xscale_flush_user_cache_all)
197 * flush_kern_cache_all()
199 * Clean and invalidate the entire cache.
201 ENTRY(xscale_flush_kern_cache_all)
207 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
208 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
212 * flush_user_cache_range(start, end, vm_flags)
214 * Invalidate a range of cache entries in the specified
217 * - start - start address (may not be aligned)
218 * - end - end address (exclusive, may not be aligned)
219 * - vma - vma_area_struct describing address space
222 ENTRY(xscale_flush_user_cache_range)
224 sub r3, r1, r0 @ calculate total size
225 cmp r3, #MAX_AREA_SIZE
226 bhs __flush_whole_cache
229 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
230 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
231 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
232 add r0, r0, #CACHELINESIZE
236 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
237 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
241 * coherent_kern_range(start, end)
243 * Ensure coherency between the Icache and the Dcache in the
244 * region described by start. If you have non-snooping
245 * Harvard caches, you need to implement this function.
247 * - start - virtual start address
248 * - end - virtual end address
250 * Note: single I-cache line invalidation isn't used here since
251 * it also trashes the mini I-cache used by JTAG debuggers.
253 ENTRY(xscale_coherent_kern_range)
254 bic r0, r0, #CACHELINESIZE - 1
255 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
256 add r0, r0, #CACHELINESIZE
260 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
261 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
265 * coherent_user_range(start, end)
267 * Ensure coherency between the Icache and the Dcache in the
268 * region described by start. If you have non-snooping
269 * Harvard caches, you need to implement this function.
271 * - start - virtual start address
272 * - end - virtual end address
274 ENTRY(xscale_coherent_user_range)
275 bic r0, r0, #CACHELINESIZE - 1
276 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
277 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
278 add r0, r0, #CACHELINESIZE
282 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
283 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
287 * flush_kern_dcache_area(void *addr, size_t size)
289 * Ensure no D cache aliasing occurs, either with itself or
292 * - addr - kernel address
293 * - size - region size
295 ENTRY(xscale_flush_kern_dcache_area)
297 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
298 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
299 add r0, r0, #CACHELINESIZE
303 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
304 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
308 * dma_inv_range(start, end)
310 * Invalidate (discard) the specified virtual address range.
311 * May not write back any entries. If 'start' or 'end'
312 * are not cache line aligned, those lines must be written
315 * - start - virtual start address
316 * - end - virtual end address
318 xscale_dma_inv_range:
319 tst r0, #CACHELINESIZE - 1
320 bic r0, r0, #CACHELINESIZE - 1
321 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
322 tst r1, #CACHELINESIZE - 1
323 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
324 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
325 add r0, r0, #CACHELINESIZE
328 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
332 * dma_clean_range(start, end)
334 * Clean the specified virtual address range.
336 * - start - virtual start address
337 * - end - virtual end address
339 xscale_dma_clean_range:
340 bic r0, r0, #CACHELINESIZE - 1
341 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
342 add r0, r0, #CACHELINESIZE
345 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
349 * dma_flush_range(start, end)
351 * Clean and invalidate the specified virtual address range.
353 * - start - virtual start address
354 * - end - virtual end address
356 ENTRY(xscale_dma_flush_range)
357 bic r0, r0, #CACHELINESIZE - 1
358 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
359 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
360 add r0, r0, #CACHELINESIZE
363 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
367 * dma_map_area(start, size, dir)
368 * - start - kernel virtual start address
369 * - size - size of region
370 * - dir - DMA direction
372 ENTRY(xscale_dma_map_area)
374 cmp r2, #DMA_TO_DEVICE
375 beq xscale_dma_clean_range
376 bcs xscale_dma_inv_range
377 b xscale_dma_flush_range
378 ENDPROC(xscale_dma_map_area)
381 * dma_map_area(start, size, dir)
382 * - start - kernel virtual start address
383 * - size - size of region
384 * - dir - DMA direction
386 ENTRY(xscale_dma_a0_map_area)
388 teq r2, #DMA_TO_DEVICE
389 beq xscale_dma_clean_range
390 b xscale_dma_flush_range
391 ENDPROC(xscsale_dma_a0_map_area)
394 * dma_unmap_area(start, size, dir)
395 * - start - kernel virtual start address
396 * - size - size of region
397 * - dir - DMA direction
399 ENTRY(xscale_dma_unmap_area)
401 ENDPROC(xscale_dma_unmap_area)
403 ENTRY(xscale_cache_fns)
404 .long xscale_flush_kern_cache_all
405 .long xscale_flush_user_cache_all
406 .long xscale_flush_user_cache_range
407 .long xscale_coherent_kern_range
408 .long xscale_coherent_user_range
409 .long xscale_flush_kern_dcache_area
410 .long xscale_dma_map_area
411 .long xscale_dma_unmap_area
412 .long xscale_dma_flush_range
415 * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
416 * clear the dirty bits, which means that if we invalidate a dirty line,
417 * the dirty data can still be written back to external memory later on.
419 * The recommended workaround is to always do a clean D-cache line before
420 * doing an invalidate D-cache line, so on the affected processors,
421 * dma_inv_range() is implemented as dma_flush_range().
423 * See erratum #25 of "Intel 80200 Processor Specification Update",
424 * revision January 22, 2003, available at:
425 * http://www.intel.com/design/iio/specupdt/273415.htm
427 ENTRY(xscale_80200_A0_A1_cache_fns)
428 .long xscale_flush_kern_cache_all
429 .long xscale_flush_user_cache_all
430 .long xscale_flush_user_cache_range
431 .long xscale_coherent_kern_range
432 .long xscale_coherent_user_range
433 .long xscale_flush_kern_dcache_area
434 .long xscale_dma_a0_map_area
435 .long xscale_dma_unmap_area
436 .long xscale_dma_flush_range
438 ENTRY(cpu_xscale_dcache_clean_area)
439 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
440 add r0, r0, #CACHELINESIZE
441 subs r1, r1, #CACHELINESIZE
445 /* =============================== PageTable ============================== */
448 * cpu_xscale_switch_mm(pgd)
450 * Set the translation base pointer to be as described by pgd.
452 * pgd: new page tables
455 ENTRY(cpu_xscale_switch_mm)
457 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
458 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
459 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
460 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
464 * cpu_xscale_set_pte_ext(ptep, pte, ext)
466 * Set a PTE and flush it out
468 * Errata 40: must set memory to write-through for user read-only pages.
471 .long 0x00 @ L_PTE_MT_UNCACHED
472 .long PTE_BUFFERABLE @ L_PTE_MT_BUFFERABLE
473 .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
474 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
475 .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
477 .long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE
478 .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
480 .long PTE_BUFFERABLE @ L_PTE_MT_DEV_WC
482 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
483 .long 0x00 @ L_PTE_MT_DEV_NONSHARED
489 ENTRY(cpu_xscale_set_pte_ext)
490 xscale_set_pte_ext_prologue
493 @ Erratum 40: must set memory to write-through for user read-only pages
495 and ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_WRITE) & ~(4 << 2)
496 teq ip, #L_PTE_MT_WRITEBACK | L_PTE_USER
498 moveq r1, #L_PTE_MT_WRITETHROUGH
499 and r1, r1, #L_PTE_MT_MASK
500 adr ip, cpu_xscale_mt_table
505 xscale_set_pte_ext_epilogue
515 .type __xscale_setup, #function
517 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
518 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
519 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
520 mov r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
521 orr r0, r0, #1 << 13 @ Its undefined whether this
522 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
526 mrc p15, 0, r0, c1, c0, 0 @ get control register
530 .size __xscale_setup, . - __xscale_setup
534 * .RVI ZFRS BLDP WCAM
535 * ..11 1.01 .... .101
538 .type xscale_crval, #object
540 crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
545 * Purpose : Function pointers used to access above functions - all calls
549 .type xscale_processor_functions, #object
550 ENTRY(xscale_processor_functions)
551 .word v5t_early_abort
553 .word cpu_xscale_proc_init
554 .word cpu_xscale_proc_fin
555 .word cpu_xscale_reset
556 .word cpu_xscale_do_idle
557 .word cpu_xscale_dcache_clean_area
558 .word cpu_xscale_switch_mm
559 .word cpu_xscale_set_pte_ext
560 .size xscale_processor_functions, . - xscale_processor_functions
564 .type cpu_arch_name, #object
567 .size cpu_arch_name, . - cpu_arch_name
569 .type cpu_elf_name, #object
572 .size cpu_elf_name, . - cpu_elf_name
574 .type cpu_80200_A0_A1_name, #object
575 cpu_80200_A0_A1_name:
576 .asciz "XScale-80200 A0/A1"
577 .size cpu_80200_A0_A1_name, . - cpu_80200_A0_A1_name
579 .type cpu_80200_name, #object
581 .asciz "XScale-80200"
582 .size cpu_80200_name, . - cpu_80200_name
584 .type cpu_80219_name, #object
586 .asciz "XScale-80219"
587 .size cpu_80219_name, . - cpu_80219_name
589 .type cpu_8032x_name, #object
591 .asciz "XScale-IOP8032x Family"
592 .size cpu_8032x_name, . - cpu_8032x_name
594 .type cpu_8033x_name, #object
596 .asciz "XScale-IOP8033x Family"
597 .size cpu_8033x_name, . - cpu_8033x_name
599 .type cpu_pxa250_name, #object
601 .asciz "XScale-PXA250"
602 .size cpu_pxa250_name, . - cpu_pxa250_name
604 .type cpu_pxa210_name, #object
606 .asciz "XScale-PXA210"
607 .size cpu_pxa210_name, . - cpu_pxa210_name
609 .type cpu_ixp42x_name, #object
611 .asciz "XScale-IXP42x Family"
612 .size cpu_ixp42x_name, . - cpu_ixp42x_name
614 .type cpu_ixp43x_name, #object
616 .asciz "XScale-IXP43x Family"
617 .size cpu_ixp43x_name, . - cpu_ixp43x_name
619 .type cpu_ixp46x_name, #object
621 .asciz "XScale-IXP46x Family"
622 .size cpu_ixp46x_name, . - cpu_ixp46x_name
624 .type cpu_ixp2400_name, #object
626 .asciz "XScale-IXP2400"
627 .size cpu_ixp2400_name, . - cpu_ixp2400_name
629 .type cpu_ixp2800_name, #object
631 .asciz "XScale-IXP2800"
632 .size cpu_ixp2800_name, . - cpu_ixp2800_name
634 .type cpu_pxa255_name, #object
636 .asciz "XScale-PXA255"
637 .size cpu_pxa255_name, . - cpu_pxa255_name
639 .type cpu_pxa270_name, #object
641 .asciz "XScale-PXA270"
642 .size cpu_pxa270_name, . - cpu_pxa270_name
646 .section ".proc.info.init", #alloc, #execinstr
648 .type __80200_A0_A1_proc_info,#object
649 __80200_A0_A1_proc_info:
652 .long PMD_TYPE_SECT | \
653 PMD_SECT_BUFFERABLE | \
654 PMD_SECT_CACHEABLE | \
655 PMD_SECT_AP_WRITE | \
657 .long PMD_TYPE_SECT | \
658 PMD_SECT_AP_WRITE | \
663 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
665 .long xscale_processor_functions
667 .long xscale_mc_user_fns
668 .long xscale_80200_A0_A1_cache_fns
669 .size __80200_A0_A1_proc_info, . - __80200_A0_A1_proc_info
671 .type __80200_proc_info,#object
675 .long PMD_TYPE_SECT | \
676 PMD_SECT_BUFFERABLE | \
677 PMD_SECT_CACHEABLE | \
678 PMD_SECT_AP_WRITE | \
680 .long PMD_TYPE_SECT | \
681 PMD_SECT_AP_WRITE | \
686 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
688 .long xscale_processor_functions
690 .long xscale_mc_user_fns
691 .long xscale_cache_fns
692 .size __80200_proc_info, . - __80200_proc_info
694 .type __80219_proc_info,#object
698 .long PMD_TYPE_SECT | \
699 PMD_SECT_BUFFERABLE | \
700 PMD_SECT_CACHEABLE | \
701 PMD_SECT_AP_WRITE | \
703 .long PMD_TYPE_SECT | \
704 PMD_SECT_AP_WRITE | \
709 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
711 .long xscale_processor_functions
713 .long xscale_mc_user_fns
714 .long xscale_cache_fns
715 .size __80219_proc_info, . - __80219_proc_info
717 .type __8032x_proc_info,#object
721 .long PMD_TYPE_SECT | \
722 PMD_SECT_BUFFERABLE | \
723 PMD_SECT_CACHEABLE | \
724 PMD_SECT_AP_WRITE | \
726 .long PMD_TYPE_SECT | \
727 PMD_SECT_AP_WRITE | \
732 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
734 .long xscale_processor_functions
736 .long xscale_mc_user_fns
737 .long xscale_cache_fns
738 .size __8032x_proc_info, . - __8032x_proc_info
740 .type __8033x_proc_info,#object
744 .long PMD_TYPE_SECT | \
745 PMD_SECT_BUFFERABLE | \
746 PMD_SECT_CACHEABLE | \
747 PMD_SECT_AP_WRITE | \
749 .long PMD_TYPE_SECT | \
750 PMD_SECT_AP_WRITE | \
755 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
757 .long xscale_processor_functions
759 .long xscale_mc_user_fns
760 .long xscale_cache_fns
761 .size __8033x_proc_info, . - __8033x_proc_info
763 .type __pxa250_proc_info,#object
767 .long PMD_TYPE_SECT | \
768 PMD_SECT_BUFFERABLE | \
769 PMD_SECT_CACHEABLE | \
770 PMD_SECT_AP_WRITE | \
772 .long PMD_TYPE_SECT | \
773 PMD_SECT_AP_WRITE | \
778 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
779 .long cpu_pxa250_name
780 .long xscale_processor_functions
782 .long xscale_mc_user_fns
783 .long xscale_cache_fns
784 .size __pxa250_proc_info, . - __pxa250_proc_info
786 .type __pxa210_proc_info,#object
790 .long PMD_TYPE_SECT | \
791 PMD_SECT_BUFFERABLE | \
792 PMD_SECT_CACHEABLE | \
793 PMD_SECT_AP_WRITE | \
795 .long PMD_TYPE_SECT | \
796 PMD_SECT_AP_WRITE | \
801 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
802 .long cpu_pxa210_name
803 .long xscale_processor_functions
805 .long xscale_mc_user_fns
806 .long xscale_cache_fns
807 .size __pxa210_proc_info, . - __pxa210_proc_info
809 .type __ixp2400_proc_info, #object
813 .long PMD_TYPE_SECT | \
814 PMD_SECT_BUFFERABLE | \
815 PMD_SECT_CACHEABLE | \
816 PMD_SECT_AP_WRITE | \
818 .long PMD_TYPE_SECT | \
819 PMD_SECT_AP_WRITE | \
824 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
825 .long cpu_ixp2400_name
826 .long xscale_processor_functions
828 .long xscale_mc_user_fns
829 .long xscale_cache_fns
830 .size __ixp2400_proc_info, . - __ixp2400_proc_info
832 .type __ixp2800_proc_info, #object
836 .long PMD_TYPE_SECT | \
837 PMD_SECT_BUFFERABLE | \
838 PMD_SECT_CACHEABLE | \
839 PMD_SECT_AP_WRITE | \
841 .long PMD_TYPE_SECT | \
842 PMD_SECT_AP_WRITE | \
847 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
848 .long cpu_ixp2800_name
849 .long xscale_processor_functions
851 .long xscale_mc_user_fns
852 .long xscale_cache_fns
853 .size __ixp2800_proc_info, . - __ixp2800_proc_info
855 .type __ixp42x_proc_info, #object
859 .long PMD_TYPE_SECT | \
860 PMD_SECT_BUFFERABLE | \
861 PMD_SECT_CACHEABLE | \
862 PMD_SECT_AP_WRITE | \
864 .long PMD_TYPE_SECT | \
865 PMD_SECT_AP_WRITE | \
870 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
871 .long cpu_ixp42x_name
872 .long xscale_processor_functions
874 .long xscale_mc_user_fns
875 .long xscale_cache_fns
876 .size __ixp42x_proc_info, . - __ixp42x_proc_info
878 .type __ixp43x_proc_info, #object
882 .long PMD_TYPE_SECT | \
883 PMD_SECT_BUFFERABLE | \
884 PMD_SECT_CACHEABLE | \
885 PMD_SECT_AP_WRITE | \
887 .long PMD_TYPE_SECT | \
888 PMD_SECT_AP_WRITE | \
893 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
894 .long cpu_ixp43x_name
895 .long xscale_processor_functions
897 .long xscale_mc_user_fns
898 .long xscale_cache_fns
899 .size __ixp43x_proc_info, . - __ixp43x_proc_info
901 .type __ixp46x_proc_info, #object
905 .long PMD_TYPE_SECT | \
906 PMD_SECT_BUFFERABLE | \
907 PMD_SECT_CACHEABLE | \
908 PMD_SECT_AP_WRITE | \
910 .long PMD_TYPE_SECT | \
911 PMD_SECT_AP_WRITE | \
916 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
917 .long cpu_ixp46x_name
918 .long xscale_processor_functions
920 .long xscale_mc_user_fns
921 .long xscale_cache_fns
922 .size __ixp46x_proc_info, . - __ixp46x_proc_info
924 .type __pxa255_proc_info,#object
928 .long PMD_TYPE_SECT | \
929 PMD_SECT_BUFFERABLE | \
930 PMD_SECT_CACHEABLE | \
931 PMD_SECT_AP_WRITE | \
933 .long PMD_TYPE_SECT | \
934 PMD_SECT_AP_WRITE | \
939 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
940 .long cpu_pxa255_name
941 .long xscale_processor_functions
943 .long xscale_mc_user_fns
944 .long xscale_cache_fns
945 .size __pxa255_proc_info, . - __pxa255_proc_info
947 .type __pxa270_proc_info,#object
951 .long PMD_TYPE_SECT | \
952 PMD_SECT_BUFFERABLE | \
953 PMD_SECT_CACHEABLE | \
954 PMD_SECT_AP_WRITE | \
956 .long PMD_TYPE_SECT | \
957 PMD_SECT_AP_WRITE | \
962 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
963 .long cpu_pxa270_name
964 .long xscale_processor_functions
966 .long xscale_mc_user_fns
967 .long xscale_cache_fns
968 .size __pxa270_proc_info, . - __pxa270_proc_info